CN108233898A - A kind of multi-clock dynamic switching circuit - Google Patents

A kind of multi-clock dynamic switching circuit Download PDF

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Publication number
CN108233898A
CN108233898A CN201711391540.7A CN201711391540A CN108233898A CN 108233898 A CN108233898 A CN 108233898A CN 201711391540 A CN201711391540 A CN 201711391540A CN 108233898 A CN108233898 A CN 108233898A
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clock
gate
low
signal
slow
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CN108233898B (en
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白永强
罗旻
鲍东山
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NUFRONT SOFTWARE TECHNOLOGY Co Ltd
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NUFRONT SOFTWARE TECHNOLOGY Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

This application discloses a kind of multi-clock dynamic switching circuit, the application the technical solution adopted is that：Input end of clock includes Slow Clock, reference clock, low-speed clock, middling speed clock and high-frequency clock；Output terminal of clock includes the first output clock, the second output clock and third output clock, includes between input end of clock and output terminal of clock：Slow Clock switching sub-circuit, reference clock switching sub-circuit, low-speed clock switching sub-circuit, middling speed clock switching sub-circuit, high-frequency clock switching sub-circuit；Result through the output of above-mentioned sub-circuit carries out or operation obtains output clock.Technical solution using the present invention being capable of the required high-frequency clock of impulse- free robustness switching at runtime SoC chip, middling speed clock, low-speed clock, reference clock and Slow Clock simultaneously generate synchronous clock domains clock phase indication signal and state, meet clock switching needs of the SoC chip between high-performance scene and multiple low-power consumption scenes.

Description

A kind of multi-clock dynamic switching circuit
Technical field
The present invention relates to clock signal switching more particularly to a kind of multi-clock dynamic switching circuits.
Background technology
SoC chip usually has high-frequency clock working region, low-speed clock working region, and synchronous high/low speed clock leads to The clock edge that phase indication signal mark high-frequency clock and low-speed clock is often needed to be aligned, in order to logic and timing Design. Meanwhile SoC chip high-performance and low-power consumption in order to balance, synchronous clock domains high-frequency clock, low-speed clock are needed, with asynchronous clock Domain reference clock, the switching at runtime between Slow Clock.
Traditional burr-free clock dynamic switching circuit only accounts for the switching between two-way asynchronous clock, and multipath clock needs To switch rear class coproduction life two-by-two, cannot generate phase when not only circuit resource being caused to waste, also underaction, and switched refers to Show signal and state, it is impossible to meet the needs of common SOC chip clock design.
Invention content
The defects of to solve conventional clock dynamic switching circuit, this application provides a kind of multi-clock dynamic switching circuits.
The technical solution adopted by the present invention is：A kind of multi-clock dynamic switching circuit, input end of clock include Slow Clock, Reference clock, middling speed clock, low-speed clock and high-frequency clock；Output terminal of clock includes the first output clock, the second output clock Clock is exported with third, is included between input end of clock and output terminal of clock：
Slow Clock synthesizes the Slow Clock after gate through Slow Clock switching sub-circuit；Reference clock through at a slow speed when Clock switching sub-circuit synthesizes the reference clock after gate；Low-speed clock is through Slow Clock switching sub-circuit synthesis by gate Low-speed clock afterwards；Middling speed clock synthesizes the middling speed clock after gate through Slow Clock switching sub-circuit；High-frequency clock passes through Slow Clock switching sub-circuit synthesizes the high-frequency clock after gate；
Slow Clock after gate, the reference clock after gate and the low-speed clock after gate, three It carries out or operation obtains the first output clock；
Slow Clock after gate, the reference clock after gate and the middling speed clock after gate, three It carries out or operation obtains the second output clock；
Slow Clock after gate, the reference clock after gate and the high-frequency clock after gate, three It carries out or operation obtains third output clock.
Slow Clock synthesizes the Slow Clock after gate through Slow Clock switching sub-circuit, specially：
First input control signal, the gate enable signal of reference clock, the gate enable signal of low-speed clock, three do Obtain the gate enable signal of Slow Clock after NAND operation, the non-and Slow Clock of the gate enable signal of Slow Clock do with Operation synthesizes the Slow Clock after gate.
Reference clock synthesizes the reference clock after gate through Slow Clock switching sub-circuit, specially：
Second input control signal, the gate enable signal of Slow Clock, the gate enable signal of low-speed clock, three do It is being obtained after NAND operation as a result, being synchronized using reference clock two-stage d type flip flop after obtain the gate of reference clock and enable letter Number；The non-and reference clock of the gate enable signal of reference clock, which is done, synthesizes the reference clock after gate with operation.
Low-speed clock synthesizes the low-speed clock after gate through Slow Clock switching sub-circuit, specially：
Third input control signal, the gate enable signal of reference clock, the gate enable signal of Slow Clock, three do It is being obtained after NAND operation as a result, being synchronized using low-speed clock two-stage d type flip flop after obtain first M signal, using one Grade d type flip flop obtains second M signal after synchronizing；Then by the synchronization of middling speed clock level-one d type flip flop, high-frequency clock level-one D Trigger obtains the gate enable signal of low-speed clock after synchronizing, second M signal, the gate enable signal of low-speed clock, Low-speed clock operation synthesizes the low-speed clock after gate.
Middling speed clock synthesizes the middling speed clock after gate through Slow Clock switching sub-circuit, specially：
First M signal obtains third M signal after middling speed clock level-one d type flip flop synchronizes, using middling speed Clock level-one d type flip flop obtains the gate enable signal of middling speed clock after synchronizing；When the gate enable signal of low-speed clock, middling speed The gate enable signal of clock and middling speed clock operation synthesize the middling speed clock after gate.
High-frequency clock synthesizes the high-frequency clock after gate through Slow Clock switching sub-circuit, specially：
Third M signal obtains the gate enable signal of high-frequency clock after high-frequency clock two-stage d type flip flop synchronizes； The gate enable signal of low-speed clock, the gate enable signal of high-frequency clock and high-frequency clock three's operation are synthesized by gate High-frequency clock afterwards.
First M signal is obtained after low-speed clock two-stage d type flip flop synchronizes, specially：
Two-stage d type flip flop includes the first synchronizer and the second synchronizer；
Third input control signal, the gate enable signal of Slow Clock, the gate enable signal of reference clock, San Zheyu Result after inverse connect the input terminal of the first synchronizer with low-speed clock, and output signal connects the input of the second synchronizer End exports first M signal.
When the process middling speed clock level-one d type flip flop is synchronous, high-frequency clock level-one d type flip flop obtains low speed after synchronizing The gate enable signal of clock, specially：
Second M signal connect the input terminal of the first d type flip flop with middling speed clock, and signal and the high-frequency clock of output connect The input terminal of the second d type flip flop is connect, exports the gate enable signal of low-speed clock.
The gate enable signal of reference clock obtains first state output signal, telltable clock switching electricity after negating operation The current state on road.
Second M signal obtains the second state output signal, the current state of telltable clock switching circuit after negating.
Second state output signal and the first output clock after NAND gate by the failing edge of the second output clock by being adopted Sample obtains the output signal of the clock phase relationship of the second output clock of instruction and the first output clock.
Second state output signal by the failing edge of third output clock after NAND gate by being sampled to obtain instruction third Export the output signal of the clock phase relationship of clock and two output clocks.
The advantageous effect that the present invention obtains is：Technical solution using the present invention being capable of impulse- free robustness switching at runtime SoC chip Required high-frequency clock, low-speed clock, reference clock and Slow Clock simultaneously generate synchronous clock domains clock phase indication signal And state, meet clock switching needs of the SoC chip between high-performance scene and multiple low-power consumption scenes.It is simple simultaneously skilful Wonderful circuit structure avoids the generation of burr, and saves circuit resource.
Description of the drawings
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or it will show below There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this Some embodiments described in application, for those of ordinary skill in the art, can also be obtained according to these attached drawings other Attached drawing.
Fig. 1 is a kind of hardware structure diagram of multi-clock dynamic switching circuit；
Fig. 2 is a kind of integrated circuit structure chart of multi-clock dynamic switching circuit；
Fig. 3 shows sel [2:0] the circuit sequence relation schematic diagram of 3 ' b100 is switched to by 3 ' b010；
Fig. 4 shows sel [2:0] the circuit sequence relation schematic diagram of 3 ' b001 is switched to by 3 ' b100.
Specific embodiment
With reference to the attached drawing in the embodiment of the present application, the technical solution in the embodiment of the present application is carried out clear, complete Ground describes, it is clear that described embodiment is some embodiments of the present application, instead of all the embodiments.Based on the application In embodiment, those skilled in the art's all other embodiments obtained without making creative work, all Belong to the range of the application protection.
A kind of multi-clock dynamic switching circuit proposed by the present invention, hardware circuit is as shown in Figure 1, input end of clock Including Slow Clock, reference clock, middling speed clock, low-speed clock and high-frequency clock；Output terminal of clock include first output clock, Second output clock and third output clock, include between input end of clock and output terminal of clock：
Slow Clock synthesizes the Slow Clock after gate through Slow Clock switching sub-circuit；Reference clock through at a slow speed when Clock switching sub-circuit synthesizes the reference clock after gate；Low-speed clock is through Slow Clock switching sub-circuit synthesis by gate Low-speed clock afterwards；Middling speed clock synthesizes the middling speed clock after gate through Slow Clock switching sub-circuit；High-frequency clock passes through Slow Clock switching sub-circuit synthesizes the high-frequency clock after gate；
Slow Clock after gate, the reference clock after gate and the low-speed clock after gate, three It carries out or operation obtains the first output clock；
Slow Clock after gate, the reference clock after gate and the middling speed clock after gate, three It carries out or operation obtains the second output clock；
Slow Clock after gate, the reference clock after gate and the high-frequency clock after gate, three It carries out or operation obtains third output clock.
Slow Clock switches sub-circuit, specially：The gate enable signal, low of first input control signal, reference clock The gate enable signal of fast clock, three obtain the gate enable signal of Slow Clock, the door of Slow Clock after doing NAND operation The non-and Slow Clock of control enable signal, which is done, synthesizes the Slow Clock after gate with operation.
Reference clock switches sub-circuit, specially：The gate enable signal, low of second input control signal, Slow Clock The gate enable signal of fast clock, three do obtaining after NAND operation as a result, being synchronized using reference clock two-stage d type flip flop The gate enable signal of reference clock is obtained afterwards；Non- done with reference clock of the gate enable signal of reference clock synthesizes with operation Reference clock after gate.
Low-speed clock switches sub-circuit, specially：The gate enable signal, slow of third input control signal, reference clock The gate enable signal of fast clock, three do obtaining after NAND operation as a result, being synchronized using low-speed clock two-stage d type flip flop After obtain first M signal, obtain second M signal after being synchronized using level-one d type flip flop；Then pass through middling speed clock one Grade d type flip flop is synchronous, high-frequency clock level-one d type flip flop obtains the gate enable signal of low-speed clock after synchronizing, among second Signal, the gate enable signal of low-speed clock, low-speed clock operation synthesize the low-speed clock after gate.
Middling speed clock switches sub-circuit, specially：First M signal obtains after middling speed clock level-one d type flip flop synchronizes To third M signal, the gate enable signal of middling speed clock is obtained after being synchronized using middling speed clock level-one d type flip flop；Low speed The gate enable signal of clock, the gate enable signal of middling speed clock and middling speed clock operation synthesize the middling speed after gate Clock.
High-frequency clock switches sub-circuit, specially：Third M signal obtains after high-frequency clock two-stage d type flip flop synchronizes To the gate enable signal of high-frequency clock；The gate enable signal of low-speed clock, the gate enable signal of high-frequency clock and high speed Clock three's operation synthesizes the high-frequency clock after gate.
In low-speed clock switching sub-circuit, low-speed clock obtains first M signal after two-stage d type flip flop synchronizes, specifically For：Two-stage d type flip flop includes the first synchronizer and the second synchronizer；Third input control signal, Slow Clock gate enable The gate enable signal of signal, reference clock, the result after three's NAND operation connect the defeated of the first synchronizer with low-speed clock Enter end, output signal connects the input terminal of the second synchronizer, exports first M signal.
Fig. 2 is integrated circuit structure chart, including：
The input of the circuit includes Slow Clock (clkslow_in), reference clock (clkref_in), input control signal (sel[2:0]), high-frequency clock (pll_x4), middling speed clock (pll_x2) and low-speed clock (pll_x1)；It is defeated that output includes first Go out clock clk_x1, the second output clock clk_x2 and third output clock clk_x4.
The circuit first branch：First input control signal (sel [0]) is synchronous with by reference clock (clkref_in) Reference clock gate enable signal (ref_ff2) and by middling speed clock (pll_x2), low-speed clock (pll_x1), it is high/ First gate enable signal x4_ff3 of low-speed clock, the gate enable signal after NAND operation as Slow Clock gatedEnable_slow；Then the non-and Slow Clock of the gate enable signal gatedEnable_slow of Slow Clock (clkslow_in) mutually with result be Slow Clock after gate.
Circuit the second branch：Gate enable signal gatedEnable_slow, the second input control signal of Slow Clock First gate enable signal x4_ff3 of (sel [1]) and high/low speed clock, the result after three's NAND operation is passed through Reference clock (clkref_in) two-stage d type flip flop is synchronized later as the gate enable signal ref_ff2 with reference to clock；It will ginseng The non-progress of the second gate enable signal ref_ff2 of clock (clkref_in) and reference clock is examined with the result after operation i.e. For the reference clock after gate；
Second gate enable signal ref_ff2 of reference clock obtains output signal clock_state [0] after negating, and refers to Show the current state of clock switch circuit.
Circuit third branch：
Input control signal (sel [2]), the second output signal ref_ff2, Slow Clock gate enable signal GatedEnable_slow synchronizes the result after three's NAND operation by low-speed clock (pll_x1) two-stage d type flip flop Signal x1_ff1 is obtained later；It samples to obtain signal x1_ff2 using low-speed clock level-one d type flip flop；Then by level-one After the sampling of fast clock (pll_x2) d type flip flop, the sampling of level-one high-frequency clock high-frequency clock (pll_x4) d type flip flop, as it is high/ First gate enable signal x4_ff3 of low-speed clock.Non-, x4_ff3 non-, low-speed clock (pll_x1) three's phase of x1_ff2 With result as the low-speed clock after gate；
X1_ff2 obtains output signal clock_state [1], the current state of telltable clock switching circuit after negating.
The 4th branch of circuit：
X1_ff1 obtains signal x2_ff1 after the sampling of level-one middling speed clock (pll_x2) d type flip flop, using level-one The second gate enable signal x2_ff2 of high/low speed clock is obtained after the sampling of middling speed clock (pll_x2) d type flip flop；High/low speed Non-, the second gate enable signal x2_ff2 non-sum middling speed clock (pll_x2) of first gate enable signal x1_ff4 of clock Three's phase and result as the middling speed clock after gate.
The 5th branch of circuit：
X2_ff1 obtains signal x4_ff1 after the sampling of level-one high-frequency clock (pll_x4) d type flip flop, using level-one The third gate enable signal x4_ff2 of high/low speed clock is obtained after the sampling of high-frequency clock (pll_x4) d type flip flop；High/low speed The non-sum of non-, high/low speed clock the first gate enable signal x1_ff4 of the third gate enable signal x4_ff2 of clock is high Fast clock (pll_x4) three phase and result as the high-frequency clock after gate.
Slow Clock after gate, the reference clock after gate and low-speed clock three's phase after gate Or output clock clk_x1 is generated later；
Slow Clock after gate, the reference clock after gate and middling speed clock three's phase by gate Or output clock clk_x2 is generated later；
Slow Clock after gate, the reference clock after gate and high-frequency clock three's phase by gate Or output clock clk_x4 is generated later.
Clock_state [1] and clk_x1 obtains instruction clk_ by being sampled after NAND gate by the failing edge of clk_x2 The output signal clkx2_phase of the clock phase relationship of x2 and clk_x1；
Clock_state [1] and clk_x2 obtains instruction clk_ by being sampled after NAND gate by the failing edge of clk_x4 The output signal clkx4_phase of the clock phase relationship of x4 and clk_x2.
Circuit sequence relationship when illustrating circuit switching, Fig. 3 show sel [2:0] 3 ' b100 are switched to by 3 ' b010 Circuit sequence relation schematic diagram；
In clock selecting control signal sel [2:0] after becoming 3 ' b100 from 3 ' b010, after reference clock synchronizes, Ref_ff2 from 0 saltus step be 1；The failing edge of next pll_x1 clocks, x1_ff0 become 0 from 1, next one pll_x1 clock Failing edge, x1_ff1 becomes 0 from 1, and the failing edge of next one pll_x1 clock, x1_ff2 becomes 0 from 1；Then next The failing edge of a pll_x2, x2_ff3 become 0 from 1；Then the failing edge of next pll_x4, x4_ff3 become 0 from 1；It arrives This, the gate enable signal of middling speed clock/2 and high-frequency clock is effective, and clk_x1/clk_x2/clk_x4 is switched to middling speed respectively Clock, low-speed clock, high-frequency clock clock rate, while clkx2_phase/clkx4_phase starts to indicate new clock Phase relation.
Fig. 4 shows sel [2:0] the circuit sequence relation schematic diagram of 3 ' b001 is switched to by 3 ' b100；
In clock selecting control signal sel [2:0] after becoming 3 ' b001 from 3 ' b100, the decline of next pll_x1 clocks Edge, x1_ff0 become 1 from 0, and the failing edge of next one pll_x1 clock, x1_ff1 becomes 1 from 0, during next one pll_x1 The failing edge of clock, x1_ff2 become 1 from 0；The failing edge that x2_ff1 becomes next pll_x2 after 1 in x1_ff1 becomes from 0 1, the x2_ff2 failing edge for becoming next pll_x2 after 1 in x2_ff1 becomes 1 from 0；X4_ff1 is after x2_ff1 becomes 1 The failing edge of next pll_x4 from 0 becomes 1, x4_ff2 and becomes the failing edge of next pll_x4 after 1 in x4_ff1 becoming from 0 It is 1；This is arrived, the gate enable signal of middling speed clock/2 and high-frequency clock becomes invalid, clk_x1/clk_x2/clk_x4 successively Failure of oscillation and it is switched to the clock rate of Slow Clock respectively.
Although the preferred embodiment of the application has been described, those skilled in the art once know basic creation Property concept, then additional changes and modifications may be made to these embodiments.So appended claims be intended to be construed to include it is excellent It selects embodiment and falls into all change and modification of the application range.Obviously, those skilled in the art can be to the application Various modification and variations are carried out without departing from spirit and scope.If in this way, these modifications and variations of the application Belong within the scope of the application claim and its equivalent technologies, then the application is also intended to exist comprising these modification and variations It is interior.

Claims (12)

1. a kind of multi-clock dynamic switching circuit, which is characterized in that input end of clock includes Slow Clock, reference clock, low speed Clock, middling speed clock and high-frequency clock；When output terminal of clock includes the first output clock, the second output clock and third output Clock includes between input end of clock and output terminal of clock：
Slow Clock synthesizes the Slow Clock after gate through Slow Clock switching sub-circuit；Reference clock is cut through reference clock It changes sub-circuit and synthesizes the reference clock after gate；Low-speed clock is through low-speed clock switching sub-circuit synthesis after gate Low-speed clock；Middling speed clock synthesizes the middling speed clock after gate through middling speed clock switching sub-circuit；High-frequency clock is through at a high speed Clock switching sub-circuit synthesizes the high-frequency clock after gate；
Slow Clock after gate, the reference clock after gate and the low-speed clock after gate, three's operation Synthesis the first output clock；
Slow Clock after gate, the reference clock after gate and the middling speed clock after gate, three's operation Synthesis the second output clock；
Slow Clock after gate, the reference clock after gate and the high-frequency clock after gate, three's operation Synthesize third output clock.
2. multi-clock dynamic switching circuit as described in claim 1, which is characterized in that the Slow Clock is cut through Slow Clock It changes sub-circuit and synthesizes the Slow Clock after gate, specially：
First input control signal, the gate enable signal of reference clock, the gate enable signal of low-speed clock, three do with it is non- The gate enable signal of Slow Clock is obtained after operation, the non-and Slow Clock of the gate enable signal of Slow Clock is done and operation Synthesize the Slow Clock after gate.
3. multi-clock dynamic switching circuit as claimed in claim 2, which is characterized in that the reference clock is cut through Slow Clock It changes sub-circuit and synthesizes the reference clock after gate, specially：
Second input control signal, the gate enable signal of Slow Clock, the gate enable signal of low-speed clock, three do with it is non- It is being obtained after operation as a result, being synchronized using reference clock two-stage d type flip flop after obtain the gate enable signal of reference clock；Ginseng The non-and reference clock for examining the gate enable signal of clock does the reference clock after gate is synthesized with operation.
4. multi-clock dynamic switching circuit as claimed in claim 3, which is characterized in that the low-speed clock is cut through Slow Clock It changes sub-circuit and synthesizes the low-speed clock after gate, specially：
Third input control signal, the gate enable signal of reference clock, the gate enable signal of Slow Clock, three do with it is non- It is being obtained after operation as a result, being synchronized using low-speed clock two-stage d type flip flop after obtain first M signal, using level-one D Trigger obtains second M signal after synchronizing；Then it is touched by the synchronization of middling speed clock level-one d type flip flop, high-frequency clock level-one D Hair device obtains the gate enable signal of low-speed clock after synchronizing, second M signal, the gate enable signal of low-speed clock, low Fast clock operation synthesizes the low-speed clock after gate.
5. multi-clock dynamic switching circuit as claimed in claim 4, which is characterized in that the middling speed clock is cut through Slow Clock It changes sub-circuit and synthesizes the middling speed clock after gate, specially：
First M signal obtains third M signal after middling speed clock level-one d type flip flop synchronizes, using middling speed clock Level-one d type flip flop obtains the gate enable signal of middling speed clock after synchronizing；The gate enable signal of low-speed clock, middling speed clock Gate enable signal and middling speed clock operation synthesize the middling speed clock after gate.
6. multi-clock dynamic switching circuit as claimed in claim 5, which is characterized in that the high-frequency clock is cut through Slow Clock It changes sub-circuit and synthesizes the high-frequency clock after gate, specially：
Third M signal obtains the gate enable signal of high-frequency clock after high-frequency clock two-stage d type flip flop synchronizes；Low speed The gate enable signal of clock, the gate enable signal of high-frequency clock and high-frequency clock three's operation are synthesized after gate High-frequency clock.
7. multi-clock dynamic switching circuit as claimed in claim 4, which is characterized in that described to be touched by low-speed clock two-stage D Hair device obtains first M signal after synchronizing, specially：
Two-stage d type flip flop includes the first synchronizer and the second synchronizer；
Third input control signal, the gate enable signal of Slow Clock, the gate enable signal of reference clock, three and non-fortune Result after calculation connect the input terminal of the first synchronizer with low-speed clock, and output signal connects the input terminal of the second synchronizer, defeated Go out first M signal.
8. multi-clock dynamic switching circuit as claimed in claim 4, which is characterized in that described to be touched by middling speed clock level-one D Hair device is synchronous, high-frequency clock level-one d type flip flop obtains the gate enable signal of low-speed clock after synchronizing, specially：
Second M signal connect the input terminal of the first d type flip flop with middling speed clock, and the signal of output connect with high-frequency clock The input terminal of 2-D trigger exports the gate enable signal of low-speed clock.
9. multi-clock dynamic switching circuit as claimed in claim 3, which is characterized in that the gate enable signal of reference clock is done First state output signal, the current state of telltable clock switching circuit are obtained after negating operation.
10. multi-clock dynamic switching circuit as claimed in claim 4, which is characterized in that second M signal obtains after negating Second state output signal, the current state of telltable clock switching circuit.
11. multi-clock dynamic switching circuit as claimed in claim 10, which is characterized in that the second state output signal and first Output clock by the failing edge of the second output clock by sampling to obtain the second output clock of instruction and first defeated after NAND gate Go out the output signal of the clock phase relationship of clock.
12. multi-clock dynamic switching circuit as claimed in claim 10, which is characterized in that the second state output signal pass through with It samples to obtain by the failing edge of third output clock after NOT gate and indicates that third output clock and two exports the clock phase of clocks The output signal of relationship.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109753481A (en) * 2019-01-15 2019-05-14 上海安路信息科技有限公司 Dynamic phasing switching system and dynamic phasing switching method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101150316A (en) * 2007-09-14 2008-03-26 电子科技大学 A multi-channel clock synchronization method and system
CN101498952A (en) * 2009-03-02 2009-08-05 北京红旗胜利科技发展有限责任公司 CPU, SoC chip and method for synchronizing clock
CN103546125A (en) * 2013-09-24 2014-01-29 北京时代民芯科技有限公司 Multi-choice and burr-free clock switching circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101150316A (en) * 2007-09-14 2008-03-26 电子科技大学 A multi-channel clock synchronization method and system
CN101498952A (en) * 2009-03-02 2009-08-05 北京红旗胜利科技发展有限责任公司 CPU, SoC chip and method for synchronizing clock
CN103546125A (en) * 2013-09-24 2014-01-29 北京时代民芯科技有限公司 Multi-choice and burr-free clock switching circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109753481A (en) * 2019-01-15 2019-05-14 上海安路信息科技有限公司 Dynamic phasing switching system and dynamic phasing switching method

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