CN108231872A - A kind of semiconductor devices and its manufacturing method - Google Patents
A kind of semiconductor devices and its manufacturing method Download PDFInfo
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- CN108231872A CN108231872A CN201611146086.4A CN201611146086A CN108231872A CN 108231872 A CN108231872 A CN 108231872A CN 201611146086 A CN201611146086 A CN 201611146086A CN 108231872 A CN108231872 A CN 108231872A
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- diffusion impervious
- impervious layer
- semiconductor devices
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000009792 diffusion process Methods 0.000 claims abstract description 138
- 239000002184 metal Substances 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000011248 coating agent Substances 0.000 claims abstract description 36
- 238000000576 coating method Methods 0.000 claims abstract description 36
- 230000004888 barrier function Effects 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 150000002500 ions Chemical class 0.000 claims abstract description 16
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 32
- 239000007789 gas Substances 0.000 claims description 20
- 230000035484 reaction time Effects 0.000 claims description 7
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 239000000376 reactant Substances 0.000 claims description 4
- 238000004062 sedimentation Methods 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000000463 material Substances 0.000 description 15
- 229910008482 TiSiN Inorganic materials 0.000 description 12
- 238000000231 atomic layer deposition Methods 0.000 description 12
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 12
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 8
- 229910010038 TiAl Inorganic materials 0.000 description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 229910052593 corundum Inorganic materials 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 229910052986 germanium hydride Inorganic materials 0.000 description 4
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 229910052741 iridium Inorganic materials 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 229910001845 yogo sapphire Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910004200 TaSiN Inorganic materials 0.000 description 2
- 229910010037 TiAlN Inorganic materials 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910003074 TiCl4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000012010 growth Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
Abstract
The present invention provides a kind of semiconductor devices and its manufacturing method, the semiconductor devices include：Semiconductor substrate；Metal gates in the Semiconductor substrate；And the coating between the metal gates and the Semiconductor substrate, the coating include Ge Doped ions.Compared with the prior art, semiconductor devices proposed by the present invention, coating therein have higher diffusion barrier capability and relatively low resistance；In addition, compared with Si elements, Ge elements are not susceptible to spread, and the influence to device performance is smaller.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of semiconductor devices and its manufacturing method.
Background technology
In CMOS integrated circuit technologies, with the continuous diminution of device size, it is desirable that grid medium thickness is constantly thinned, and
Grid leakage current then exponentially increases with the thinned of grid medium thickness, this use for allowing for high K dielectric material becomes inevitable.
And traditional polygate electrodes are due to poly-Si depletion effect, boron penetration, there are incompatibility (such as Fermi's energy with high K dielectric
Grade pinning) the problems such as and can be substituted by metallic gate electrode material.
In high K dielectric/metal-gate structures, the diffusion of element can occur under the action of electric field, for example, in metal gates
Metal and gate dielectric layer in oxygen etc. can be diffused into work-function layer, cause the drift of work function, device performance made to reduce very
To failure.Therefore it needs to add between high-K dielectric layer and work-function layer and between metallized metal grid and work-function layer to expand
Dissipate barrier layer.Currently used diffusion impervious layer is TiN layer.However, TiN layer is polycrystalline and column crystal micro-structure, have more
Crystal boundary, under the action of electric field, oxygen in metal and gate dielectric layer in gate electrode etc. be easy to via its grain boundary decision into
Work-function layer.The study found that TiN column crystals growths can be prevented by adding in Si elements, impalpable structure, thus Si doping TiN are formed
Layer (TiSiN) can improve the diffusion barrier capability of TiN layer.However, the resistance of TiSiN is higher, it will using TiSiN diffusion impervious layers
Resistance is improved, so as to reduce device performance.In addition, Si elements are prone to spread, so as to influence metal gate structure
Performance.
Therefore, to solve above-mentioned technical problem of the prior art, it is necessary to propose a kind of system of new semiconductor devices
Make method
Invention content
In view of the deficiencies of the prior art, the present invention provides a kind of novel semiconductor devices, including：
Semiconductor substrate；Metal gates in the Semiconductor substrate；And positioned at the metal gates with it is described
Coating between Semiconductor substrate, the coating include Ge Doped ions.
Illustratively, the coating includes the first diffusion impervious layer between gate dielectric layer and work-function layer, institute
It states the first diffusion impervious layer and includes Ge Doped ions.
Illustratively, the second diffusion barrier between first diffusion impervious layer and the work-function layer is further included
Layer.
Illustratively, the coating includes the third diffusion impervious layer between work-function layer and metal gates, institute
It states third diffusion impervious layer and includes Ge Doped ions.
Illustratively, the 4th diffusion barrier between the third diffusion impervious layer and the work-function layer is further included
Layer.
Illustratively, first diffusion impervious layer includes TiGeN layers.
Illustratively, the third diffusion impervious layer includes TiGeN layers.
Illustratively, second diffusion impervious layer includes TiN layer.
Illustratively, the 4th diffusion impervious layer includes TiN layer.
Illustratively, the thickness ratio of first diffusion impervious layer and second diffusion impervious layer is 2-3.
Illustratively, the thickness ratio of the third diffusion impervious layer and the 4th diffusion impervious layer is 2-3.
The present invention also provides a kind of manufacturing method of semiconductor devices, including：Semiconductor substrate is provided；In the semiconductor
Coating is formed on substrate, the coating includes Ge Doped ions；Metal gates are formed on the coating.
Illustratively, the coating includes the first diffusion impervious layer between gate dielectric layer and work-function layer, institute
It states the first diffusion impervious layer and includes Ge Doped ions.
Illustratively, the second diffusion barrier between first diffusion impervious layer and the work-function layer is further included
Layer.
Illustratively, the coating includes the third diffusion impervious layer between work-function layer and metal gates, institute
It states third diffusion impervious layer and includes Ge Doped ions.
Illustratively, the 4th diffusion barrier between the third diffusion impervious layer and the work-function layer is further included
Layer.
Illustratively, first diffusion impervious layer includes TiGeN layers.
Illustratively, the third diffusion impervious layer includes TiGeN layers.
Illustratively, second diffusion impervious layer includes TiN layer.
Illustratively, the 4th diffusion impervious layer includes TiN layer.
Illustratively, the thickness ratio of first diffusion impervious layer and second diffusion impervious layer is 2-3.
Illustratively, the thickness ratio of the third diffusion impervious layer and the 4th diffusion impervious layer is 2-3.
Illustratively, the step of forming the coating on the semiconductor substrate includes：By controlling each reaction
In periodic reaction object in the product of the dosage of Ge bases gas or sedimentation time to control each reaction time Ge doping concentration.
Illustratively, each the reaction time is：Ti base gases, Ge base gases, N base gases, with generation are imported successively
One TiGeN layers.
Compared with the prior art, semiconductor devices proposed by the present invention, coating therein have higher diffusion barrier
Ability and relatively low resistance；In addition, compared with Si elements, Ge elements are not susceptible to spread, and the influence to device performance is smaller.
Description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 is the schematic cross sectional view of a kind of semiconductor devices that the embodiment of the present invention one provides.
Fig. 2 is the schematic cross sectional view of a kind of semiconductor devices that the embodiment of the present invention two provides.
Fig. 3 is the schematic cross sectional view of a kind of semiconductor devices that the embodiment of the present invention three provides.
Fig. 4 is the flow chart of the manufacturing method of semiconductor devices provided by the invention.
Specific embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.Disclosure will be made thoroughly and complete, and will fully convey the scope of the invention on the contrary, providing these embodiments
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or during layer, then there is no elements or layer between two parties.It should be understood that although it can make
Various elements, component, area, floor and/or part described with term first, third, second etc., these elements, component, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, component, area, floor or part with it is another
One element, component, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by third element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and be used so as to describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention, which further includes, to be made
With the different orientation with the device in operation.For example, if the device overturning in attached drawing, then, is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented to other elements or features " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
In order to stop in high K dielectric/metal-gate structures, oxygen in metal and gate dielectric layer in metal electrode layer etc. can expand
It dissipates into work-function layer, between needing between high-K dielectric layer and work-function layer and between metal gate layers and work-function layer
Add in diffusion impervious layer.Currently used diffusion impervious layer is TiN layer.However, element is easily expanded via the crystal boundary in TiN
It dissipates.The diffusion barrier capability of TiN layer can be improved by adding in Si elements.However, TiSiN layers of resistance is higher.In addition, Si elements are easy to
It spreads, so as to influence the performance of metal gate structure.
In view of the deficiencies of the prior art, the present invention provides a kind of novel semiconductor devices, including：
Semiconductor substrate；Metal gates in the Semiconductor substrate；And positioned at the metal gates with it is described
Coating between Semiconductor substrate, the coating include Ge Doped ions.
The coating includes the first diffusion impervious layer between gate dielectric layer and work-function layer, first diffusion
Barrier layer includes Ge Doped ions.Further include the second diffusion between first diffusion impervious layer and the work-function layer
Barrier layer.
The coating includes the third diffusion impervious layer between work-function layer and metal gates, the third diffusion
Barrier layer includes Ge Doped ions.Further include the 4th diffusion between the third diffusion impervious layer and the work-function layer
Barrier layer.
First diffusion impervious layer includes TiGeN layers.The third diffusion impervious layer includes TiGeN layers.Described second
Diffusion impervious layer includes TiN layer.4th diffusion impervious layer includes TiN layer.
The thickness ratio of first diffusion impervious layer and second diffusion impervious layer is 2-3.The third diffusion barrier
The thickness ratio of layer and the 4th diffusion impervious layer is 2-3.
Compared with the prior art, semiconductor devices proposed by the present invention, coating therein have higher diffusion barrier
Ability and relatively low resistance.In addition, compared with Si elements, Ge elements are not susceptible to spread, and the influence to device performance is smaller.
In order to thoroughly understand the present invention, detailed structure and/or step will be proposed in following description, to illustrate this
Invent the technical solution proposed.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this hair
It is bright to have other embodiment.[exemplary embodiment one]
With reference to Fig. 1, the schematic cross sectional view of the semiconductor devices of proposition of the embodiment of the present invention is shown.It is described partly to lead
Body device includes：Gate dielectric layer 101, the first diffusion impervious layer 102, the second diffusion impervious layer 103, work-function layer 104, third expand
Dissipate barrier layer 105, the 4th diffusion impervious layer 106, metal gates 107.
The gate dielectric layer 101 is high-K gate medium layer, and material can select such as TiO2、Al2O3、ZrO2、HfO2、
Ta2O5、La2O3Deng.Illustratively, HfO is selected in the present embodiment2As the high-K dielectric layer.The high-K gate is formed to be situated between
The method of matter layer can be physical gas-phase deposition or atom layer deposition process, and thickness can be 15-60 angstroms.
First diffusion impervious layer, 102 and second diffusion impervious layer 103 is respectively to be sequentially formed in the gate dielectric layer
TiGeN layers on 101 and the TiN layer being formed on the TiGeN layers.Illustratively, described TiGeN layers with the TiN layer
Thickness ratio is 2-3, its thickness ratio is 2 in the present embodiment, and the overall thickness of the two can be 10-100 angstroms.First diffusion barrier
102 and second diffusion impervious layer 103 of layer can effectively stop that the oxygen in gate dielectric layer 101 etc. diffuses into work-function layer 104, expand
It dissipates blocking capability and is higher than TiN layer, it is approximate with TiSiN layers, and its resistance is then less than TiSiN layers.In addition, compared with Si elements, Ge
Element is not susceptible to spread, and the influence to device performance is smaller.
The work-function layer 104 is one layer in the lamination of gate structure.Illustratively, the work-function layer 104 includes
TiAl layers and TiN layer, preparation can be formed by the methods of atomic layer deposition (ALD) method, and thickness is also not limited to a certain
Numberical range.
4th diffusion impervious layer 106 and the third diffusion impervious layer 105 are respectively to be sequentially formed in the work content
TiN layer on several layers 104 and the TiGeN layers being formed in the TiN layer.Illustratively, described TiGeN layers and the TiN layer
Thickness ratio for 2-3, its thickness ratio is 2 in the present embodiment, and the overall thickness of the two can be 10-100 angstroms.The third diffusion resistance
105 and the 4th diffusion impervious layer 106 of barrier can be effectively in barrier metal grid 107 metal ion diffuse into work-function layer
104, diffusion barrier capability is higher than TiN layer, approximate with TiSiN layers, and its resistance is then less than TiSiN layers.In addition, with Si elements
It compares, Ge elements are not susceptible to spread, and the influence to device performance is smaller.
The metal gates 107 are located on the third diffusion impervious layer 105.The metal gates 107 are metallicity electricity
Pole, material may include one or more in Al, Ta, Ti, W, Cu, Pt, Ru, Mo or Ir, but be not limited only to above-mentioned material.
It should be noted that in the embodiment of the present invention, unshowned other layers can also be included in the gate structure,
Such as soakage layer etc..
Compared with the prior art, semiconductor devices proposed by the present invention, coating therein have higher diffusion barrier
Ability and relatively low resistance.In addition, compared with Si elements, Ge elements are not susceptible to spread, and the influence to device performance is smaller.
[exemplary embodiment two]
With reference to Fig. 2, the schematic cross sectional view of the semiconductor devices of proposition of the embodiment of the present invention is shown.It is described partly to lead
Body device includes：Gate dielectric layer 201, the first diffusion impervious layer 202, the second diffusion impervious layer 203, work-function layer 204, metal gate
Pole 205.
The gate dielectric layer 201 is high-K gate medium layer, and material can select such as TiO2、Al2O3、ZrO2、HfO2、
Ta2O5、La2O3Deng.Illustratively, HfO is selected in the present embodiment2As the high-K dielectric layer.The high-K gate is formed to be situated between
The method of matter layer 201 can be physical gas-phase deposition or atom layer deposition process, and thickness can be 15-60 angstroms.
First diffusion impervious layer, 202 and second diffusion impervious layer 203 is respectively to be sequentially formed in the gate dielectric layer
TiGeN layers on 201 and the TiN layer being formed on the TiGeN layers.Illustratively, described TiGeN layers with the TiN layer
Thickness ratio is 2-3, its thickness ratio is 2 in the present embodiment, and the overall thickness of the two can be 10-100 angstroms.First diffusion barrier
202 and second diffusion impervious layer 203 of layer can effectively stop that the oxygen in gate dielectric layer 201 etc. diffuses into work-function layer, spread
Blocking capability is higher than TiN layer, approximate with TiSiN layers, and its resistance is then less than TiSiN layers.In addition, compared with Si elements, Ge members
Element is not susceptible to spread, and the influence to device performance is smaller.
The work-function layer 204 is one layer in the lamination of gate structure.Illustratively, the work-function layer 204 includes
TiAl layers and TiN layer, preparation can be formed by the methods of atomic layer deposition (ALD) method, and thickness is also not limited to a certain
Numberical range.
The metal gates 205 are located in the work-function layer.The metal gates 205 be metallic electrode, material
It may include one or more in Al, Ta, Ti, W, Cu, Pt, Ru, Mo or Ir, but be not limited only to above-mentioned material.The metal gate
Can also there are diffusion impervious layer, such as TiN, TaN, TaC, TiGeN, TaSiN, WN, TiAl, TiAlN between pole and work-function layer
In it is one or more, but be not limited to above-mentioned material.
It should be noted that in the embodiment of the present invention, unshowned other layers can also be included in the gate structure,
Such as soakage layer etc..
Compared with the prior art, semiconductor devices proposed by the present invention, coating therein have higher diffusion barrier
Ability and relatively low resistance.In addition, compared with Si elements, Ge elements are not susceptible to spread, and the influence to device performance is smaller.
[exemplary embodiment three]
With reference to Fig. 3, the schematic cross sectional view of the semiconductor devices of proposition of the embodiment of the present invention is shown.It is described partly to lead
Body device includes：Gate dielectric layer 301, work-function layer 302, third diffusion impervious layer 303, the 4th diffusion impervious layer 304, metal gate
Pole 305.
The gate dielectric layer 301 is high-K gate medium layer, and material can select such as TiO2、Al2O3、ZrO2、HfO2、
Ta2O5、La2O3Deng.Illustratively, HfO is selected in the present embodiment2As the high-K dielectric layer.The high-K gate is formed to be situated between
The method of matter layer 301 can be physical gas-phase deposition or atom layer deposition process, and thickness can be 15-60 angstroms.
The work-function layer 302 is one layer in the lamination of gate structure.Illustratively, the work-function layer 302 includes
TiAl layers and TiN layer, preparation can be formed by the methods of atomic layer deposition (ALD) method, and thickness is also not limited to a certain
Numberical range.Can also have diffusion impervious layer between the work-function layer and gate dielectric layer, for example, TiN, TaN, TaC, TiGeN,
It is one or more in TaSiN, WN, TiAl, TiAlN, but it is not limited to above-mentioned material.
4th diffusion impervious layer 304 and the third diffusion impervious layer 303 are respectively to be sequentially formed in the work content
TiN layer on several layers 302 and the TiGeN layers being formed in the TiN layer.Illustratively, described TiGeN layers and the TiN layer
Thickness ratio for 2-3, its thickness ratio is 2 in the present embodiment, and the overall thickness of the two can be 10-100 angstroms.The third diffusion resistance
304 and the 4th diffusion impervious layer 303 of barrier can be effectively in barrier metal grid 305 metal ion diffuse into work-function layer
302, diffusion barrier capability is higher than TiN layer, approximate with TiSiN layers, and its resistance is then less than TiSiN layers.In addition, with Si elements
It compares, Ge elements are not susceptible to spread, and the influence to device performance is smaller.
The metal gates 305 are located on the third diffusion impervious layer 303.The metal gates 305 are metallicity electricity
Pole, material may include one or more in Al, Ta, Ti, W, Cu, Pt, Ru, Mo or Ir, but be not limited only to above-mentioned material.
It should be noted that in the embodiment of the present invention, the gate structure can also include unshowned other layers, example
Such as soakage layer.
Compared with the prior art, semiconductor devices proposed by the present invention, coating therein have higher diffusion barrier
Ability and relatively low resistance.In addition, compared with Si elements, Ge elements are not susceptible to spread, and the influence to device performance is smaller.
[exemplary embodiment four]
In the following, a kind of manufacturer of semiconductor devices of one embodiment of the present of invention proposition is described with reference to Fig. 1 and Fig. 4
Method.Wherein, Fig. 1 is a kind of structure of the correlation step formation of the manufacturing method of semiconductor devices of one embodiment of the present of invention
Sectional view；Fig. 4 is a kind of schematic flow chart of the manufacturing method of semiconductor devices of one embodiment of the present of invention.
Illustratively, the manufacturing method of the semiconductor devices of one embodiment of the present of invention, includes the following steps：
First, step 401 is performed, Semiconductor substrate (not shown) is provided.Specifically, heretofore described Semiconductor substrate
It can be at least one of following material being previously mentioned：Silicon (SSOI), absolutely is laminated on insulator for silicon, silicon-on-insulator (SOI)
SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. are laminated on edge body.
Optionally, doped region and/or isolation structure, the isolation structure be could be formed in the semiconductor substrate
For shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) isolation structure and other active devices.
Then, gate dielectric layer 101 is formed in substrate surface.The gate dielectric layer 101 be high-K gate medium layer, material
Such as TiO can be selected2、Al2O3、ZrO2、HfO2、Ta2O5、La2O3Deng.Illustratively, HfO is selected in the present embodiment2As
High-K dielectric layer.The method for forming the high-K gate medium layer 101 can be physical gas-phase deposition or atomic layer deposition work
Skill, thickness can be 15-60 angstroms.
Then, perform step 402, form coating on the semiconductor substrate, the coating including Ge adulterate from
Son.First, the first diffusion impervious layer 102 is formed on the gate dielectric layer 101 successively, and in first diffusion impervious layer
The second diffusion impervious layer 103 is formed on 102.First diffusion impervious layer, 102 and second diffusion impervious layer 103 is respectively successively
The TiGeN layers being formed on the gate dielectric layer 101 and the TiN layer being formed on the TiGeN layers.Illustratively, it is described
The thickness ratio of TiGeN layers and the TiN layer is 2-3, its thickness ratio is 2 in the present embodiment, and the overall thickness of the two can be 10-
100 angstroms.The forming method of the diffusion impervious layer can be physical vaporous deposition (PVD), chemical vapour deposition technique (CVD),
Atomic layer deposition method (ALD) etc..ALD method is selected to form first diffusion impervious layer 102 in the present embodiment.Specifically, it deposits
Temperature is 350 DEG C, and cavity indoor pressure 3Torr, the flow control of reactant gas is in 100~500sccm.First, it is passed through
TiCl4Gas 0.5-2s.Then, Ar gas 6s are imported, rinse reaction chamber and take away extra reaction gas, reaction is isolated
Object.Then it is passed through GeH4Gas 15s.Then, Ar gases 6s is imported with reactant separation.Then, NH is imported3Gas 10s.Then,
Ar gases 6s is imported with reactant separation.So far a reaction time is completed.It can be by controlling each GeH reaction time4Gas
Flow or sputtering time control the doping concentration of Ge in generated TiGeN layers.Illustratively, when being passed through GeH4During gas
Between when being 15s, the TiGeN layer thickness that obtains this reaction time is 0.73 angstrom, and wherein Ge doping concentrations are 8.5atom%.Generation
After the TiGeN layers of target thickness, it can make to be passed through GeH4Gas time continues to react for 0s, to generate TiN layer.It is exemplary
Ground, the TiN layer thickness obtained in a reaction time are 0.46 angstrom.This period certain number is repeated, to obtain target thickness
TiN layer.
Then, work-function layer 104 is formed on second diffusion impervious layer 103.The work-function layer 104 includes TiAl
Layer and TiN layer, preparation can be formed by the methods of atomic layer deposition (ALD) method, and thickness is also not limited to a certain numerical value
Range.
Then, the 4th diffusion impervious layer 106 and third diffusion impervious layer 105 are formed in work-function layer 104.Described 4th
Diffusion impervious layer 106 is the TiN layer being formed in the work-function layer 104, and the third diffusion impervious layer 105 is is formed in
State the TiGeN layers in TiN layer.Illustratively, the thickness ratio of described TiGeN layers and the TiN layer is 2-3, its in the present embodiment
Thickness ratio is 2, and the overall thickness of the two can be 10-100 angstroms.Preparation method remaining with the first diffusion impervious layer and the second diffusion hinders
Barrier is identical, the difference lies in：GeH is kept first4The sputtering time of gas is 0s, generates the TiN layer of target thickness, then
Increase GeH4The sputtering time of gas, to form the TiGeN layers of predetermined thickness in the TiN layer.
Then, step 403 is performed, metal gates are formed on the coating.Specifically, in the third diffusion barrier
Metal gates 107 are formed on layer 105.The metal gates 107 be metallic electrode, material may include Al, Ta, Ti, W, Cu,
It is one or more in Pt, Ru, Mo or Ir, but it is not limited only to above-mentioned material.
So far, the introduction of the correlation step of the manufacturing method of the semiconductor devices of the embodiment of the present invention is completed.It can manage
Solution, the present embodiment method, semi-conductor device manufacturing method not only include above-mentioned steps, before above-mentioned steps, among or later also
It may include other desired step, be included in the range of this implementation manufacturing method.
Compared with the prior art, semiconductor devices proposed by the present invention, coating therein have higher diffusion barrier
Ability and relatively low resistance.In addition, compared with Si elements, Ge elements are not susceptible to spread, and the influence to device performance is smaller.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (24)
1. a kind of semiconductor devices, which is characterized in that including：Semiconductor substrate；Metal gate in the Semiconductor substrate
Pole；And the coating between the metal gates and the Semiconductor substrate, the coating include Ge Doped ions.
2. semiconductor devices according to claim 1, which is characterized in that the coating includes being located at gate dielectric layer and work(
The first diffusion impervious layer between function layer, first diffusion impervious layer include Ge Doped ions.
3. semiconductor devices according to claim 2, which is characterized in that further include positioned at first diffusion impervious layer with
The second diffusion impervious layer between the work-function layer.
4. semiconductor devices according to claim 1, which is characterized in that the coating includes being located at work-function layer and gold
Belong to the third diffusion impervious layer between grid, the third diffusion impervious layer includes Ge Doped ions.
5. semiconductor devices according to claim 4, which is characterized in that further include positioned at the third diffusion impervious layer with
The 4th diffusion impervious layer between the work-function layer.
6. semiconductor devices according to claim 2, which is characterized in that first diffusion impervious layer includes TiGeN layers.
7. semiconductor devices according to claim 4, which is characterized in that the third diffusion impervious layer includes TiGeN layers.
8. semiconductor devices according to claim 3, which is characterized in that second diffusion impervious layer includes TiN layer.
9. semiconductor devices according to claim 5, which is characterized in that the 4th diffusion impervious layer includes TiN layer.
10. semiconductor devices according to claim 3, which is characterized in that first diffusion impervious layer and described second
The thickness ratio of diffusion impervious layer is 2-3.
11. semiconductor devices according to claim 5, which is characterized in that the third diffusion impervious layer and the described 4th
The thickness ratio of diffusion impervious layer is 2-3.
12. a kind of manufacturing method of semiconductor devices, which is characterized in that including：Semiconductor substrate is provided；It is served as a contrast in the semiconductor
Coating is formed on bottom, the coating includes Ge Doped ions；Metal gates are formed on the coating.
13. according to the method for claim 12, which is characterized in that the coating includes being located at gate dielectric layer and work function
The first diffusion impervious layer between layer, first diffusion impervious layer include Ge Doped ions.
14. according to the method for claim 13, which is characterized in that further include positioned at first diffusion impervious layer with it is described
The second diffusion impervious layer between work-function layer.
15. according to the method for claim 12, which is characterized in that the coating includes being located at work-function layer and metal gate
Third diffusion impervious layer between pole, the third diffusion impervious layer include Ge Doped ions.
16. according to the method for claim 15, which is characterized in that further include positioned at the third diffusion impervious layer with it is described
The 4th diffusion impervious layer between work-function layer.
17. according to the method for claim 13, which is characterized in that first diffusion impervious layer includes TiGeN layers.
18. according to the method for claim 15, which is characterized in that the third diffusion impervious layer includes TiGeN layers.
19. according to the method for claim 14, which is characterized in that second diffusion impervious layer includes TiN layer.
20. according to the method for claim 16, which is characterized in that the 4th diffusion impervious layer includes TiN layer.
21. according to the method for claim 14, which is characterized in that first diffusion impervious layer is hindered with the described second diffusion
The thickness ratio of barrier is 2-3.
22. according to the method for claim 16, which is characterized in that the third diffusion impervious layer is hindered with the described 4th diffusion
The thickness ratio of barrier is 2-3.
23. according to the method for claim 12, which is characterized in that form the coating on the semiconductor substrate
Step includes：By controlling in each reactant reaction time the dosage of Ge base gases or sedimentation time to control each reaction week
The doping concentration of Ge in the product of phase.
24. according to the method for claim 23, which is characterized in that each reaction time is：Ti base gas is imported successively
Body, Ge base gases, N base gases, with one TiGeN layers of generation.
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Citations (3)
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| CN104051252A (en) * | 2013-03-11 | 2014-09-17 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of high-K metal gate structure |
| CN104081531A (en) * | 2012-02-27 | 2014-10-01 | 应用材料公司 | Atomic layer deposition method for metal gate electrode |
| CN104752179A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104081531A (en) * | 2012-02-27 | 2014-10-01 | 应用材料公司 | Atomic layer deposition method for metal gate electrode |
| CN104051252A (en) * | 2013-03-11 | 2014-09-17 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of high-K metal gate structure |
| CN104752179A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and forming method thereof |
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