CN108231860A - A kind of display screen production method and AMOLED display screens - Google Patents
A kind of display screen production method and AMOLED display screens Download PDFInfo
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- CN108231860A CN108231860A CN201810083885.4A CN201810083885A CN108231860A CN 108231860 A CN108231860 A CN 108231860A CN 201810083885 A CN201810083885 A CN 201810083885A CN 108231860 A CN108231860 A CN 108231860A
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- H—ELECTRICITY
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
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Abstract
The present invention discloses a kind of display screen production method and AMOLED display screens.The display screen production method, including：Buffer layer and polysilicon layer are formed on substrate；It is respectively formed gate metal layer, storage capacitance metal layer, the first source drain metal layer, the second source drain metal layer, planarization layer, anode layer and multiple interlayer insulating films；Respectively between the polysilicon layer, gate metal layer, storage capacitance metal layer, the first source drain metal layer, the second source drain metal layer and each layer of planarization layer, the anode layer is located on the planarization layer wherein the multiple interlayer insulating film；Wherein described second source drain metal layer is the metal layer of whole face covering, is connect by through-hole with the first source drain metal layer, polysilicon layer and storage capacitance metal layer.Scheme provided by the invention can improve the light emission luminance uniformity of display screen, improve the display effect of AMOLED display screens.
Description
Technical field
The present invention relates to technical field of flat panel display, and in particular to a kind of display screen production method and AMOLED display screens.
Background technology
With the development of display technology, OLED (Organic Light Emitting Diode, Organic Light Emitting Diode)
Display screen gradually appears in each display field.AMOLED(Active Matrix Organic Light Emitting
Diode, active matrix organic light-emitting diode) it is display panel of new generation, belong to spontaneous light type, compared to general liquid crystal
Panel, have fast response time, without backlight, contrast higher, overall structure is frivolous, visual angle is wide, small power consumption and soft
Property the advantages that, have more wide application prospect.
In AMOLED, generally gone using the constant current of TFT (Thin Film Transistor, thin film transistor (TFT))
Driving OLED shines.But due to generally all having line impedence in circuit, influenced by line impedence is walked, it will there are IR_
Drop (pressure drop) problem.So-called impedance be usually resistance with reactance on vector and, when alternating current passes through impedance, impedance
The voltage at both ends, which is known as the pressure drop of the impedance namely impedance, can divide a part of voltage.Therefore, because IR_Drop (pressure drop)
Problem can lead to the input proximal end of the display area of AMOLED display screens and the V of the pixel of input distal endDD(power supply high voltage)
Voltage value differs greatly, and due to VDDThe difference of voltage will can generate different electric current in each pixel circuit, cause to produce
The non-uniform problem of raw OLED light emission luminance, so as to influence the display effect of AMOLED display screens.
Invention content
In view of this, it is an object of the invention to propose a kind of display screen production method and AMOLED display screens, can improve
The light emission luminance uniformity of display screen improves the display effect of AMOLED display screens.
According to an aspect of the present invention, a kind of display screen production method is provided, including：
Buffer layer and polysilicon layer are formed on substrate；
It is respectively formed gate metal layer, storage capacitance metal layer, the first source drain metal layer, the second source drain metal
Layer, planarization layer, anode layer and multiple interlayer insulating films；
Wherein the multiple interlayer insulating film respectively be located at the polysilicon layer, gate metal layer, storage capacitance metal layer,
Between first source drain metal layer, the second source drain metal layer and each layer of planarization layer, the anode layer is located at described flat
On smoothization layer；
Wherein described second source drain metal layer is the metal layer of whole face covering, is leaked by through-hole and first source electrode
Pole metal layer, polysilicon layer are connected with storage capacitance metal layer.
Optionally, the second source drain metal layer for do not include pattern metal layer and/or,
The second source drain metal layer is made of titanium-aluminium-titanium-composite construction.
Optionally, the second source drain metal layer is on the insulating layer on the first source drain metal layer upper strata
It is formed；
The second source drain metal layer upper strata re-forms insulating layer.
Optionally, the method further includes：
On the insulating layer on the first source drain metal layer upper strata etching formed at least two through-holes, by it is described extremely
Few two through-holes cause the second source drain metal layer and the first source drain metal layer, polysilicon layer and storage electricity
Hold metal layer connection.
Optionally, it is described to be respectively formed gate metal layer, storage capacitance metal layer, the first source drain metal layer, second
Source drain metal layer, planarization layer, anode layer and multiple interlayer insulating films, including：
The first insulating layer is formed on the polysilicon layer；
Gate metal layer is formed on first insulating layer；
Second insulating layer is formed in the gate metal layer；
Storage capacitance metal layer is formed in the second insulating layer；
Third insulating layer is formed on the storage capacitance metal layer；
The first source drain metal layer is formed on the third insulating layer；
The 4th insulating layer is formed on the first source drain metal layer；
The second source drain metal layer is formed on the 4th insulating layer；
The 5th insulating layer is formed on the second source drain metal layer；
Planarization layer is formed on the 5th insulating layer；
Anode layer is formed on the planarization layer.
Optionally, the method further includes：
It etches to form first through hole, the second through-hole and third through-hole in the third insulating layer, wherein the first through hole
It is connected with the polysilicon layer, second through-hole is connected with the gate metal layer, the third through-hole and the storage electricity
Hold metal layer to be connected；
It etches to form fourth hole and fifth hole in the 4th insulating layer, wherein the fourth hole and described first
The corresponding first source drain metal layer position of through-hole is connected, the fifth hole the first source electrode corresponding with the third through-hole
Drain metal layer position is connected；
It etches to form the 6th through-hole and the 7th through-hole in the planarization layer, wherein the 6th through-hole and the 7th through-hole make
The first source drain metal layer is obtained to connect with the anode layer.
According to another aspect of the present invention, a kind of AMOLED display screens are provided：
The buffer layer and polysilicon layer formed including substrate, on substrate；
Further include gate metal layer, storage capacitance metal layer, the first source drain metal layer, the second source drain metal
Layer, planarization layer, anode layer and multiple interlayer insulating films；
Wherein the multiple interlayer insulating film respectively be located at the polysilicon layer, gate metal layer, storage capacitance metal layer,
Between first source drain metal layer, the second source drain metal layer and each layer of planarization layer, the anode layer is located at described flat
On smoothization layer；
Wherein described second source drain metal layer is the metal layer of whole face covering, and the second source drain metal layer leads to
Through-hole is crossed to connect with the first source drain metal layer, polysilicon layer and storage capacitance metal layer.
Optionally, the second source drain metal layer for do not include pattern metal layer and/or,
The second source drain metal layer is the metal layer made of titanium-aluminium-titanium-composite construction.
Optionally, at least two that etching formation is provided on the insulating layer on the first source drain metal layer upper strata are logical
Hole, the second source drain metal layer pass through at least two through-hole and the first source drain metal layer, polysilicon
Layer is connected with storage capacitance metal layer.
Optionally, the first insulating layer in the multiple interlayer insulating film is located on the polysilicon layer；
The gate metal layer is located on first insulating layer；
Second insulating layer in the multiple interlayer insulating film is located in the gate metal layer；
The storage capacitance metal layer is located in the second insulating layer；
Third insulating layer in the multiple interlayer insulating film is located on the storage capacitance metal layer；
The first source drain metal layer is located on the third insulating layer；
The 4th insulating layer in the multiple interlayer insulating film is located on the first source drain metal layer；
The second source drain metal layer is located on the 4th insulating layer；
The 5th insulating layer in the multiple interlayer insulating film is located on the second source drain metal layer；
The planarization layer is located on the 5th insulating layer；
The anode layer is located on the planarization layer.
It can be found that the technical solution of the embodiment of the present invention, after forming buffer layer and polysilicon layer on substrate, then distinguishes
Formed gate metal layer, storage capacitance metal layer, the first source drain metal layer, the second source drain metal layer, planarization layer,
Anode layer and multiple interlayer insulating films；Wherein the second source drain metal layer is the metal layer that increases newly of the embodiment of the present invention, this
Two source drain metal layers are the metal layer of whole face covering, by through-hole and the first source drain metal layer, polysilicon layer and are deposited
Storing up electricity holds metal layer connection.Because increasing entire SD1 metal layers, it is equivalent to VDDCabling impedance design is uniformly covered for whole face
Lid, then VDDWalking line impedence will become smaller, and then reduce VDDCabling by input proximal end to the generation of distal end voltage drop, from
And the problem of being effectively improved display area light emission luminance is uneven as caused by IR_Drop, improve the aobvious of AMOLED display screens
Show effect.
Further, the second source drain metal layer of the embodiment of the present invention can be the metal for not including pattern
Layer and/or, the second source drain metal layer may be used TiAlTi (titanium-aluminium-titanium-composite construction) making.
Further, the second source drain metal layer of the embodiment of the present invention is in the first source drain metal
It is formed on the insulating layer on layer upper strata；The second source drain metal layer upper strata re-forms insulating layer.
Description of the drawings
Disclosure illustrative embodiments are described in more detail in conjunction with the accompanying drawings, the disclosure above-mentioned and its
Its purpose, feature and advantage will be apparent, wherein, in disclosure illustrative embodiments, identical reference label
Typically represent same parts.
Fig. 1 is a kind of schematic flow chart of display screen production method according to an embodiment of the invention；
Fig. 2 is a kind of another schematic flow chart of display screen production method according to an embodiment of the invention；
Fig. 3 is the pixel circuit schematic diagram of 2T1C structures involved according to one embodiment of present invention；
Fig. 4 is a kind of structure diagram of AMOLED display screens according to an embodiment of the invention.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.
Although showing the preferred embodiment of the disclosure in attached drawing, however, it is to be appreciated that may be realized in various forms
The disclosure by embodiments set forth herein without should be limited.On the contrary, these embodiments are provided so that the disclosure more
Add thorough and complete, and the scope of the present disclosure can be completely communicated to those skilled in the art.
The present invention provides a kind of display screen production method, can improve the light emission luminance uniformity of display screen, improves AMOLED
The display effect of display screen.
Below in conjunction with the technical solution of the attached drawing detailed description embodiment of the present invention.
Fig. 1 is a kind of schematic flow chart of display screen production method according to an embodiment of the invention.
Reference Fig. 1, the method includes：
In a step 101, buffer layer and polysilicon layer are formed on substrate.
In the step, buffer layer and amorphous silicon layer can be formed on substrate, the amorphous silicon layer is then turned into polycrystalline
Silicon layer.
Wherein, aforesaid substrate can be glass substrate or flexible base board etc., and flexible base board can be flexible polymer
Substrate etc..
The amorphous silicon layer can be turned to polysilicon layer by the step by modes such as laser annealing techniques.It should be noted
It is that can also use other modes that the amorphous silicon layer is turned to polysilicon layer, the present invention is simultaneously not limited.
In a step 102, gate metal layer, storage capacitance metal layer, the first source drain metal layer, second are respectively formed
Source drain metal layer, planarization layer, anode layer and multiple interlayer insulating films；Wherein the multiple interlayer insulating film is located at respectively
The polysilicon layer, gate metal layer, storage capacitance metal layer, the first source drain metal layer, the second source drain metal layer
And between each layer of planarization layer, the anode layer is located on the planarization layer；Wherein described second source drain metal layer is
The metal layer of whole face covering is connected by through-hole and the first source drain metal layer, polysilicon layer and storage capacitance metal layer
It connects.
Wherein, the first source drain metal layer is also referred to as SD metal layers, and the second source drain metal layer is also referred to as SD1 metals
Layer.
Wherein, the second source drain metal layer can be do not include pattern metal layer and/or, second source
Pole drain metal layer may be used TiAlTi (titanium-aluminium-titanium-composite construction) and be made.
Wherein, the second source drain metal layer is the shape on the insulating layer on the first source drain metal layer upper strata
Into；The second source drain metal layer upper strata re-forms insulating layer.
Wherein, it can etch to form at least two through-holes on the insulating layer on the first source drain metal layer upper strata,
Pass through at least two through-hole the second source drain metal layer and the first source drain metal layer, polysilicon
Layer is connected with storage capacitance metal layer.
It can be found that the technical solution of the embodiment of the present invention, after forming buffer layer and polysilicon layer on substrate, then distinguishes
Formed gate metal layer, storage capacitance metal layer, the first source drain metal layer, the second source drain metal layer, planarization layer,
Anode layer and multiple interlayer insulating films；Wherein the second source drain metal layer is the metal layer that increases newly of the embodiment of the present invention, this
Two source drain metal layers are the metal layer of whole face covering, by through-hole and the first source drain metal layer, polysilicon layer and are deposited
Storing up electricity holds metal layer connection.Because increasing entire SD1 metal layers, it is equivalent to VDDCabling impedance design is uniformly covered for whole face
Lid, then VDDWalking line impedence will become smaller, and then reduce VDDCabling by input proximal end to the generation of distal end voltage drop, from
And the problem of being effectively improved display area light emission luminance is uneven as caused by IR_Drop, improve the aobvious of AMOLED display screens
Show effect.
Fig. 2 is a kind of another schematic flow chart of display screen production method according to an embodiment of the invention.Fig. 2
The display screen production method of the present invention is described in more detail relative to Fig. 1 for shown method.
In existing the relevant technologies, due to V caused by pressure dropDDThe difference of voltage can produce in each pixel circuit of display screen
Raw different electric current, it is uneven so as to cause display screen light emission luminance.Scheme provided in an embodiment of the present invention, by changing VDD
Cabling impedance design can improve by inputting proximal end to the V of distal endDDBrightness disproportionation problem caused by voltage differences, in addition may be used also
To improve the service life of OLED and luminous efficiency.
It is illustrated with the pixel circuit of the 2T1C structures of Fig. 3.Fig. 3 includes 1 driving TFF (Driving TFT), 1
A switch TFT (Switching TFT), 1 storage capacitance Cst and 1 OLED, wherein VDDIt is power supply high voltage, Vss is electricity
Source low-voltage, Data are data-signals, and Scan is scanning signal.Wherein, data-signal is reached and is driven after switch TFT is opened
The grid of dynamic TFT so as to control the size of current of driving TFT, and then controls the brightness of OLED.
When TFT is driven to be operated in saturation region pattern, the operating current I of TFT is drivendFor：
Wherein, electron mobilities of the μ for raceway groove, CoxFor the channel capacitance of driving transistor unit area, W is driving crystalline substance
The channel width of body pipe, channel lengths of the L for driving transistor, VsgFor the voltage between the source electrode and grid of driving transistor,
VthFor the threshold voltage (also referred to as cut-in voltage) of driving transistor, VDDFor power supply high voltage, VgGrid for driving transistor
Voltage.
It can be found from above-mentioned formula, the pixel driving current and V of display screen difference display areaDDThere are positives for voltage swing
Guan Xing.Since there are V in the designing scheme of the prior artDDThe larger problem of line impedence is walked, causes to input proximal end and input distal end
VDDVoltage value differs greatly, and OLED light emission luminance and input current IdCurrent difference that is directly proportional, being generated when voltage differences are big
It is different also big, so if the V of entire display area can be madeDDVoltage maintain it is smaller than more uniform level namely voltage differences,
It can be so that the difference of the current value generated in each pixel circuit reduces, so as to improve asking for OLED display screen brightness disproportionation
Topic.
Therefore, the present invention is according to above-mentioned analysis, it is proposed that a kind of display screen that display effect is improved by improving IR_Drop
Production method mainly in back plate design, increases by one layer of entire VDDRouting layer namely increase source drain metal layer (SD1
Metal layer), and pass through through-hole (via) and be connected to each pixel.Because increasing entire SD1 metal layers, it is equivalent to VDD
Cabling impedance design is whole face uniform fold, then VDDWalking line impedence will become smaller, and then reduce VDDCabling by input proximal end to
The voltage drop namely voltage differences of the generation of distal end become smaller, it is possible to so that the current value difference in each pixel circuit becomes smaller,
The problem of light emission luminance is uneven as caused by IR_Drop so as to being effectively improved display area.
Technical solution of the embodiment of the present invention is described in detail referring to Fig. 2, method described in Fig. 2 includes：
In step 201, buffer layer and amorphous silicon layer are formed on the glass substrate, and the amorphous silicon layer is turned into polysilicon
Layer.
The step is illustrated by glass substrate of substrate but not limited to this or in other types substrate for example
Buffer layer and amorphous silicon layer are formed on flexible base board.
The amorphous silicon layer can be turned to polysilicon layer by the step by modes such as laser annealing techniques.It should be noted
It is that can also use other modes that the amorphous silicon layer is turned to polysilicon layer, the present invention is simultaneously not limited.
In step 202, the first insulating layer is formed on the polysilicon layer.
Wherein, the insulating layer of the embodiment of the present invention is formed using insulating materials, these insulating materials for example can be SiNx
(silicon nitride), SiO2(silica) or TiO2(titanium dioxide) etc. but not limited to this.
In step 203, gate metal layer is formed on first insulating layer.
In step 204, second insulating layer is formed in the gate metal layer.
In step 205, Cst metal layers (storage capacitance metal layer) are formed in the second insulating layer.
In step 206, third insulating layer is formed on the Cst metal layers.
Wherein, it performs etching to form first through hole, the second through-hole and third through-hole in the third insulating layer, described first
Through-hole is connected with polysilicon layer, and second through-hole is connected with gate metal layer, and third through-hole is connected with Cst metal layers.
It is formed, can also be formed using other modes it should be noted that etching may be used in through-hole, the present invention is not limited
It is fixed.
In step 207, SD metal layers (the first source drain metal layer) are formed on the third insulating layer.
In the embodiment of the present invention, TiAlTi (titanium-aluminium-titanium-composite construction) making may be used in SD metal layers.SD metal layers
It generally requires MASK (mask) and is etched pattern, etched pattern includes more than one.V on SD metal layersDDCabling can basis
The design of different manufacturers and it is different.
In a step 208, the 4th insulating layer is formed on the SD metal layers.
Wherein, it performs etching to form fourth hole and fifth hole in the 4th insulating layer, the fourth hole and
One through-hole corresponds to SD metal layers position and is connected, and fifth hole SD metal layers position corresponding with third through-hole is connected.
The SD metal layers of the embodiment of the present invention can play snap action so that newly-installed VDDRouting layer namely SD1 gold
Belonging to layer can connect with the polysilicon layer and Cst metal layers of lower floor.
In step 209, SD1 metal layers (the second source drain metal layer) are formed on the 4th insulating layer.
In the embodiment of the present invention, increase by one layer of entire VDDRouting layer namely on the insulating layer increase SD1 metal layers.Its
In, TiAlTi (titanium-aluminium-titanium-composite construction) making may be used in SD1 metal layers.
The SD1 metal layers of the embodiment of the present invention, do not need to pattern-making, it is only necessary to set one layer of metal.SD1 gold
Belong to layer and could be provided as whole face covering metal, can be attached in this way in the corresponding position of each sub-pixel by through-hole.
Because increasing entire SD1 metal layers, it is whole face uniform fold to be equivalent to VDD cablings impedance design, then VDDCabling hinders
It is anti-to become smaller, and then reduce VDDCabling is aobvious so as to be effectively improved by inputting proximal end to the voltage drop of the generation of distal end
The problem of showing region light emission luminance be uneven as caused by IR_Drop.
Detailed analysis is carried out below：
Generally for the resistive element of sectional uniform, resistance value is
In above-mentioned formula, ρ is the resistivity (Europe centimetre) of resistance material, and L is the length (centimetre) of resistive element, and A is electricity
The sectional area (square centimeter) of resistance body.
For film resistor, thickness d very little is generally more difficult to survey standard, and ρ changes again with the thickness d of film resistor,
Therefore it generally will be regarded as the constant related with thin-film material and be known as film resistance, actually the resistance value of its namely square film,
Therefore also known as sheet resistance Rs (Europe/side).Usual Rs values are in a limited range, and Rs too conferences influence the stabilization of resistor performance.This
SD1 metal layers are one layer of uniform films in inventive embodiments, itself are also as a resistive element, belong to a kind of planar shaped resistance
Body.
The resistance value R and the relationship of sheet resistance Rs of SD1 metal layers are as follows：
W in above-mentioned formula is the width (centimetre) of film.
It can be found that the embodiment of the present invention increases one layer of SD1 metal layer, SD1 metal layers are also one layer uniformly thin
Film, by VDDCabling impedance design is the thin-film width W in SD1 metal layer whole face uniform folds namely in increasing above-mentioned formula,
The resistance value R of so SD1 metal layers will become smaller namely VDDWalking line impedence will become smaller, and then reduce VDDCabling is near by inputting
Hold the voltage drop to distal end, it is possible to so that the current value difference in each pixel circuit becomes smaller, it is aobvious so as to be effectively improved
The problem of showing region light emission luminance is uneven as caused by IR_Drop, the display effect of display screen is improved.
In step 210, the 5th insulating layer is formed on the SD1 metal layers.
In step 211, PLN layers (planarization layers) are formed on the 5th insulating layer.
Wherein, it performs etching to form the 6th through-hole and the 7th through-hole at described PLN layers, the 7th through-hole and the 8th leads to
SD metal layers, ANODE layers of connection is realized together in hole.
In the step 212, ANODE layers (anode layers) are formed on the PLN layers.
It can be found that the technical solution of the embodiment of the present invention, passes through a kind of reduction VDDThe mode of line impedence is walked, solves mesh
Preceding OLED generally existings as caused by IR_Drop pressure drops the problem of brightness disproportionation.Specifically, it is the increase in entire SD1
Metal layer is equivalent to VDDCabling impedance design is whole face uniform fold, then VDDWalking line impedence will become smaller, and then reduce
VDDCabling is become smaller by the voltage drop namely voltage differences for inputting proximal end to the generation of distal end, it is possible to so that each pixel circuit
In current value difference become smaller, the problem of light emission luminance is uneven as caused by IR_Drop so as to being effectively improved display area.
In addition it is possible to avoid OLED be chronically at luminance difference it is larger in the case of, luminescent material consumption is different and cause in pixel
Different zones aging variation sex chromosome mosaicism.
The above-mentioned display screen production method for describing the present invention in detail, the knot of corresponding AMOLED display screens introduced below
Structure.
Fig. 4 is a kind of structure diagram of AMOLED display screens according to an embodiment of the invention.
The structure of AMOLED display screens, attached drawing in Fig. 4 are illustrated in Fig. 4 with conventional 2T1C dot structures section
Label includes：Substrate 1, buffer layer 2, polysilicon layer 3, the first insulating layer 4, gate metal layer 5, second insulating layer 6, Cst metals
Layer 7, third insulating layer 8, SD metal layers 9, the 4th insulating layer 10, SD1 metal layers 11, the 5th insulating layer 12, PLN layers 13, ANODE
Layer 14, first through hole 21, the second through-hole 22, third through-hole 23, fourth hole 24, fifth hole 25, the 6th through-hole the 26, the 7th
Through-hole 27.
With reference to Fig. 4, present example provides a kind of AMOLED display screens：
The AMOLED display screens include substrate 1, the buffer layer 2 formed on substrate 1 and polysilicon layer 3；
Further include gate metal layer 5, the 7, first source drain metal layer of storage capacitance metal layer (Cst metal layers) (SD gold
Belong to layer) the 9, second source drain metal layer (SD1 metal layers) 11, planarization layer (PLN layers) 13, anode layer 14 and multiple interlayers it is exhausted
Edge layer (the first insulating layer 4, second insulating layer 6, third insulating layer 8, the 4th insulating layer 10, the 5th insulating layer 12)；
Wherein the multiple interlayer insulating film is located at the polysilicon layer 3, gate metal layer 5, storage capacitance metal respectively
Between layer 13 each layer of the 7, first source drain metal layer 9, the second source drain metal layer 11 and planarization layer, the anode layer 14
On the planarization layer 13；
Metal layer of the wherein described second source drain metal layer 11 for whole face covering, the second source drain metal layer
11 are connect by through-hole with the first source drain metal layer 9, polysilicon layer 3 and storage capacitance metal layer 7.
Wherein, substrate 1 can be glass substrate or flexible base board etc., and flexible base board can be flexible polymer substrate
Deng.
Wherein, SD1 metal layers 11 can be do not include pattern metal layer and/or, SD1 metal layers 11 can be use
The metal layer that TiAlTi (titanium-aluminium-titanium-composite construction) makes.
Wherein, SD metal layers 9 for the metal layer comprising pattern and/or, SD metal layers 9 can be using TiAlTi (titanium-
Aluminium-titanium-composite construction) make metal layer.
Wherein, at least two through-holes that etching is formed, the SD1 metals are provided on the insulating layer on 9 upper strata of SD metal layers
Layer 11 is connect by least two through-hole with SD metal layers 9, polysilicon layer 3 and Cst metal layers 7.
Wherein, the first insulating layer 4 in the multiple interlayer insulating film is located on the polysilicon layer 3；
The gate metal layer 5 is located on first insulating layer 4；
Second insulating layer 6 in the multiple interlayer insulating film is located in the gate metal layer 5；
The Cst metal layers 7 are located in the second insulating layer 6；
Third insulating layer 8 in the multiple interlayer insulating film is located on the Cst metal layers 7；
The SD metal layers 9 are located on the third insulating layer 8；
The 4th insulating layer 10 in the multiple interlayer insulating film is located on the SD metal layers 9；
The SD1 metal layers 11 are located on the 4th insulating layer 10；
The 5th insulating layer 12 in the multiple interlayer insulating film is located on the SD1 metal layers 11；
The PLN layers 13 are located on the 5th insulating layer 12；
The ANODE layers 14 are located on the PLN layers 13.
Wherein, first through hole 21, the second through-hole 22 and third through-hole 23 are formed in the third insulating layer 8 etching, wherein
The first through hole 21 is connected with the polysilicon layer 3, and second through-hole 22 is connected with the gate metal layer 5, and described
Three through-holes 23 are connected with the Cst metal layers 7；
The 4th insulating layer 10 etching form fourth hole 24 and fifth hole 25, wherein the fourth hole 24 with
21 corresponding 9 position of SD metal layers of first through hole is connected, the fifth hole 25 and the 23 corresponding SD of third through-hole
9 position of metal layer is connected；
It is etched in the PLN layers 13 and forms the 6th through-hole 26 and the 7th through-hole 27, wherein the 6th through-hole 26 and the 7th
Through-hole 27 is so that the SD metal layers 9 are connect with the ANODE layers 14.
The present invention also provides a kind of display devices, have used above-mentioned structure shown in Fig. 4.The display device can be：
Liquid crystal display panel, Electronic Paper, LCD TV, liquid crystal display, Digital Frame, mobile phone, tablet computer etc. are any to have display function
Product or component.
In conclusion the technical solution of the embodiment of the present invention, after forming buffer layer and polysilicon layer on substrate, then distinguishes
Formed gate metal layer, storage capacitance metal layer, the first source drain metal layer, the second source drain metal layer, planarization layer,
Anode layer and multiple interlayer insulating films；Wherein the second source drain metal layer is the metal layer that increases newly of the embodiment of the present invention, this
Two source drain metal layers are the metal layer of whole face covering, by through-hole and the first source drain metal layer, polysilicon layer and are deposited
Storing up electricity holds metal layer connection.Because increasing entire SD1 metal layers, it is equivalent to VDDCabling impedance design is uniformly covered for whole face
Lid, then VDDWalking line impedence will become smaller, and then reduce VDDCabling by input proximal end to the generation of distal end voltage drop, from
And the problem of being effectively improved display area light emission luminance is uneven as caused by IR_Drop, improve the aobvious of AMOLED display screens
Show effect.Furthermore it is also possible to improve the service life and luminous efficiency of OLED.
Above it is described in detail according to the technique and scheme of the present invention by reference to attached drawing.
It will be understood by those of ordinary skill in the art that：The above is only a specific embodiment of the present invention, not
For limiting the present invention, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all
It is included within protection scope of the present invention.
Claims (10)
1. a kind of display screen production method, which is characterized in that including：
Buffer layer and polysilicon layer are formed on substrate；
Be respectively formed gate metal layer, storage capacitance metal layer, the first source drain metal layer, the second source drain metal layer,
Planarization layer, anode layer and multiple interlayer insulating films；
Wherein the multiple interlayer insulating film is located at the polysilicon layer, gate metal layer, storage capacitance metal layer, first respectively
Between source drain metal layer, the second source drain metal layer and each layer of planarization layer, the anode layer is located at the planarization
On layer；
Wherein described second source drain metal layer is the metal layer of whole face covering, passes through through-hole and first source drain gold
Belong to layer, polysilicon layer is connected with storage capacitance metal layer.
2. according to the method described in claim 1, it is characterized in that：
The second source drain metal layer for do not include pattern metal layer and/or,
The second source drain metal layer is made of titanium-aluminium-titanium-composite construction.
3. according to the method described in claim 1, it is characterized in that：
The second source drain metal layer is formed on the insulating layer on the first source drain metal layer upper strata；
The second source drain metal layer upper strata re-forms insulating layer.
4. according to the method described in claim 3, it is characterized in that, the method further includes：
Etching forms at least two through-holes on the insulating layer on the first source drain metal layer upper strata, passes through described at least two
A through-hole causes the second source drain metal layer and the first source drain metal layer, polysilicon layer and storage capacitance gold
Belong to layer connection.
5. method according to any one of claims 1 to 4, which is characterized in that described to be respectively formed gate metal layer, storage
Capacitance metal layer, the first source drain metal layer, the second source drain metal layer, planarization layer, anode layer and multiple interlayers are exhausted
Edge layer, including：
The first insulating layer is formed on the polysilicon layer；
Gate metal layer is formed on first insulating layer；
Second insulating layer is formed in the gate metal layer；
Storage capacitance metal layer is formed in the second insulating layer；
Third insulating layer is formed on the storage capacitance metal layer；
The first source drain metal layer is formed on the third insulating layer；
The 4th insulating layer is formed on the first source drain metal layer；
The second source drain metal layer is formed on the 4th insulating layer；
The 5th insulating layer is formed on the second source drain metal layer；
Planarization layer is formed on the 5th insulating layer；
Anode layer is formed on the planarization layer.
6. according to the method described in claim 5, it is characterized in that, the method further includes：
It etches to form first through hole, the second through-hole and third through-hole in the third insulating layer, wherein the first through hole and institute
It states polysilicon layer to be connected, second through-hole is connected with the gate metal layer, the third through-hole and storage capacitance gold
Belong to layer to be connected；
It etches to form fourth hole and fifth hole in the 4th insulating layer, wherein the fourth hole and the first through hole
Corresponding first source drain metal layer position is connected, the fifth hole the first source drain corresponding with the third through-hole
Metal layer position is connected；
It etches to form the 6th through-hole and the 7th through-hole in the planarization layer, wherein the 6th through-hole and the 7th through-hole cause institute
The first source drain metal layer is stated to connect with the anode layer.
7. a kind of AMOLED display screens, it is characterised in that：
The buffer layer and polysilicon layer formed including substrate, on substrate；
It further includes gate metal layer, storage capacitance metal layer, the first source drain metal layer, the second source drain metal layer, put down
Smoothization layer, anode layer and multiple interlayer insulating films；
Wherein the multiple interlayer insulating film is located at the polysilicon layer, gate metal layer, storage capacitance metal layer, first respectively
Between source drain metal layer, the second source drain metal layer and each layer of planarization layer, the anode layer is located at the planarization
On layer；
Wherein described second source drain metal layer is the metal layer of whole face covering, and the second source drain metal layer passes through logical
Hole is connect with the first source drain metal layer, polysilicon layer and storage capacitance metal layer.
8. AMOLED display screens according to claim 7, it is characterised in that：
The second source drain metal layer for do not include pattern metal layer and/or,
The second source drain metal layer is the metal layer made of titanium-aluminium-titanium-composite construction.
9. AMOLED display screens according to claim 7, it is characterised in that：
Be provided on the insulating layer on the first source drain metal layer upper strata etching formed at least two through-holes, described second
Source drain metal layer passes through at least two through-hole and the first source drain metal layer, polysilicon layer and storage capacitance
Metal layer connects.
10. AMOLED display screens according to any one of claims 7 to 9, it is characterised in that：
The first insulating layer in the multiple interlayer insulating film is located on the polysilicon layer；
The gate metal layer is located on first insulating layer；
Second insulating layer in the multiple interlayer insulating film is located in the gate metal layer；
The storage capacitance metal layer is located in the second insulating layer；
Third insulating layer in the multiple interlayer insulating film is located on the storage capacitance metal layer；
The first source drain metal layer is located on the third insulating layer；
The 4th insulating layer in the multiple interlayer insulating film is located on the first source drain metal layer；
The second source drain metal layer is located on the 4th insulating layer；
The 5th insulating layer in the multiple interlayer insulating film is located on the second source drain metal layer；
The planarization layer is located on the 5th insulating layer；
The anode layer is located on the planarization layer.
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| US12002424B2 (en) | 2021-04-30 | 2024-06-04 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate and display device |
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