CN108231834B

CN108231834B - Light emitting display device and method of manufacturing the same

Info

Publication number: CN108231834B
Application number: CN201711267179.7A
Authority: CN
Inventors: 金钟成; 金豪镇; 白承旼
Original assignee: LG Display Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 2016-12-14
Filing date: 2017-12-05
Publication date: 2021-11-05
Anticipated expiration: 2037-12-05
Also published as: CN108231834A; KR20180068549A; JP6612305B2; US10692947B2; EP3336899B1; EP3336899A1; JP2018098185A; TWI647837B; TW201822348A; US20180166522A1

Abstract

Disclosed are a light emitting display device and a method of manufacturing the same, which prevent the life span of a light emitting layer from being shortened and prevent conduction defects from occurring. The light emitting display device includes a plurality of pixels each including: a transistor having a gate electrode, an active layer overlapping the gate electrode, a source electrode connected to one side of the active layer, and a drain electrode connected to the other side of the active layer. The plurality of pixels further includes a light emitting device having a first electrode, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer. The light emitting display device includes a contact hole in which first electrodes of at least two of the plurality of pixels are electrically connected to a side surface of a corresponding source electrode or a side surface of a corresponding drain electrode.

Description

Light emitting display device and method of manufacturing the same

Technical Field

The present disclosure relates to a light emitting display device and a method of manufacturing the same.

Background

With the development of the information-oriented society, various demands for display devices for displaying images are increasing. Accordingly, various display devices such as a Liquid Crystal Display (LCD) device, a Plasma Display Panel (PDP) device, a light emitting display device, and the like are being used recently.

A light emitting display device including an organic light emitting display device is a self-luminous display device and is better than an LCD device in view angle and contrast. In addition, since the organic light emitting display device does not require a separate backlight, the organic light emitting display device can be made light and thin, and power consumption of the organic light emitting display device is excellent. In addition, the organic light emitting display device is driven with a low Direct Current (DC) voltage, has a fast response time, and is low in manufacturing cost.

The organic light emitting display devices each include an anode, a bank dividing the anode, a hole transport layer, an organic light emitting layer, and an electron transport layer formed on the anode, and a cathode formed on the electron transport layer. In this case, when a high-level voltage is applied to the anode and a low-level voltage is applied to the cathode, holes and electrons move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and recombine with each other in the organic light emitting layer to emit light.

In the organic light emitting display device, pixels that emit light are formed in respective regions in which an anode, an organic light emitting layer, and a cathode are sequentially stacked. Banks are disposed in the respective non-light emitting regions where light is not emitted. That is, the bank functions as a pixel defining layer defining a pixel.

The anode is connected to a source or drain of a Thin Film Transistor (TFT) through a contact hole, and is supplied with a high-level voltage through the TFT. It is difficult for the organic light emitting layer to be uniformly deposited in the contact hole due to the step height of the contact hole, and thus, the organic light emitting layer is covered by the bank without being formed in the contact hole.

Recently, head-mounted displays including organic light emitting display devices are being developed. Head-mounted displays are monitor devices for Virtual Reality (VR) or Augmented Reality (AR), which are worn as glasses or helmets and form a focus at a distance close to the eyes of a user. Small organic light emitting display devices applied to head-mounted displays, mobile devices, and the like have high resolution, and thus the size of each pixel is gradually reduced.

However, the contact hole is formed through a photolithography process, and the contact hole cannot be formed to have a certain size or less due to the limitation of the photolithography process. That is, although the size of the pixel is reduced, there is a limitation in reducing the size of the contact hole. Specifically, the contact hole is provided in the non-light emitting region, and therefore, when the size of the pixel is reduced, the area ratio of the non-light emitting region in the pixel is increased, and the area ratio of the light emitting region in the pixel is reduced. If the area ratio of the light emitting region in the pixel is reduced, the luminance of the light emitting region should be increased in order to compensate for the reduced ratio of the light emitting region, and for this reason, the life of the organic light emitting layer is shortened.

In addition, if the size of the pixel is reduced, the size of the source or drain of the TFT may become smaller than that of the contact hole. In this case, the anode electrode is not formed only on the upper surface of the source or drain electrode exposed through the contact hole, but may be formed on the bottom of the contact hole and the side surface of the source or drain electrode. Thus, as shown in fig. 1A and 1B. The anode may be disconnected in the side surface of the source or drain electrode due to the step height between the bottom of the contact hole and the source or drain electrode. Therefore, an on defect in which the pixel does not emit light occurs.

Disclosure of Invention

Accordingly, the present disclosure is directed to a light emitting display device and a method of fabricating the same that substantially obviate one or more problems due to limitations and disadvantages of the related art.

An aspect of the present disclosure is directed to provide a light emitting display device and a method of manufacturing the same that prevents a reduction in the life of a light emitting layer.

Another aspect of the present disclosure is directed to provide a light emitting display device preventing an on defect from occurring and a method of manufacturing the same.

Additional advantages and features of the disclosure will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the disclosure. The objectives and other advantages of the disclosure will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, there is provided a light emitting display device including a plurality of pixels, each of the plurality of pixels including: a transistor having a gate electrode, an active layer overlapping the gate electrode, a source electrode connected to one side of the active layer, and a drain electrode connected to the other side of the active layer; and a light emitting device having a first electrode, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer. The light emitting display device includes a contact hole in which first electrodes of at least two of the plurality of pixels are electrically connected to a side surface of the corresponding source electrode or a side surface of the corresponding drain electrode.

In another aspect of the present disclosure, a light emitting display device is provided, which includes a plurality of pixels and a contact hole. Each of the plurality of pixels includes: a transistor having a gate, a source region, and a drain region; a source coupled to the source region; a drain coupled to the drain region; an auxiliary electrode coupled to one of the source or the drain; and a first electrode of a light emitting device coupled to the auxiliary electrode. The first electrodes of at least two pixels of the plurality of pixels are electrically connected to side surfaces of the respective auxiliary electrodes in the contact holes.

It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure. In the drawings:

fig. 1A and 1B are exemplary views illustrating an example in which an anode and a cathode are short-circuited due to a step height of a contact hole when an organic light emitting layer is formed in the contact hole;

fig. 2 is a perspective view illustrating an organic light emitting display device according to one or more embodiments of the present disclosure;

fig. 3 is a plan view illustrating further details of the organic light emitting display device of fig. 2;

fig. 4 is a plan view illustrating in detail an example of a pixel in a display area according to one or more embodiments of the present disclosure;

FIG. 5 is a sectional view taken along line I-I' of FIG. 4;

FIG. 6 is an enlarged cross-sectional view of region A of FIG. 5;

fig. 7 is a flowchart illustrating a method of manufacturing an organic light emitting display device according to one or more embodiments of the present disclosure;

fig. 8A to 8F are sectional views taken along line I-I' of fig. 4 for describing a method of manufacturing the organic light emitting display device of fig. 7, according to an embodiment of the present disclosure;

fig. 9 is a plan view illustrating in detail another example of a pixel in a display area according to one or more embodiments of the present disclosure;

FIG. 10 is a sectional view taken along line III-III' of FIG. 9;

fig. 11 is a flowchart illustrating a method of manufacturing an organic light emitting display device according to one or more embodiments of the present disclosure;

fig. 12A to 12H are sectional views taken along line III-III of fig. 9 for describing a method of manufacturing the organic light emitting display device of fig. 11, according to an embodiment of the present disclosure;

fig. 13A and 13B are plan views illustrating in detail another example of a pixel in a display area according to an embodiment of the present disclosure;

fig. 14A and 14B are plan views illustrating in detail another example of pixels in a display area according to an embodiment of the present disclosure; and

fig. 15A and 15B are plan views illustrating in detail another example of pixels in a display area according to an embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible or convenient to describe the various embodiments provided herein, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

In the following description, a detailed description of well-known functions, features, or configurations may be omitted where included to otherwise obscure the description of the various embodiments of the present disclosure. Terms described in the specification should be understood as follows.

Advantages and features of the present disclosure and methods of accomplishing the same will be provided by the following exemplary embodiments described with reference to the accompanying drawings. This disclosure may, however, be embodied in different forms and should not be construed as limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art.

The shapes, sizes, proportions, angles and numbers of the embodiments disclosed in the drawings for describing the present disclosure are exemplary only, and thus the present disclosure is not limited to the details shown.

Terms such as "comprising," having, "and" including "used in this specification have an inclusive meaning and may include additional components, elements, features, and the like, unless expressly limited by a term such as" only. Unless expressly limited to the singular, singular terms may include the plural.

In interpreting the elements, the elements are interpreted to include the error range, although there is no explicit description of the error range.

In describing the positional relationship, for example, when the positional relationship between two components is described as "on …", "above …", "below …", and "next to …", one or more other components may be provided between the two components unless explicit limiting terms such as "only" or "directly" are used.

In describing temporal relationships, for example, when temporal sequences are described as "after …", "subsequent", "next", and "before …", instances of non-sequential order may be included unless a specific limiting term such as "only" or "directly" is used.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

As used herein, the X-axis direction, the Y-axis direction, and the Z-axis direction should not be construed to represent any particular geometric relationship or direction (e.g., vertical or horizontal), but are instead intended to have a broader directionality within the scope of the elements of the present disclosure that function normally.

The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of a first item, a second item, and a third item" includes all combinations of two or more of any of the first item, the second item, and the third item, as well as any of the first item, the second item, or the third item.

As will be well understood by those skilled in the art, the features of the various embodiments of the present disclosure may be partially or fully coupled or combined with each other and may be variously interoperable with each other and technically driven. Embodiments of the present disclosure may be performed independently of each other or may be performed together in an interdependent relationship.

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 2 is a perspective view illustrating the organic light emitting display device 100 according to an embodiment of the present disclosure. Fig. 3 is a plan view illustrating other details of the organic light emitting display device 100 of fig. 2, such as a first substrate, a gate driver, a source drive Integrated Circuit (IC), a flexible film, a circuit board, and a timing controller.

Referring to fig. 2 and 3, the organic light emitting display device 100 according to an embodiment of the present disclosure may include a display panel 110, a gate driver 120, a source drive IC130, a flexible film 140, a circuit board 150, and a timing controller 160.

The display panel 110 may include a first substrate 111 and a second substrate 112. The second substrate 112 may be a package substrate. The first substrate 111 may be a plastic film, a glass substrate, or the like. The second substrate 112 may be a plastic film, a glass substrate, an encapsulation film (protective film), or the like.

A plurality of gate lines, a plurality of data lines, and a plurality of pixels P may be disposed on a surface of the first substrate 111 facing the second substrate 112. The pixels may be respectively disposed in a plurality of regions defined by the crossing structure of the gate and data lines.

Each of the pixels may include a Thin Film Transistor (TFT) and an organic light emitting device including a first electrode, an organic light emitting layer, and a second electrode. When a gate signal is input through the gate line, each of the pixels may supply a certain current to the organic light emitting device by using the TFT according to a data voltage supplied through the data line. Accordingly, the organic light emitting device of each of the pixels may emit light having a certain luminance according to a certain current. Various embodiments of the pixels will be described in further detail herein.

As shown in fig. 3, the display panel 110 may be divided into a display area DA in which pixels are disposed to display an image and a non-display area NDA in which an image is not displayed. The gate lines, the data lines, and the pixels may be disposed in the display area DA. The gate driver 120 and the plurality of pads may be disposed in the non-display area NDA.

The gate driver 120 may sequentially supply gate signals to the gate lines according to the gate control signal input from the timing controller 160. The gate driver 120 may be disposed in the non-display area NDA outside one or both sides of the display area DA of the display panel 110 in a gate driver in panel (GIP) type. Alternatively, the gate driver 120 may be manufactured as a driving chip and may be mounted on a flexible film, and further may be attached on the non-display area NDA outside one or both sides of the display area DA of the display panel 110 in a Tape Automated Bonding (TAB) type.

The source drive IC130 may receive digital video data and a source control signal from the timing controller 160. The source drive ICs 130 may convert digital video data into analog data voltages according to the source control signals, and may supply the analog data voltages to the data lines, respectively. If the source drive ICs 130 are manufactured as a driving chip, the source drive ICs 130 may be mounted on the flexible film 140 in a Chip On Film (COF) type or a Chip On Plastic (COP) type.

A plurality of pads such as data pads may be disposed in the non-display area NDA of the display panel 110. Lines connecting the pads to the source drive ICs 130 and lines connecting the pads with the lines of the circuit board 150 may be disposed on the flexible film 140. The flexible film 140 may be attached on the pad through an anisotropic conductive film, and thus, the pad may be connected to the wiring of the flexible film 140.

As shown, the circuit board 150 may be attached on the flexible film 140, and the flexible film 140 may be provided as a plurality of flexible films 140. A plurality of circuits implemented as driving chips may be mounted on the circuit board 150. For example, the timing controller 160 may be mounted on the circuit board 150. The circuit board 150 may be a Printed Circuit Board (PCB) or a Flexible Printed Circuit Board (FPCB).

The timing controller 160 may receive digital video data and timing signals from an external system board (not shown) through a cable of the circuit board 150. The timing controller 160 may generate a gate control signal for controlling an operation timing of the gate driver 120 and a source control signal for controlling the source drive ICs 130 based on the timing signal, and the source drive ICs 130 may be provided as a plurality of source drive ICs 130. The timing controller 160 may provide the gate control signal to the gate driver 120 and may provide the source control signal to the plurality of source drive ICs 130.

Fig. 4 is a plan view illustrating an example of a pixel in the display area in detail.

In fig. 4, for convenience of description, only the pixel P, the first electrode AND of the organic light emitting device, the light emitting area EA, the first AND second contact holes CT1 AND CT2, AND the common contact hole CTs are illustrated.

Referring to fig. 4, a plurality of pixels P may be provided, and each of the pixels P may include at least one TFT and an organic light emitting device.

The TFT may include an active layer, a gate electrode overlapping the active layer, a source electrode connected to one side of the active layer, and a drain electrode connected to the other side of the active layer. The active layer may include a source region, a drain region, and a channel region between the source region and the drain region. The source electrode may thus be connected to the source region of the active layer, and the drain electrode may be connected to the drain region of the active layer. The TFT may be replaced with another suitable transistor.

The organic light emitting device may include a first electrode AND corresponding to the anode, an organic light emitting layer, AND a second electrode corresponding to the cathode. The light emitting region EA may indicate a region in which the first electrode AND, the organic light emitting layer, AND the second electrode are sequentially stacked AND holes from the first electrode AND electrons from the second electrode are recombined in the organic light emitting layer to emit light. The light emitting areas EA of the neighboring pixels P may be separated by a bank, and thus, the bank may correspond to a non-light emitting area that does not emit light.

The first contact hole CT1 may be a contact hole formed for connecting the drain electrode of the TFT to the active layer. Accordingly, the drain electrode of the TFT may be connected to the active layer through the first contact hole CT 1.

The second contact hole CT2 may be a contact hole formed for connecting the source electrode of the TFT to the active layer. Accordingly, the source electrode of the TFT may be connected to the active layer through the second contact hole CT 2.

As shown in fig. 4, N (where N is an integer equal to or greater than 2) pixels P may share the common contact hole CTS. The common contact hole CTS may be a hole exposing the drain electrode of the TFT of each of the N pixels P. That is, the drains of the TFTs of the N pixels P may be exposed through the common contact hole CTS. The first electrode AND of the organic light emitting device of each of the N pixels P may be connected to the drain electrode of the corresponding TFT through the common contact hole CTS.

In fig. 4, N is exemplified as 4(N is 4), but the present embodiment is not limited thereto. For example, as shown in fig. 13A and 14A, N may be 2(N ═ 2), and as shown in fig. 15A, N may be 3(N ═ 3). As shown in fig. 13A, even when N is 2, pixels P adjacent to each other in a first direction (e.g., Y-axis direction) may share the common contact hole CTS, and as shown in fig. 14A, pixels P adjacent to each other in a second direction (e.g., X-axis direction) crossing the first direction (e.g., Y-axis direction) may share the common contact hole CTS. In addition, as shown in fig. 15A, when N is 3, the pixels P adjacent to each other in the triangular shape may share the common contact hole CTS.

As described above, in the embodiment of the present disclosure, the N pixels P may share the common contact hole CTS for connecting the first electrode of the organic light emitting device to the drain electrode of the TFT. Therefore, in the embodiment of the present disclosure, the reduction of the light emitting area EA is prevented by sharing the contact hole CTS, thereby preventing the reduction of the life span of the organic light emitting layer due to the reduction of the light emitting area EA.

In fig. 4, the common contact hole CTS is described to expose the drain electrode of the TFT for convenience of description, but the embodiment is not limited thereto. In other embodiments, the common contact hole CTS may expose the source of the TFT.

Fig. 5 is a sectional view illustrating an example taken along line I-I' of fig. 4.

Referring to fig. 5, a buffer layer (not shown) may be formed on a surface of the first substrate 111 facing the second substrate 112. A buffer layer may be formed on a surface of the first substrate 111 for protecting the plurality of TFTs 210 and the plurality of organic light emitting devices 260 from water permeated through the first substrate 111 that is easily permeated by water. The buffer layer may include a plurality of inorganic layers alternately stacked. For example, the buffer layer may be formed of a multi-layer in which one or more inorganic layers of silicon oxide (SiOx), silicon nitride (SiNx), and SiON are alternately stacked. The buffer layer may be omitted in various embodiments.

The TFT210 may be formed on the buffer layer. In fig. 5, it is illustrated that the first electrode 261 of each of the pixels P is connected to the drain electrode 214 of at least one TFT, but not limited thereto, the first electrode 261 may be connected to the source electrode 213 of at least one TFT.

Each of the TFTs 210 may include an active layer 211, a gate electrode 212, a source electrode 213, and a drain electrode 214. In fig. 5, it is exemplarily illustrated that the TFT210 is formed in a top gate type in which the gate electrode 212 is disposed on the active layer 211, but the embodiment provided herein is not limited thereto. In other embodiments, the TFT210 may be formed in a bottom gate type in which the gate electrode 212 is disposed under the active layer 211 or a double gate type in which the gate electrode 212 is disposed above the active layer 211 and under the active layer 211.

The active layer 211 may be formed on the buffer layer. The active layer 211 may be formed of any semiconductor material including a silicon-based semiconductor material or an oxide-based semiconductor material. A light blocking layer (not shown) for blocking external light from being incident on the active layer 211 may be formed between the buffer layer and the active layer 211.

The gate insulating layer 220 may be formed on the active layer 211. The gate insulating layer 220 may be formed of an inorganic layer such as silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer thereof.

The gate electrode 212 and the gate line may be formed on the gate insulating layer 220. The gate electrode 212 and the gate line may each be formed of a single layer or a multi-layer, which may include one of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. The gate electrode 212 may be connected to the gate line such that the gate electrode 212 receives a signal provided on the gate line.

An interlayer dielectric 230 may be formed on the gate electrode 212 and the gate line. The interlayer dielectric 230 may be formed of an inorganic layer such as SiOx, SiNx, or a multi-layer thereof.

The source electrode 213, the drain electrode 214, and the data line may be formed on the interlayer dielectric 230. The source electrode 213 may contact the active layer 211 through a second contact hole CT2 passing through the gate insulating layer 220 and the interlayer dielectric 230. The drain electrode 214 may contact the active layer 211 through a first contact hole CT1 passing through the gate insulating layer 220 and the interlayer dielectric 230. The source electrode 213, the drain electrode 214, and the data line may each be formed of a single layer or a plurality of layers including one of Mo, Cr, Ti, Ni, Nd, and Cu or an alloy thereof. The data line may be connected to the source electrode 213 so that a driving signal provided on the data line may be provided to the drain electrode 214 when the TFT is turned on by a gate signal provided at the gate electrode 212.

A passivation layer 240 for insulating the TFT210 may be formed on the source and drain

electrodes

213 and 214 and the data line. The passivation layer 240 may be formed of an inorganic layer such as SiOx, SiNx, or a multi-layer thereof.

A first planarization layer 250 for planarizing a step height caused by the TFT210 may be formed on the passivation layer 240. The first planarization layer 250 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

The organic light emitting device 260 and the bank 270 may be formed on the first planarization layer 250. The organic light emitting device 260 may include a first electrode 261, an organic light emitting layer 262, and a second electrode 263. The first electrode 261 may be an anode, and the second electrode 263 may be a cathode.

The first electrode 261 may be formed on the first planarization layer 250. The first electrode 261 may pass through the passivation layer 240 and the first planarization layer 250, and may be connected to a side surface of the drain electrode 214 of the TFT210 through a common contact hole CTS. The common contact hole CTS may be a hole passing through the first planarization layer 250, the passivation layer 240, and extending at least partially into the interlayer dielectric 230. Accordingly, a portion of the interlayer dielectric 230 is recessed or recessed in the common contact hole CTS. The common contact hole CTS may be formed by simultaneously etching the first planarization layer 250, the passivation layer 240, the drain electrode 214, and the interlayer dielectric 230. Accordingly, only a side surface of the drain electrode 214 of the TFT may be exposed through the common contact hole CTS, and thus, since the first electrode 261 extends along the side surface of the common contact hole CTS to be in contact with the exposed side surface of the drain electrode 214, the first electrode 261 may be connected to the exposed side surface of the drain electrode 214 of the TFT210 through the common contact hole CTS. The process of forming the common contact hole CTS will be described in more detail in operation (S103) of fig. 7.

As shown in further detail in fig. 6, the common contact hole CTS may include an entrance ENT, a bottom FL, and a contact region CNT. The first electrode 261 and the drain electrode 214 of the TFT210 are connected to each other in a contact region CNT located between the inlet ENT and the bottom FL. In order to connect the first electrode 261 to the drain electrode 214 of the TFT210, the common contact hole CTS may be formed to have an inclined sidewall in a tapered shape from the entrance ENT to the contact region CNT. A width W1 of the common contact hole CTS across the entrance ENT may be wider than a width W3 of the contact region CNT. Further, the first electrode 261 of the pixel P should be disconnected from the first electrode of another pixel P adjacent to the pixel P in the common contact hole CTS. Therefore, in order to form the first electrode 261 to be disconnected from the first electrode of the adjacent pixel P in the common contact hole CTS, the width W2 of the bottom FL of the common contact hole CTS may be made wider than the width W3 of the contact region CNT, which facilitates the disconnection of the first electrode 261 in the common contact hole CTS. More specifically, the common contact hole CTS may be formed to be inclined from the contact region CNT to the bottom portion FL in an inverse tapered shape, or may be formed in any shape such that the lower surface of the drain electrode 214 of the TFT210 may be exposed in the contact region CNT. For example, as shown in fig. 5, the common contact hole CTS may have an undercut shape (undercut shape) in which the interlayer dielectric 230 disposed under the drain electrode 214 of the TFT210 is recessed to expose a lower surface of the drain electrode 214 of the TFT 210. The undercut provides a space for accommodating some of the material forming the first electrode 261, thereby breaking the first electrode 261 in the common contact hole CTS.

The first electrode 261 may be formed through a sputtering process, an e-BEAM deposition process, an evaporation process, or the like. Even when the first electrode 261 is formed through a sputtering process having a good step coverage characteristic, the common contact hole CTS may be formed to have an inverse tapered shape between the contact region CNT and the bottom portion FL, or may be formed in any shape such that the lower surface of the drain electrode 214 of the TFT210 may be exposed, and thus the first electrode 261 may be formed to be disconnected in the common contact hole CTS. Step coverage means that even in a portion where the step height is formed, layers deposited by a deposition process are continuously connected without being disconnected. However, as shown in fig. 6, even the process of forming the first electrode 261 with good step coverage will cause the first electrode 261 to be disconnected between the contact region CNT and the bottom portion FL due to the reverse taper or undercut.

Further, since the common contact hole CTS is formed in an inverse tapered shape between the contact region CNT and the bottom FL or may be formed in any shape such that the lower surface of the drain electrode 214 of the TFT210 may be exposed, the dummy electrode 261a may be formed on the bottom FL of the common contact hole CTS so as to be disconnected from the first electrode 261. As shown in fig. 5, the dummy electrode 261a may contact a first portion of a side surface of the interlayer dielectric 230 in the contact hole CTS. A second portion of the side surface of the interlayer dielectric 230 is not in contact with the dummy electrode 261 a. The first electrode 261 and the dummy electrode 261a may be formed through the same process and thus may be formed of the same material. The dummy electrode 261a may thus be a part of the material forming the first electrode 261, but the dummy electrode 261a is disconnected from the first electrode 261. For example, the first electrode 261 and the dummy electrode 261a may be formed of a transparent metal material or an opaque metal material. The transparent conductive material may be a transparent conductive material (or a Transparent Conductive Oxide (TCO)) such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. The opaque conductive material may be a laminated structure of Al, Ag, Mo, and Ti (Mo/Ti), a laminated structure of Cu, Al, and Ti (ITO/Al/ITO), an APC alloy, or a laminated structure of an APC alloy and ITO (ITO/APC/ITO). The APC alloy may be an alloy of Ag, palladium (Pd), and Cu.

The bank 270 may be formed to fill the common contact hole CTS. The bank 270 may contact a second portion of the side surface of the interlayer dielectric 250 in the contact hole CTS. That is, the bank 270 may be in contact with a side surface of the interlayer dielectric 250 between an upper surface of the dummy electrode 261a and a lower surface of the drain electrode 214. In addition, the bank 270 may be formed on the first planarization layer 250 and may cover an edge of the first electrode 261. The bank 270 thus divides the plurality of light emitting areas EA. That is, the bank 270 may define the light emitting area EA.

Each of the light emitting regions EA may indicate a region in which the first electrode 261 corresponding to an anode, the organic light emitting layer 262, and the second electrode 263 corresponding to a cathode are sequentially stacked and holes from the first electrode 261 and electrons from the second electrode 263 are recombined in the organic light emitting layer to emit light. In this case, the region where the bank 270 is disposed does not emit light, and thus may be defined as a non-light emitting region.

The bank 270 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, or the like.

An organic emission layer 262 may be formed on the first electrode 261 and the bank 270. The organic light emitting layer 262 may be a common layer commonly formed in each of the pixels P, and may be a white light emitting layer emitting white light. In this case, the organic light emitting layer 262 may be formed as a serial structure of two or more stacked bodies. Each stack may include a hole transport layer, at least one light emitting layer, and an electron transport layer.

Further, a charge generation layer may be formed between the stacked bodies. The charge generation layer may include an n-type charge generation layer disposed adjacent to the lower stacked body and a p-type charge generation layer formed on the n-type charge generation layer and disposed adjacent to the upper stacked body. The n-type charge generation layer may inject electrons into the lower stack, and the p-type charge generation layer may inject holes into the upper stack. The n-type charge generation layer may be formed of an organic layer doped with an alkali metal such as lithium (Li), sodium (Na), potassium (K), or cesium (Cs), or an alkaline earth metal such as magnesium (Mg), strontium (Sr), barium (Ba), or radium (Ra). The p-type charge generation layer may be an organic layer formed by doping an organic material with a dopant having a hole transporting ability.

In fig. 5, it is illustrated that the organic light emitting layer 262 is a common layer commonly formed in each of the pixels P and is a white light emitting layer emitting white light, but the embodiment is not limited thereto. In other embodiments, the respective organic light emitting layers 262 may be separately disposed in each of the pixels P, and in this case, the pixels P may be divided into red pixels including red light emitting layers emitting red light, green pixels including green light emitting layers emitting green light, and blue pixels including blue light emitting layers emitting blue light.

The second electrode 263 may be formed on the organic light emitting layer 262. The second electrode 263 may be a common layer commonly formed in each of the pixels P. The second electrode 263 may be formed of a transparent conductive material (or TCO) such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO) or a semi-transmissive conductive material such as Mg, Ag, or an alloy of Mg and Ag, which is capable of transmitting light. In the case where the second electrode 263 is formed of a semi-transmissive conductive material, light emitting efficiency may be improved by the micro-cavity. A capping layer may be formed on the second electrode 263.

An encapsulation layer 280 may be formed on the second electrode 263. The encapsulation layer 280 prevents oxygen or water from penetrating into the organic light emitting layer 262 and the second electrode 263. The encapsulation layer 280 may include at least one inorganic layer. The inorganic layer may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, or the like. In addition, the encapsulation layer 280 may further include at least one organic layer for preventing particles from penetrating into the organic light emitting layer 262 and the second electrode 263 through the encapsulation layer 280.

A plurality of

color filters

301 and 302 and a black matrix 310 may be disposed on the second substrate 112 between the second substrate 112 and the encapsulation layer 280. The color filters 301 and 302 may be respectively disposed corresponding to the pixels P. The black matrix 310 may be disposed between and partially overlap the

adjacent color filters

301 and 302, and may be disposed corresponding to the bank 270.

The color filters 301 and 302 on the second substrate 112 may be adhered to the encapsulation layer 280 on the first substrate 111 by an adhesive layer 290. Thus, the first substrate 111 and the structures formed thereon may be bonded to the second substrate 112 and the structures formed thereon. The adhesive layer 290 may be a transparent adhesive film, a transparent adhesive resin, or the like. The second substrate 112 may be a plastic film, a glass substrate, an encapsulation film (protective film), or the like.

As described above, in the embodiment of the present disclosure, since the common contact hole CTS is formed to have an inverse tapered shape between the contact region CNT and the bottom portion FL, or may be formed in any shape such that the lower surface of the drain electrode 214 of the TFT210 may be exposed, the first electrode 261 may be opened at the common contact hole CTS. As a result, in the embodiment of the present disclosure, the first electrodes 261 of the organic light emitting devices 260 of each of the adjacent pixels P may be electrically connected to the respective drain electrodes 214 of the respective TFTs 210 through the common contact holes CTS without being shorted with each other. Accordingly, in the embodiment of the present disclosure, the N pixels may share the common contact hole CTS for connecting the first electrode of the organic light emitting device to the drain electrode of the TFT. Accordingly, in the embodiment of the present disclosure, the reduction of the light emitting region is prevented by the common contact hole CTS, thereby preventing the life span of the organic light emitting layer from being shortened due to the reduction of the light emitting region EA.

Fig. 7 is a flowchart illustrating a method of manufacturing an organic light emitting display device according to an embodiment of the present disclosure. Fig. 8A to 8F are sectional views taken along line I-I' of fig. 4 for describing a method of manufacturing an organic light emitting display device according to an embodiment of the present disclosure;

the sectional views shown in fig. 8A to 8F relate to a method of manufacturing the organic light emitting display device shown in fig. 5, and therefore, like reference numerals denote like elements. Hereinafter, a method of manufacturing an organic light emitting display device according to an embodiment of the present disclosure will be described in detail with reference to fig. 7 and 8A to 8F.

In S101, referring to fig. 8A, the active layer 211, the gate electrode 212, the source electrode 213, and the drain metal layer 214a included in each of the plurality of TFTs 210 may be formed, and the passivation layer 240 and the first planarization layer 250 covering the TFTs 210 may be formed.

In detail, before the TFT210 is formed, a buffer layer may be formed on the first substrate 111 for protecting the TFT210 from water permeated through the substrate 111. The buffer layer may include a plurality of inorganic layers alternately stacked for protecting the TFT210 and the organic light emitting device 260 from water permeated through the first substrate 111 that is easily permeated by water. For example, the buffer layer may be formed of a multi-layer in which one or more inorganic layers of silicon oxide (SiOx), silicon nitride (SiNx), and/or SiON are alternately stacked. The buffer layer may be formed by using a Chemical Vapor Deposition (CVD) process.

Subsequently, the active layer 211 of each of the TFTs 210 may be formed on the buffer layer. In detail, the active metal layer may be formed on the entire buffer layer by using a sputtering process, a metal organic chemical vapor phase (MOCVD) process, or the like. Subsequently, the active layer 211 may be formed by patterning the active metal layer through a mask process using a photoresist pattern. The active layer 211 may be formed of a silicon-based semiconductor material, an oxide-based semiconductor material, or the like.

Subsequently, a gate insulating layer 220 may be formed on the active layer 211. The gate insulating layer 220 may be formed of an inorganic layer such as silicon oxide (SiOx), silicon nitride (SiNx), or a multi-layer thereof.

Subsequently, the gate electrode 212 of each of the TFTs 210 may be formed on the gate insulating layer 220. In detail, the first metal layer may be formed on the entire gate insulating layer 220 by using a sputtering process, an MOCVD process, or the like. Subsequently, the gate electrode 212 may be formed by patterning the first metal layer through a mask process using a photoresist pattern. The gate electrode 212 may be formed of a single layer or a plurality of layers including one of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

Subsequently, an interlayer dielectric 230 may be formed on the gate 212. The interlayer dielectric 230 may be formed of an inorganic layer such as SiOx, SiNx, or a multi-layer thereof.

Subsequently, a plurality of contact holes CT1, CT2 may be formed through the gate insulating layer 220 and the interlayer dielectric 230 to expose the active layer 211.

Subsequently, a source 213 and a drain metal layer 214a of each of the TFTs 210 may be formed on the interlayer dielectric 230. In detail, the second metal layer may be formed on the entire interlayer dielectric 230 and in the contact holes CT1, CT2 by using a sputtering process, an MOCVD process, or the like. Subsequently, the source and drain

metal layers

213 and 214a may be formed by patterning the second metal layer through a mask process using a photoresist pattern. The source electrode 213 may contact one side of the active layer 211 through a second contact hole CT2 passing through the gate insulating layer 220 and the interlayer dielectric 230. The drain metal layer 214a may contact the other side of the active layer 211 through a first contact hole CT1 passing through the gate insulating layer 220 and the interlayer dielectric 230. The source 213 and drain 214a metal layers may each be formed of a single layer or a plurality of layers including one of Mo, Cr, Ti, Ni, Nd, and Cu or an alloy thereof. In addition, as shown in fig. 8A, the drain metal layers 214a of the neighboring pixels P may be connected to each other.

Subsequently, a passivation layer 240 may be formed on the source 213 and drain metal layers 214a of each of the TFTs 210 and on the interlayer dielectric 230. The passivation layer 240 may be formed of an inorganic layer such as SiOx, SiNx, or a multi-layer thereof. The passivation layer 240 may be formed by using a CVD process.

Subsequently, a first planarization layer 250 for planarizing a step height caused by the TFT210 may be formed on the passivation layer 240. The first planarization layer 250 may be formed of an organic layer of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

At S102, referring to fig. 8B, a first photoresist pattern PR1 may be formed on the first planarization layer 250. The first photoresist pattern PR1 may be formed in an area except for an area where the common contact hole CTS is to be formed.

At S103, referring to fig. 8C, the common contact hole CTS may be formed by simultaneously etching the first planarization layer 250, the passivation layer 240, the drain metal layer 214a, and the interlayer dielectric 230, which are not covered by the first photoresist pattern PR1, and then the first photoresist pattern PR1 may be removed.

The common contact hole CTS may be a hole passing through the first planarization layer 250, the passivation layer 240, and the drain metal layer 214a and extending at least partially into the interlayer dielectric 230. The common contact hole CTS thus forms a depression or recess of the interlayer dielectric 230. Since the common contact hole CTS is formed by simultaneously etching the first planarization layer 250, the passivation layer 240, the drain metal layer 214a, and the interlayer dielectric 230, the pattern of the drain electrode 214 may be completed as the side surface of the drain electrode 214 of the TFT210 is exposed by the common contact hole CTS.

The common contact hole CTS may include an entrance ENT, a bottom FL, and a contact region CNT between the entrance ENT and the bottom FL formed by exposing a side surface of the drain electrode 214 of the TFT 210. In order to connect the first electrode 261 to the drain electrode 214 of the TFT210, the common contact hole CTS may be formed to be inclined in a tapered shape from the entrance ENT to the contact region CNT, and in particular, the width W1 of the entrance ENT may be wider than the width W3 of the contact region CNT. Further, the first electrode 261 of the pixel P is disconnected in the common contact hole CTS, otherwise the first electrode 261 will be connected to the first electrode of another pixel P adjacent to the pixel P. Therefore, in order to make the first electrode 261 be interrupted at the common contact hole CTS, the width W2 of the bottom FL of the common contact hole CTS may be wider than the width W3 of the contact region CNT. The common contact hole CTS may be formed to be inclined from the contact region CNT to the bottom FL in an inverse tapered shape, or may be formed in any shape such that the lower surface of the drain electrode 214 of the TFT210 may be exposed in the contact region CNT. For example, as shown in fig. 8C, the common contact hole CTS may have an undercut shape in which the interlayer dielectric 230 disposed under the drain electrode 214 of the TFT210 is recessed so as to expose the lower surface of the drain electrode 214 of the TFT 210.

The common contact hole CTS may be formed by using a dry etching process. First, the drain metal layer 214a may be exposed by etching the first planarization layer 250 and the passivation layer 240 with a first etching gas. In this case, the first etching gas may be a gas that etches the first planarization layer 250 and the passivation layer 240 but does not etch a metal layer such as the drain metal layer 214 a. Subsequently, the drain electrode 214 may be formed by etching the exposed drain metal layer 214a using a second etching gas. In this case, the second etching gas may be a gas that etches a metal layer such as the drain metal layer 214a but does not etch the interlayer dielectric 230. Subsequently, the interlayer dielectric 230 may be etched by using a third etching gasTo form undercuts and recessed or recessed portions to complete the common contact hole CTS. The third etching gas may be oxygen (O)₂) Or oxygen (O)₂) And CF₄For forming the common contact hole CTS into a shape such that the lower surface of the drain electrode 214 of the TFT210 may be exposed.

At S104, referring to fig. 8D, a first electrode 261 may be formed on the first planarization layer 250 and on the inclined side surface of the common contact hole CTS.

In detail, the third metal layer may be formed on the entire first planarization layer 250 by using a sputtering process, an MOCVD process, an e-BEAM deposition process, an evaporation process, or the like. Subsequently, the first electrode 261 may be formed by patterning the third metal layer through a mask process using a photoresist pattern.

The first electrode 261 may be connected to a side surface of the drain electrode 214 of the TFT210 exposed through the common contact hole CTS. Since the first electrode 261 is connected only to the side surface of the drain electrode 214 of the TFT210, the contact resistance of the first electrode 261 and the drain electrode 214 may be high. Therefore, in order to reduce the contact resistance of the first electrode 261 and the drain electrode 214, the thickness of the first electrode 261 and the thickness of the drain electrode 214 may be selected to be thick enough to provide a suitable contact resistance. The thickness of the first electrode 261 and the thickness of the drain electrode 214 may be selected based on the contact resistance of the first electrode 261 and the drain electrode 214, which may be appropriately determined through previous experiments.

Even when the first electrode 261 is formed through the sputtering process having the good step coverage characteristic, the common contact hole CTS may be formed to have an inverse tapered shape between the contact region CNT and the bottom portion FL, or may be formed in any shape such that the lower surface of the drain electrode 214 of the TFT210 may be exposed, and thus the first electrode 261 may be broken at the common contact hole CTS. Step coverage means that even in a portion where the step height is formed, layers deposited by a deposition process are continuously connected without being disconnected.

In addition, the dummy electrode 261a may be formed on the bottom FL of the common contact hole CTS so as to be disconnected from the first electrode 261. The first electrode 261 and the dummy electrode 261a may be formed through the same process and thus may be formed of the same material. That is, the dummy electrode 261a may be a portion of the third metal layer formed on the bottom FL of the common contact hole CTS, but disconnected from the first electrode 261 due to an inverse taper or undercut. For example, the first electrode 261 and the dummy electrode 261a may be formed of a transparent metal material or an opaque metal material. The transparent conductive material may be a transparent conductive material (or a Transparent Conductive Oxide (TCO)) such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. The opaque conductive material may be a laminated structure of Al, Ag, Mo, and Ti (Mo/Ti), a laminated structure of Cu, Al, and Ti (ITO/Al/ITO), an APC alloy, or a laminated structure of an APC alloy and ITO (ITO/APC/ITO). The APC alloy may be an alloy of Ag, palladium (Pd), and Cu.

At S105, referring to fig. 8E, a bank 270 may be formed to fill the common contact hole CTS.

The bank 270 may fill the common contact hole CTS so that the organic light emitting layer 262 is uniformly deposited. In addition, a bank 270 may be formed on the first planarization layer 250 to cover an edge of the first electrode 261 and divide the plurality of light emitting areas EA. That is, the bank 270 may define the light emitting area EA.

At S106, referring to fig. 8F, an organic light emitting layer 262 and a second electrode 263 may be formed on the first electrode 261 and the bank 270.

In detail, the organic light emitting layer 262 may be formed on the first electrode 261 and the bank 270 through a deposition process or a development process. The organic light emitting layer 262 may be a common layer commonly formed in each of the pixels P. In this case, the organic light emitting layer 262 may be a white light emitting layer emitting white light.

If the organic light emitting layer 262 is a white light emitting layer, the organic light emitting layer 262 may be formed as a tandem structure of two or more stacked bodies. Each of the stacks may include a hole transport layer, at least one light emitting layer, and an electron transport layer.

Subsequently, a second electrode 263 may be formed on the organic light emitting layer 262. The second electrode 263 may be a common layer commonly formed in each of the pixels P. The second electrode 263 may be formed of a transparent conductive material (or TCO) such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO) or a semi-transmissive conductive material such as Mg, Ag, or an alloy of Mg and Ag, which is capable of transmitting light. In the case where the second electrode 263 is formed of a semi-transmissive conductive material, light emitting efficiency may be improved by the micro-cavity. The second electrode 263 may be formed through a Physical Vapor Deposition (PVD) process such as a sputtering process. A capping layer may be formed on the second electrode 263.

Subsequently, an encapsulation layer 280 may be formed on the second electrode 263. The encapsulation layer 280 prevents oxygen or water from penetrating into the organic light emitting layer 262 and the second electrode 263. The encapsulation layer 280 may include at least one inorganic layer. The inorganic layer may be formed of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, or the like.

In addition, the encapsulation layer 280 may further include at least one organic layer. The organic layer may be formed to have a sufficient thickness for preventing particles from penetrating into the organic light emitting layer 262 and the second electrode 263 via the encapsulation layer 280.

Subsequently, the second substrate 112 in which the plurality of

color filters

301 and 302 and the black matrix 310 are disposed may be bonded to the first substrate 111. The color filters 301 and 302 on the second substrate 112 may be adhered to the encapsulation layer 280 on the first substrate 111 by an adhesive layer 290. The adhesive layer 290 may be a transparent adhesive film, a transparent adhesive resin, or the like.

As described above, according to the embodiment of the present disclosure, the common contact hole CTS may be formed by simultaneously etching the first planarization layer 250, the passivation layer 240, the drain metal layer 214a, and the interlayer dielectric 230. Accordingly, in one embodiment of the present disclosure, a side surface of the drain electrode 214 of the TFT210 may be exposed by the common contact hole CTS. As a result, in the embodiment of the present disclosure, the size of the drain electrode 214 of the TFT210 is prevented from being smaller than that of the contact hole, thereby preventing the first electrode 261 from being disconnected on the side surface of the source or drain electrode due to the step height between the bottom of the contact hole and the drain electrode 214. Therefore, in the embodiments of the present disclosure, the on defect in which the pixel does not emit light is prevented from occurring.

Fig. 9 is a plan view illustrating another example of pixels in the display area in detail.

In fig. 9, for convenience of description, only the pixel P, the first electrode AND, the light emitting region EA, the auxiliary contact hole CT3, AND the common contact hole CTs are illustrated.

Referring to fig. 9, a plurality of pixels P may be provided, and each of the pixels P may include at least one TFT and an organic light emitting device.

The TFT may include an active layer, a gate electrode overlapping the active layer, a source electrode connected to one side of the active layer, and a drain electrode connected to the other side of the active layer.

The organic light emitting device may include a first electrode AND corresponding to the anode, an organic light emitting layer, AND a second electrode corresponding to the cathode. The light emitting region EA may denote a region where the first electrode AND, the organic light emitting layer, AND the second electrode are sequentially stacked AND holes from the first electrode AND electrons from the second electrode are recombined in the organic light emitting layer to emit light. The light emitting areas EA of the neighboring pixels P may be separated by a bank, and thus the bank may correspond to a non-light emitting area that does not emit light.

The auxiliary contact hole CT3 may be a contact hole formed to connect the drain electrode of the TFT to an auxiliary electrode. Accordingly, the drain electrode of the TFT may be connected to the auxiliary electrode through the auxiliary contact hole CT 3.

The common contact hole CTS may be a hole exposing the auxiliary electrode connected to the corresponding drain electrode of each of the N (where N is an integer equal to or greater than 2) pixels P. That is, the auxiliary electrodes in the N pixels P may be exposed through the common contact hole CTS. The first electrode of the organic light emitting device of each of the N pixels P may be connected to the auxiliary electrode through the common contact hole CTS. That is, the first electrode of the organic light emitting device of each of the N pixels P may be electrically connected to the drain electrode of the TFT through the auxiliary electrode.

In fig. 9, N pixels P may share the common contact hole CTS. In fig. 9, N is exemplified as 4(N is 4), but the present embodiment is not limited thereto. For example, as shown in fig. 13B and 14B, N may be 2(N ═ 2), and as shown in fig. 15B, N may be 3(N ═ 3). As shown in fig. 13B, even when N is 2, pixels P adjacent to each other in a first direction (e.g., Y-axis direction) may share the common contact hole CTS, and as shown in fig. 14B, pixels P adjacent to each other in a second direction (e.g., X-axis direction) crossing the first direction (e.g., Y-axis direction) may share the common contact hole CTS. In addition, as shown in fig. 15B, when N is 3, the pixels P adjacent to each other in the triangular shape may share the common contact hole CTS.

In fig. 9, the auxiliary electrode is described as being connected to the drain electrode of the TFT through the auxiliary contact hole CT3 for convenience of description, but the embodiment is not limited thereto. In other embodiments, the auxiliary electrode may be connected to the source electrode of the TFT through an auxiliary contact hole CT 3.

Fig. 10 is a sectional view illustrating another example taken along line III-III' of fig. 9.

The sectional view shown in fig. 10 is substantially the same as that described above with reference to fig. 5, except that the auxiliary electrode 264 and the second planarization layer 251 are additionally formed and the auxiliary electrode 264 is exposed through the common contact hole CTS instead of the source electrode 213 or the drain electrode 214 of the TFT 210. Therefore, detailed descriptions of the first and

second substrates

111 and 112, the active layer 211, the gate electrode 212, the source and drain

electrodes

213 and 214 of the TFT210, the gate insulating layer 220, the interlayer dielectric 230, the passivation layer 240, the first planarization layer 250, the organic light emitting layer 262, the second electrode 263, the encapsulation layer 280, the adhesive layer 290, the

color filters

301 and 302, and the black matrix 310 illustrated in fig. 10 are omitted.

Referring to fig. 10, an auxiliary contact hole CT3 may be formed through the passivation layer 240 and the first planarization layer 250 to expose the drain electrode 214 of the TFT 210. The auxiliary electrode 264 may be formed on the first planarization layer 250 and in the auxiliary contact hole CT3, and may be connected to the drain electrode 214 of the TFT210 through the auxiliary contact hole CT 3.

The auxiliary electrode 264 may be formed of a transparent metal material or an opaque metal material. The transparent conductive material may be a transparent conductive material (or a Transparent Conductive Oxide (TCO)) such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. The opaque conductive material may be a laminated structure of Al, Ag, Mo, and Ti (Mo/Ti), a laminated structure of Cu, Al, and Ti (ITO/Al/ITO), an APC alloy, or a laminated structure of an APC alloy and ITO (ITO/APC/ITO). The APC alloy may be an alloy of Ag, palladium (Pd), and Cu.

The second planarization layer 251 may be formed on the auxiliary electrode 264 and in the auxiliary contact hole CT 3. The second planarization layer 251 may be formed to fill the auxiliary contact hole CT 3. The second planarization layer 251 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

The first electrode 261 may be formed on the second planarization layer 251. The first electrode 261 may pass through the second planarization layer 251 and may be connected to a side surface of the auxiliary electrode 264 through a common contact hole CTS. The common contact hole CTS may be a hole passing through the second planarization layer 251 and extending at least partially into the first planarization layer 250. Accordingly, a portion of the first planarization layer 250 is recessed or indented in the common contact hole CTS. The common contact hole CTS may be formed by simultaneously etching the second planarization layer 251, the auxiliary electrode 264, and the first planarization layer 250. Accordingly, only the side surface of the auxiliary electrode 264 may be exposed through the common contact hole CTS, and thus, the first electrode 261 may be connected to the side surface of the auxiliary electrode 264 through the common contact hole CTS. The process of forming the common contact hole CTS will be described in more detail in operation (S205) of fig. 11.

The first electrode 261 may be connected to only a side surface of the auxiliary electrode 264, thereby increasing contact resistance of the first electrode 261 and the auxiliary electrode 264. Therefore, in order to reduce the contact resistance of the first electrode 261 and the auxiliary electrode 264, the thickness of the first electrode 261 and the thickness of the auxiliary electrode 264 may be increased to provide a suitable contact resistance. The thickness of the first electrode 261 and the thickness of the auxiliary electrode 264 may be selected based on the contact resistance of the first electrode 261 and the auxiliary electrode 264, which may be appropriately determined through previous experiments.

Like the embodiment shown in fig. 6, the common contact hole CTS may include an entrance ENT, a bottom FL, and a contact region CNT between the entrance ENT and the bottom FL, through which the first electrode 261 and the auxiliary electrode 264 are connected to each other. In order to connect the first electrode 261 to the auxiliary electrode 264, the common contact hole CTS may be formed to have an inclined sidewall in a tapered shape from the entrance ENT to the contact region CNT, and in particular, the width of the entrance ENT may be wider than the width W3 of the contact region CNT. In addition, the first electrode 261 of the pixel P is disconnected from the first electrode of another pixel P adjacent to the pixel P in the common contact hole CTS. Therefore, in order to make the first electrode 261 be interrupted at the common contact hole CTS, the width W2 of the bottom FL of the common contact hole CTS may be made wider than the width W3 of the contact region CNT, and more specifically, the common contact hole CTS may be formed to be inclined from the contact region CNT to the bottom FL in a reverse tapered shape, or may be formed in any shape such that the lower surface of the auxiliary electrode 264 may be exposed in the contact region CNT. For example, as in fig. 10, the common contact hole CTS may have an undercut shape in which the first planarization layer 250 disposed under the auxiliary electrode 264 is recessed so that the lower surface of the auxiliary electrode 264 is exposed.

The first electrode 261 may be formed through a sputtering process, an MOCVD process, an e-BEAM deposition process, an evaporation process, or the like. Even when the first electrode 261 is formed through the sputtering process having the good step coverage characteristic, the common contact hole CTS may be formed to have an inverse tapered shape between the contact region CNT and the bottom portion FL, or may be formed in any shape such that the lower surface of the auxiliary electrode 264 may be exposed, and thus the first electrode 261 may be disconnected in the common contact hole CTS.

In addition, the dummy electrode 261a may be formed on the bottom FL of the common contact hole CTS so as to be disconnected from the first electrode 261. The first electrode 261 and the dummy electrode 261a may be formed through the same process and thus may be formed of the same material. For example, the first electrode 261 and the dummy electrode 261a may be formed of a transparent metal material or an opaque metal material. The transparent conductive material may be a transparent conductive material (or a Transparent Conductive Oxide (TCO)) such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. The opaque conductive material may be a laminated structure of Al, Ag, Mo, and Ti (Mo/Ti), a laminated structure of Cu, Al, and Ti (ITO/Al/ITO), an APC alloy, or a laminated structure of an APC alloy and ITO (ITO/APC/ITO). The APC alloy may be an alloy of Ag, palladium (Pd), and Cu.

The bank 270 may be formed to fill the common contact hole CTS. In addition, a bank 270 may be formed on the second planarization layer 251 to cover an edge of the first electrode 261 and divide the plurality of light emitting areas EA. That is, the bank 270 may define the light emitting area EA.

As described above, in the embodiment of the present disclosure, since the common contact hole CTS is formed in an inverse tapered shape between the contact region CNT and the bottom portion FL, or may be any shape such that the lower surface of the auxiliary electrode 264 may be exposed, the auxiliary electrode 264 may be opened at the common contact hole CTS. As a result, in the embodiment of the present disclosure, the first electrode 261 of the organic light emitting device 260 of each of the adjacent pixels P may be electrically connected to the auxiliary electrode 264 through the common contact hole CTS. The first electrode 261 is thus connected to the drain electrode 214 of the TFT210 via the auxiliary electrode 264. Accordingly, in one embodiment of the present disclosure, the N pixels may share a common contact hole CTS for connecting the first electrode of the organic light emitting device to the auxiliary electrode 264 and thus to the drain electrode of the TFT. Accordingly, in the embodiment of the present disclosure, the reduction of the light emitting region is prevented by the common contact hole CTS, thereby preventing the reduction of the life span of the organic light emitting layer due to the reduction of the light emitting region EA.

Fig. 11 is a flowchart illustrating a method of manufacturing an organic light emitting display device according to an embodiment of the present disclosure. Fig. 12A to 12H are sectional views taken along line III-III of fig. 9 for describing a method of manufacturing an organic light emitting display device according to an embodiment of the present disclosure.

The sectional views shown in fig. 12A to 12H relate to a method of manufacturing the organic light emitting display device shown in fig. 10, and therefore, like reference numerals denote like elements. Hereinafter, a method of manufacturing an organic light emitting display device according to an embodiment of the present disclosure will be described in detail with reference to fig. 11 and 12A to 12H.

At S201, referring to fig. 12A, the active layer 211, the gate electrode 212, the source electrode 213, and the drain electrode 214 included in each of the plurality of TFTs 210 may be formed, and the passivation layer 240 and the first planarization layer 250 covering the TFTs 210 may be formed.

The method for forming the active layer 211 and the gate electrode 212, the gate insulating layer 220, and the interlayer dielectric 230 of each of the TFTs 210 is substantially the same as the operation (S101) of fig. 7 described above with reference to fig. 8A.

A source 213 and a drain 214 of each of the TFTs 210 may be formed on the interlayer dielectric 230. In detail, the second metal layer may be formed on the entire interlayer dielectric 230 by using a sputtering process, an MOCVD process, or the like. Subsequently, the source electrode 213 and the drain electrode 214 may be formed by patterning the second metal layer through a mask process using a photoresist pattern. The source electrode 213 may contact one side of the active layer 211 through a second contact hole passing through the gate insulating layer 220 and the interlayer dielectric 230. The drain electrode 214 may contact the other side of the active layer 211 through a first contact hole passing through the gate insulating layer 220 and the interlayer dielectric 230. The source electrode 213 and the drain electrode 214 may each be formed of a single layer or a plurality of layers including one of Mo, Cr, Ti, Ni, Nd, and Cu or an alloy thereof.

Subsequently, a passivation layer 240 may be formed on the source and drain

electrodes

213 and 214 of each of the TFTs 210 and on the interlayer dielectric 230. The passivation layer 240 may be formed of an inorganic layer such as SiOx, SiNx, or a multi-layer thereof. The passivation layer 240 may be formed by using a CVD process.

Subsequently, a first planarization layer 250 for planarizing a step height caused by the TFT210 may be formed on the passivation layer 240. The first planarization layer 250 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

At S202, referring to fig. 12B, a second photoresist pattern PR2 may be formed on the first planarization layer 250. The second photoresist pattern PR2 may be formed in an area except for an area where the auxiliary contact hole CT3 is to be formed.

At S203, referring to fig. 12C, an auxiliary contact hole CT3 exposing the drain electrode 214 of each of the TFTs 210 may be formed by etching the first planarization layer 250 and the passivation layer 240, which are not covered by the second photoresist pattern PR2, and then the second photoresist pattern PR2 may be removed.

At S204, referring to fig. 12D, an auxiliary metal layer 264' may be formed on the first planarization layer 250 and in the auxiliary contact hole CT 3. The auxiliary metal layer 264' may be connected to the exposed drain electrode 214 of each of the TFTs 210 in the auxiliary contact hole CT 3.

The auxiliary metal layer 264' may be formed of a transparent metal material or an opaque metal material. The transparent conductive material may be a transparent conductive material (or a Transparent Conductive Oxide (TCO)) such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. The opaque conductive material may be a laminated structure of Al, Ag, Mo, and Ti (Mo/Ti), a laminated structure of Cu, Al, and Ti (ITO/Al/ITO), an APC alloy, or a laminated structure of an APC alloy and ITO (ITO/APC/ITO). The APC alloy may be an alloy of Ag, palladium (Pd), and Cu.

Subsequently, the second planarization layer 251 may be formed on the auxiliary metal layer 264'. The second planarization layer 251 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

Subsequently, a third photoresist pattern PR3 may be formed on the second planarization layer 251. The third photoresist pattern PR3 may be formed in an area except for an area where the common contact hole CTS is to be formed.

At S205, referring to fig. 12E, a common contact hole CTS may be formed by simultaneously etching the second planarization layer 251, the auxiliary metal layer 264', and the first planarization layer 250, which are not covered by the third photoresist pattern PR3, and then, the third photoresist pattern PR3 may be removed.

The common contact hole CTS may be a hole passing through the second planarization layer 251 and the auxiliary metal layer 264' and extending at least partially into the first planarization layer 250. The common contact hole CTS thus forms a depression or recess portion of the first planarization layer 250. Since the common contact hole CTS is formed by simultaneously etching the second planarization layer 251, the auxiliary metal layer 264', and the first planarization layer 250, the pattern of the auxiliary electrode 264 may be finished as the side surface of the auxiliary electrode 264 is exposed by the common contact hole CTS.

The common contact hole CTS may include an entrance ENT, a bottom FL, and a contact region CNT formed between the entrance ENT and the bottom FL by exposing a side surface of the auxiliary electrode 264. In order to connect the first electrode 261 to the auxiliary electrode 264, the common contact hole CTS may be formed to be inclined in a tapered shape from the entrance ENT to the contact region CNT, and in particular, the width W1 of the entrance ENT may be wider than the width W3 of the contact region CNT. Further, the first electrode 261 of the pixel P is disconnected in the common contact hole CTS, otherwise the first electrode 261 will be connected to the first electrode of another pixel P adjacent to the pixel P. Therefore, in order to make the first electrode 261 be interrupted at the common contact hole CTS, the width W2 of the bottom FL of the common contact hole CTS may be wider than the width W3 of the contact region CNT, and in particular, the common contact hole CTS may be formed to be inclined in an inverted cone shape from the contact region CNT to the bottom FL, or may be formed in any shape such that the lower surface of the auxiliary electrode 264 may be exposed in the contact region CNT. For example, as shown in fig. 12E, the common contact hole CTS may have an undercut shape in which the first planarization layer 250 disposed under the auxiliary electrode 264 is recessed so as to expose the lower surface of the auxiliary electrode 264.

The common contact hole CTS may be formed by using a dry etching process. First, the auxiliary metal layer 264' may be exposed by etching the second planarization layer 251 with a first etching gas. In this case, the first etching gas may be a gas that etches the second planarization layer 251 but does not etch a metal layer such as the auxiliary metal layer 264'. Subsequently, the auxiliary electrode 264 may be formed by etching the exposed auxiliary metal layer 264' using a second etching gas. In this case, the second etching gas may be a gas that etches a metal layer such as the auxiliary metal layer 264' but does not etch the first planarization layer 250. Subsequently, the common contact hole CTS may be completed by etching the first planarization layer 250 using a third etching gas to form an undercut and a recessed or depressed portion.

At S206, referring to fig. 12F, a first electrode 261 may be formed on the second planarization layer 251 and on the inclined side surface of the common contact hole CTS.

In detail, the third metal layer may be formed on the entire second planarization layer 251 by using a sputtering process, an MOCVD process, an e-BEAM deposition process, an evaporation process, or the like. Subsequently, the first electrode 261 may be formed by patterning the third metal layer through a mask process using a photoresist pattern.

The first electrode 261 may be connected to a side surface of the auxiliary electrode 264 exposed through the common contact hole CTS. Since the first electrode 261 is connected to only the side surface of the auxiliary electrode 264, the contact resistance of the first electrode 261 and the auxiliary electrode 264 may be high. Therefore, in order to reduce the contact resistance of the first electrode 261 and the auxiliary electrode 264, the thickness of the first electrode 261 and the thickness of the auxiliary electrode 264 may be selected to be thick enough to provide a suitable contact resistance. The thickness of the first electrode 261 and the thickness of the auxiliary electrode 264 may be selected based on the contact resistance of the first electrode 261 and the auxiliary electrode 264, which may be appropriately determined through previous experiments.

Even when the first electrode 261 is formed through the sputtering process having the good step coverage characteristic, the common contact hole CTS may be formed to have an inverse tapered shape between the contact region CNT and the bottom portion FL, or may be formed in any shape such that the lower surface of the auxiliary electrode 264 may be exposed, and thus, the first electrode 261 may be broken at the common contact hole CTS. Step coverage means that even if layers deposited by a deposition process in a portion where a step height is formed are continuously connected without disconnection.

At S207, referring to fig. 12G, a bank 270 may be formed to fill the common contact hole CTS.

The bank 270 may fill the common contact hole CTS so that the organic light emitting layer 262 is uniformly deposited. In addition, a bank 270 may be formed on the second planarization layer 251 to cover an edge of the first electrode 261 and divide the plurality of light emitting areas EA. That is, the bank 270 may define the light emitting area EA.

At S208, referring to fig. 12H, an organic light emitting layer 262 and a second electrode 263 may be formed on the first electrode 261 and the bank 270.

The operation (S208) of forming the organic light emitting layer 262 and the second electrode 263 in fig. 11 is substantially the same as the operation (S106) of fig. 7 described above with reference to fig. 8F. Therefore, a detailed description of the operation (S208) of forming the organic light emitting layer 262 and the second electrode 263 in fig. 12 is omitted.

As described above, according to the embodiment of the present disclosure, the common contact hole CTS may be formed by simultaneously etching the second planarization layer 251, the auxiliary metal layer 264', and the first planarization layer 250. Accordingly, in one embodiment of the present disclosure, the side surface of the auxiliary electrode 264 may be exposed by the common contact hole CTS. As a result, in the embodiment of the present disclosure, the size of the drain electrode 214 of the TFT210 is prevented from being smaller than the size of the contact hole, thereby preventing the first electrode 261 from being disconnected on the side surfaces of the source and drain electrodes due to the step height between the bottom of the contact hole and the drain electrode 214. Therefore, in the embodiments of the present disclosure, the on defect in which the pixel does not emit light is prevented from occurring.

It is to be noted that although the above-described embodiments of the present disclosure are exemplified by an organic light emitting display apparatus having an organic light emitting device, the embodiments are merely for illustrative purposes, and the present disclosure is not limited thereto. For example, the present disclosure may also be implemented with a phosphor-light emitting display device having a phosphor-light emitting device.

By way of summary and review, according to embodiments of the present disclosure, the first electrode may be formed without interruption at the common contact hole. As a result, in the embodiment of the present disclosure, the first electrode of the organic light emitting device of each of the adjacent pixels may be electrically connected to the drain electrode of the TFT through the common contact hole. Accordingly, in the embodiment of the invention, the N pixels may share a common contact hole for connecting the first electrode of the organic light emitting device to the drain electrode of the corresponding TFT. Therefore, in the embodiments of the present disclosure, the reduction of the light emitting region is prevented by the common contact hole, thereby preventing the reduction of the life span of the organic light emitting layer due to the reduction of the light emitting region.

Further, according to an embodiment of the present disclosure, the common contact hole may be formed by simultaneously etching the first planarization layer, the passivation layer, the drain metal layer, and the interlayer dielectric. Accordingly, in the embodiment of the present disclosure, a side surface of the drain electrode of the TFT may be exposed by the common contact hole. As a result, in the embodiment of the present disclosure, the size of the drain electrode of the TFT is prevented from being formed smaller than the size of the contact hole, thereby preventing the first electrode from being disconnected on the side surface of the source or drain electrode due to the step height between the bottom surface of the contact hole and the drain electrode. Therefore, in the embodiments of the present disclosure, the on defect in which the pixel does not emit light is prevented from occurring.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the spirit or scope of the disclosure. Thus, it is intended that the present disclosure cover the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.

The various embodiments described above can be combined to provide further embodiments.

These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which the claims are entitled. Accordingly, the claims are not limited by the disclosure.

Cross Reference to Related Applications

This application claims the benefit of korean patent application No. 10-2016-.

Claims

1. A light emitting display device, comprising:

a plurality of pixels, each of the plurality of pixels comprising:

a transistor having a gate electrode, an active layer overlapping the gate electrode, a source electrode connected to one side of the active layer, and a drain electrode connected to the other side of the active layer; and

a light emitting device having a first electrode, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer; and

contact holes in which first electrodes of at least two pixels of the plurality of pixels are electrically connected to a side surface of the respective source electrodes or a side surface of the respective drain electrodes,

wherein the contact hole is undercut to expose a lower surface of the corresponding source electrode or the corresponding drain electrode.

2. The light emitting display device according to claim 1, wherein the contact hole includes an entrance having a first width, a bottom having a second width, and a contact region between the entrance and the bottom and having a third width, the first electrodes of the at least two pixels being electrically connected to the respective source electrode or the respective drain electrode in the contact region, the third width being smaller than the first width and the second width.

3. The light-emitting display device according to claim 2, further comprising:

a dummy electrode disposed on a bottom of the contact hole, the dummy electrode being disconnected from the first electrodes of the at least two pixels.

4. The light-emitting display device according to claim 3, wherein the dummy electrode and the first electrodes of the at least two pixels are formed of the same material.

5. The light-emitting display device according to claim 2, further comprising: a bank located in the bottom of the contact hole, the contact region, and the entrance.

6. The light-emitting display device according to claim 1, further comprising: a bank at least partially filling the contact hole.

7. The light-emitting display device according to claim 6, further comprising: a first planarization layer between the first electrode and at least one of the source electrode and the drain electrode.

8. The light-emitting display device according to claim 6, further comprising: a dummy electrode on the interlayer dielectric in the contact hole and under the first planarization layer.

9. The light-emitting display device according to claim 8, wherein the dummy electrode is in contact with a first portion of a side surface of the interlayer dielectric in the contact hole, and wherein the bank is in contact with a second portion of the side surface of the interlayer dielectric between the dummy electrode and the source electrode or the drain electrode in the contact hole.

10. The light-emitting display device according to claim 1, wherein the transistor further comprises: a gate insulating layer disposed between the active layer and the gate electrode; an interlayer dielectric disposed between the gate and the source and between the gate and the drain; and a first planarization layer disposed on the source electrode and the drain electrode, and

the contact hole extends through the first planarization layer and at least partially into the interlayer dielectric.

11. The light emitting display device according to claim 1, wherein the at least two pixels comprise: a first pixel; a second pixel adjacent to the first pixel along a first direction; a third pixel adjacent to the first pixel along a second direction transverse to the first direction; and a fourth pixel adjacent to the third pixel in the first direction and adjacent to the second pixel in the second direction.

12. The light emitting display device according to claim 1, wherein the at least two pixels comprise: a first pixel; a second pixel adjacent to the first pixel along a first direction; and a third pixel adjacent to one of the first pixel or the second pixel along a second direction transverse to the first direction.

13. A light emitting display device, comprising:

a plurality of pixels, each of the plurality of pixels comprising:

a transistor having a gate, a source region, and a drain region;

a source coupled to the source region;

a drain coupled to the drain region;

an auxiliary electrode coupled to one of the source or the drain; and a first electrode of a light emitting device coupled to the auxiliary electrode; and

contact holes in which first electrodes of at least two pixels of the plurality of pixels are electrically connected to side surfaces of the respective auxiliary electrodes,

wherein the contact hole includes an undercut exposing a lower surface of the corresponding auxiliary electrode.

14. The light emitting display device of claim 13, wherein each of the plurality of pixels further comprises:

a first planarization layer on the source and drain electrodes; and

an auxiliary contact hole extending through the first planarization layer and exposing a portion of one of the source electrode and the drain electrode, the auxiliary electrode being coupled to the exposed portion of the one of the source electrode and the drain electrode in the auxiliary contact hole.

15. The light emitting display device of claim 14, wherein each of the plurality of pixels further comprises:

a gate insulating layer between the source and drain regions and the gate;

an interlayer dielectric between the gate and the source and between the gate and the drain; and

a second planarization layer on and in the auxiliary contact hole,

wherein the contact hole extends through the second planarization layer and at least partially into the first planarization layer.

16. The light-emitting display device according to claim 13, further comprising: a bank at least partially filling the contact hole, the bank forming a non-light emitting region of the light emitting display device.

17. The light emitting display device according to claim 13, wherein the at least two pixels comprise: a first pixel; a second pixel adjacent to the first pixel along a first direction; a third pixel adjacent to the first pixel along a second direction transverse to the first direction; and a fourth pixel adjacent to the third pixel in the first direction and adjacent to the second pixel in the second direction.

18. The light emitting display device according to claim 13, wherein the at least two pixels comprise: a first pixel; a second pixel adjacent to the first pixel along a first direction; and a third pixel adjacent to one of the first pixel or the second pixel along a second direction transverse to the first direction.