CN1082277C - Circuit for frequency converting and modulating - Google Patents

Abstract

In the modulation circuit of the frequency conversion circuit, the filter with the impulse response of the rectangular pulse wave multiplied by the cosine wave of f ₃ /4 is formed as a band-pass type centered on f ₃ /4, and its transfer function is in the form of a series sum It means that the numerator is processed at the low-speed sampling frequency f ₂ and the denominator is processed at the high-speed sampling frequency f ₃ (=L×f ₂ , where L is an odd number), thereby achieving an adjustment-free structure and miniaturization of the circuit , In addition, by D/A converting the output of the molecule processed by the low-speed sampling frequency _f2 . The part of the denominator that is processed at the high-speed sampling frequency _f3 is completed by means of switched capacitors, which can reduce power consumption.

Description

Frequency conversion circuit and modulation circuit

The invention relates to frequency conversion circuits and modulation circuits in radio transmitting devices such as car phones and portable phones.

FIG. 16 is a configuration diagram of a conventional modulation device. In FIG. 16 , 1 is the digital baseband transmission signal input end, which is connected to the D/A converter 2 . 3 is a low-pass filter (hereinafter referred to as LPF), which is connected to the D/A converter 2 . 4 is an analog multiplier connected with LPF3. 5 is a clock transmitting circuit, which is connected with D/A converter 2. 6 is an oscillator, which is connected with the analog multiplier 4. 7 is an analog modulated wave output terminal, which is connected with the analog multiplier 4.

Next, the operation of the conventional example of the modulator configured as above will be described. If at first input the digital baseband transmission signal (such as D/A converted sound signal, modem (MODEM) signal, etc.) The sampled value signal becomes an analog baseband transmission signal after being interpolated by LPF3. Then the signal is multiplied by the 24MHz sine wave from the oscillator 6 in the analog multiplier 4, converted into a modulated wave with a center frequency of 24MHz, and then output from the analog modulated wave output terminal 7.

As mentioned above, even according to the conventional example, it can operate as a modulation circuit.

However, in the above-mentioned conventional modulation circuit, the sampling value output of the D/A converter needs to have a very steep interpolation LPF characteristic that suppresses the harmonic spectrum having a frequency that is an integer multiple of the sampling frequency 384KHz. In addition, at this time, there is a problem that it is difficult to miniaturize the circuit and make it uncontrollable (adjustment-free), because the DC bias voltage applied to the operational amplifier and the like in the circuit causes deterioration phenomena such as carrier leakage of the modulated wave.

In order to solve such conventional problems, the present invention aims to provide a frequency conversion circuit and a frequency modulation circuit capable of reducing the size and control of the circuit.

In order to achieve the above object, the present invention has noticed that the filter transfer function of the rectangular impulse response without delay and distortion can be given by the series and form that do not need multiplication, and the filter is formed by the transfer function of the series and form. While inserting the digital transmission signal, the high-order harmonic spectrum is extracted for frequency conversion, trying to make the circuit miniaturized and uncontrolled.

By interpolating the digital baseband transmission signal to increase the sampling frequency, the characteristic curve of the interpolation filter after D/A conversion can be changed slowly to make the circuit miniaturized. In addition, when interpolating the digital baseband transmission signal, one frequency in the high-order harmonic spectrum of the frequency that is an integer multiple of the sampling frequency is extracted for frequency conversion to obtain a band-pass signal and then D/A conversion is performed. Therefore, in future operational amplifiers, etc. The DC bias voltage added in will not make the modulated wave produce carrier leakage and other deterioration phenomena, and it can make the circuit uncontrolled. Furthermore, since the digital filter for the above-mentioned interpolation and frequency conversion is a filter transfer function that forms a rectangular impulse response without delay and distortion in the form of a series sum, it does not use a multiplier but a delayer and an adder-subtractor It can be realized, and because the numerator of this transfer function works with a low-speed clock signal, it is possible to greatly reduce the delay and adder and subtractor compared with the filter structure of the usual sum of products. Therefore, it is possible to try to make the circuit smaller and consume less power. In addition, since there is no need for multiplication and a small number of adders and subtracters, by only increasing the word length of the adder and subtractor (the number of adder and subtractors) by a few bits, it is possible to perform filtering using integer operations without calculation errors. device operation.

Fig. 1 is a block diagram showing the constitution of a frequency conversion circuit in Embodiment 1 of the present invention.

Fig. 2 is a timing chart showing the operation in Embodiment 1 of the present invention.

FIG. 3 is a waveform diagram showing an impulse response waveform of HB(Z) in Example 1 of the present invention.

4a and 4b are characteristic diagrams showing the relationship between frequency and gain of HB(Z) in Embodiment 1 of the present invention.

5A and 5B are characteristic diagrams showing the relationship between the frequency of H(Z) and the gain in Embodiment 1 of the present invention.

6A, 6B and 6C are block diagrams showing filter configurations for realizing transfer functions in Embodiment 1 of the present invention.

Fig. 7 is a block diagram showing the configuration of a frequency conversion circuit in Embodiment 2 of the present invention.

Fig. 8 is a timing chart showing the operation of Embodiment 2 of the present invention.

Fig. 9 is a block diagram showing a partial configuration of a modulation circuit in Embodiment 3 of the present invention.

Fig. 10 is a block diagram showing a partial configuration of a modulation circuit in Embodiment 4 of the present invention.

Fig. 11 is a block diagram showing the configuration of a modulation circuit in Embodiment 5 of the present invention.

Fig. 12 is a waveform diagram showing an impulse response waveform of HL(Z) in Example 5 of the present invention.

Fig. 13 is a characteristic diagram showing the relationship between frequency and gain of HL(Z) in Embodiment 5 of the present invention.

Fig. 14 is a characteristic diagram showing the relationship between the frequency of H(Z) and the gain in Embodiment 5 of the present invention.

Fig. 15 is a block diagram showing the configuration of a frequency conversion circuit in Embodiment 6 of the present invention.

Fig. 16 is a block diagram showing the structure of a conventional frequency conversion circuit.

(Example 1)

The frequency conversion circuit in Embodiment 1 of the present invention will be described below with reference to the block diagram of FIG. 1 and the timing diagram of FIG. 2 .

$\mathrm{HB}\left(Z\right)=\frac{1+Z^{-250}}{1+Z^{-2}}=1-Z^{-2}+Z^{-4}-\…+Z^{-248}\…\…\left(1\right)$ The frequency conversion circuit of the present embodiment 1 is after sampling frequency 768KHZ, center frequency 96KHZ, bandwidth is 12 digital band-pass transmission signals of 16KHZ to sampling frequency 96MHZ (=768KHZ * 125), center frequency 24MHZ after digital band-pass transmission signal , After D/A conversion, the analog transmission signal is obtained through a band-pass filter (BPF) with a center frequency of 24MHZ. The transfer function of the digital filter of present embodiment 1 is expressed as follows with (1) formula:

$\mathrm{HB}\left(Z\right)=\frac{1+Z^{-250}}{1+Z^{-2}}=1-Z^{-2}+Z^{-4}-\…+Z^{-248}\…\…\left(1\right)$

Here, Z ^-1 represents a delay of (96MHZ) ^-1 .

Fig. 3 is the impulse response waveform of HB (Z), and Fig. 4A and 4B represent its frequency-gain characteristic, Fig. 5 A and 5B represent the frequency-gain characteristic of H (Z), this filter is to have center frequency and be the band of 24MHZ Pass filter (BPF), because the high-order harmonic spectrum that is an integer multiple of 384KHZ away from (interval) the center frequency is equivalent to the notch frequency of H (Z), it can be seen that this spectrum is attenuated by more than 70dB. Fig. 6A, 6B and 6C represent the structure that is used to realize the transfer function represented by equation (1), here, Fig. 6A is only a kind of cascaded structure, Fig. 6B is the direct extension of transfer function HB (Z) of Fig. 6A type structure (configuration), and Fig. 6C corresponds to Fig. 6B, but the molecular part of the transfer function H(Z) working at a sampling frequency of 768KHZ is rearranged to be connected to its previous stage, while working at a sampling frequency of 768KHZ The denominator part of the 96MHZ transfer function H(Z) is rearranged to be connected to its subsequent stage. In this embodiment, the structure (configuration) of Fig. C is employed.

In FIG. 1, the input terminal 101 is a digital baseband transmission signal input terminal, which is connected with the delay register 102 and the clock generation circuit 120 (sometimes only marked with symbols below). 102 is a 12-bit delay register, connected to 101, 103, 120. 103 is a 12-bit delay register, which is connected with 102, 104, 120. 104 is a 13-bit adder connected to 101, 103, 105, and 107. 105 is a 13-bit delay register, connected with 104, 106, 120. 106 is a 13-bit delay register, which is connected with 105, 107, 120. 107 is a 14-bit adder connected to 104, 105, 106, 108, 110. 108 is a 14-bit delay register, which is connected with 107, 109, 110, 120. 109 is a 14-bit delay register, which is connected with 108, 110, 120. 110 is a 15-bit adder connected with 107, 108, 109, 111. 111 is 0 signal insertion switch SW, which is connected with 110, 112, 120. 112 is a 16-bit subtractor connected with 111, 113, 114. 113 is a 16-bit delay register, connected to 112, 114, 115, 120. 114 is a 17-bit subtractor connected with 113, 115, 116. 115 is a 17-bit delay register, connected with 114, 116, 120. 116 is an 18-bit subtractor connected with 115, 117, 118. 117 is an 18-bit register connected with 116, 118, 120. 118 is a 12-bit D/A converter connected to 116 , 117 , 119 , and 120 . 119 is an analog BFF connected with 118 and 121 . 120 is a clock generation circuit, which is connected to 102 , 103 , 105 , 106 , 108 , 109 , 111 , 113 , 115 , 117 , and 118 . 121 is an analog modulation output terminal, which is connected with 119.

Next, the work of this embodiment will be described. In Fig. 1, if at first input 1 sampling (signal) from digital baseband transmission signal input terminal at the 768KHZ clock signal leading edge that comes in clock generation circuit 120, then adder 104 adds the content of delay register 103 and input signal, The adder 107 adds the content of the delay register 106 to the output of the adder 104, the adder 110 adds the content of the delay register 109 to the output of the adder 107 and outputs the result of the addition to SW111, at the rear edge of the 768KHZ clock The output of delay register 108 is transmitted to delay register 109, the output of adder 107 is transmitted to delay register 108, the output of delay register 105 is transmitted to delay register 106, the output of adder 104 is transmitted to delay register 105, the output of delay register 102 The input signal transmitted to the delay register 103 and from the digital baseband transmit signal input terminal 101 is transmitted to the delay register 102 . In addition, SW111 outputs the output of the adder 110 within one clock time unit of the 96KHZ clock signal starting from the leading edge of the 768KHZ clock, and outputs 0 during the remaining 124 clock times, thereby performing 96MHZ sampling output. And then at the leading edge of the 96MHZ clock signal from the clock generation circuit 120, the subtractor 112 subtracts the content of the delay register 113 from the output of the SW111, the subtractor 114 subtracts the content of the delay register 115 from the output of the subtractor 112, and the subtractor 116 After subtracting the content of the delay register 117 from the output of the subtractor 114 and output the subtracted result to the D/A converter 118, the output of the subtractor 116 is transmitted to the delay register 117, the subtractor at the trailing edge of the 96MHZ clock signal The output of 114 is sent to delay register 115 , and the output of subtractor 112 is sent to delay register 113 . The output of the D/A converter 118 passes through the analog BPF 119 with a center frequency of 24MHZ to form an analog transmission signal.

In this way, according to Embodiment 1 of the present invention, by interpolating the digital baseband transmission signal to increase the sampling frequency, the characteristic (curve) of the analog BPF 119 changes slowly and the circuit can be miniaturized. In addition, during the insertion period of the digital band-pass transmission signal, a frequency in the high-order harmonic spectrum of the integer multiple frequency of the sampling frequency is extracted (extracted) for conversion, and a band-pass signal is obtained before D/A conversion. Therefore, in In the future, the DC bias voltage added to the operational amplifier will not cause deterioration such as carrier leakage of the modulated wave, and the circuit can be adjusted-free.

Furthermore, the digital filter for the above-mentioned interpolation and frequency conversion constitutes the filter transfer function of the rectangular impulse response without delay distortion through the form of the series sum, which can be realized with a delay device and an adder-subtractor without a multiplier, A digital filter without delay and distortion can be used for frequency conversion that does not require adjustment (no control). In addition, although the sampling frequency of this digital filter is 96MHZ, because half of its processing is at 768KHZ, so each stage of HB(Z) only needs 3 delayers and 2 subtractors, that is to say, all of them need 9 Only one delay device and six subtractors can be used to achieve small size and low power consumption. In addition, if the subtractor prepares a maximum word length of 18 bits, error-free operation can be realized.

(Example 2)

Next, the frequency conversion circuit in Embodiment 2 of the present invention will be described with reference to the block diagram of FIG. 7 and the timing diagram of FIG. 8 .

The frequency conversion circuit of the present embodiment is that the sampling frequency is 768KHZ, the center frequency is 96KHZ, and the frequency conversion of the 12-bit digital baseband transmission signal with a bandwidth of 16KHZ is a bandpass transmission signal with a sampling frequency of 96MHZ (=768KHZ×250) and a center frequency of 24MHZ. The BPF with a frequency of 24MHZ gets the transmitted signal. The transfer function H (Z) of the digital filter of the present embodiment is also expressed by the above equation (1), and a part of the filter working at a sampling frequency of 768KHZ is the same as in Embodiment 1, but the input signal is converted through a 768KHZ D/A converter After sampling the value signal, use a switched capacitor circuit (hereinafter referred to as SC circuit) to perform 96MHZ operation processing, thereby suppressing the conversion speed of the D/A converter and reducing power consumption.

In FIG. 7 , 201 is a digital baseband transmission signal input terminal, which is connected to 202 and 235 . 202 is a 12-bit delay register, connected to 201, 203, 235. 203 is a 12-bit delay register, connected to 202, 204, 235. 204 is a 13-bit adder connected to 201, 203, 205, and 207. 205 is a 13-bit delay register, connected to 204, 206, 235. 206 is a 13-bit delay register, connected to 205, 207, 235. 207 is a 14-bit adder connected to 204 , 205 , 206 , 208 , and 210 . 208 is a 14-bit delay register, connected to 207, 209, 210, 235. 209 is a 14-bit delay register, connected to 208, 210, 235. 210 is a 15-bit adder connected to 207, 208, 209, and 211. 211 is a 12-bit D/A converter connected to 210, 212, and 235. 212 is a 0 signal insertion switch SW, which is connected to 211, 213, and 235. 213 is an analog switch connected to 212 and 214 . 214 is a capacitor with a capacitance of 2C, which is connected to 213 and 215 . 215 is an analog switch connected to 214, 218, 216. 216 is a capacitor with a capacity C, which is connected to 215 , 217 , 218 , and 220 . 217 is an operational amplifier connected to 215 , 216 , 218 , and 220 . 218 is an analog switch connected to 215 , 216 , 217 and 220 . 219 is a capacitor with a capacity of 2C, which is connected to 218 . 220 is an analog switch, connected to 216, 217, 218, 221. 221 is a capacitor with a capacity of 2C, which is connected to 220 and 222 . 222 is an analog switch, connected to 221, 223, 224, 225. 223 is a capacitor with a capacity C, which is connected to 222 , 224 , 225 , and 227 . 224 is an operational amplifier connected to 222 , 223 , 225 , and 227 . 225 is an analog switch, connected to 222, 223, 224, 225, 227. 226 is a capacitor with a capacity of 2C, which is connected to 225 . 227 is an analog switch, connected to 223, 224, 226, 228. 228 is a capacitor with a capacity of 2C, which is connected to 227 and 229 . 229 is an analog switch, connected to 228, 230, 231, 232. 230 is a capacitor with a capacity C, which is connected to 229 , 231 , 232 , and 234 . 231 is an operational amplifier connected to 229 , 230 , 231 , and 234 . 232 is an analog switch, connected to 229, 230, 201, 233, 234. 233 is a capacitor with a capacity of 2C, which is connected to 232 . 234 is an analog BPF, which is connected to 230, 231, 233, and 236. 235 is a clock generating circuit, which is connected to 202 , 203 , 205 , 206 , 208 , 209 , 211 , and 212 . 236 is an analog modulation output terminal, which is connected with 234.

Next, the operation of this embodiment will be described. In Fig. 7, if at first from the leading edge of the 768KHZ clock signal of clock generation circuit 235, input 1 sampling signal from digital baseband transmission signal input end 201, then adder 204 adds the content of delay register 203 in the input signal, addition The adder 207 adds the content of the delay register 206 to the output of the adder 204, and the adder 210 adds the content of the delay register 209 to the output of the 207, and the result of the addition is output to the D/A converter 211 and converted into After the sampling value signal is output to SW212, the output of the delay register 208 is transmitted to the delay register 209 on the trailing edge of the 768KHZ clock signal, the output of the adder 207 is transmitted to the delay register 208, and the output of the delay register 205 is transmitted to the delay register 206 , the output of the adder 204 is transmitted to the delay register 205 , the output of the delay register 202 is transmitted to the delay register 203 , and the input signal from the digital bandpass transmit signal input terminal 201 is transmitted to the delay register 202 . In addition, starting from the leading edge of the 768KHZ clock, within 1 clock time unit of the 96MHZ clock signal, SW212 outputs the output of the D/A converter 211, but outputs 0 in the remaining 124 clock time units, thereby outputting 96MHZ sampling Signal. In addition, at the leading edge of the 96MHZ clock φ1 generated by the clock generating circuit 235, the capacitor 214 is charged to the output voltage of SW212, the capacitors 219 and 221 are charged to the output voltage of the operational amplifier 217, and the capacitors 226 and 228 are charged to the operational amplifier 224. The output voltage of the operational amplifier 231, the capacitor 233 is charged to the output voltage of the operational amplifier 231, and these states are maintained at the trailing edge of the clock φ1. Then, at the leading edge of the 96MHZ clock φ2 generated by the clock generation circuit 235, the charges of capacitors 214 and 219 are transferred to capacitor 216, the charges of capacitors 221 and 226 are transferred to capacitor 223, and the capacitance of capacitors 228 and 233 is transferred to Capacitor 230, and kept at the trailing edge of the clock φ2, through the analog BPF234 with a center frequency of 24MHZ to obtain an analog transmit signal.

As described above, according to the second embodiment of the present invention, similar to the first embodiment, the frequency conversion can be performed while achieving circuit miniaturization and uncontrolled. In addition, according to the above equation (1), when the digital baseband transmit signal is interpolated and the higher harmonics are extracted, the D/A conversion is performed at the frequency of 768KHZ after performing the molecular part in the equation (1) with a digital circuit , Implementing the denominator part in equation (1) with an uncontrolled SC circuit can suppress the D/A conversion speed and reduce power loss.

(Example 3)

Next, Embodiment 3 of the present invention will be described. Fig. 9 is a block diagram showing the configuration of the frequency conversion circuit in the modulation circuit of this embodiment.

In the modulation circuit of this embodiment, after the 12-bit digital baseband transmission signal with a sampling frequency of 48KHZ and a bandwidth of 16KHZ is converted into a digital bandpass transmission signal with a sampling frequency of 96MHZ (=384KHZ×250) and a center frequency of 24MHZ, D/A conversion is performed , the analog transmission signal is obtained through the BPF with a center frequency of 24MHZ. The transfer function H(Z) of the digital filter of this embodiment is expressed by equation (2). $\mathrm{HB}\left(Z\right)=\frac{1+Z^{-8}}{1+Z^{-2}}=1-Z^{-2}+Z^{-4}-Z^{-6}\…\…\left(2\right)$

Here, Z ^-1 represents a delay of (384KHZ) ^-1 .

In FIG. 9 , 301 is a digital baseband transmission signal input terminal, which is connected to 302 and 320 . 302 is a 12-bit delay register, connected to 301, 303, 320. 303 is a 12-bit delay register connected to 302, 304, 320. 304 is a 13-bit adder connected to 301, 303, 305, and 307. 305 is a 13-bit delay register, connected to 304, 306, 320. 306 is a 13-bit delay register, connected to 305, 307, 320. 307 is a 14-bit adder connected to 304 , 305 , 306 , 308 , and 320 . 308 is a 14-bit delay register, which is connected to 307, 309, 310, and 320. 309 is a 14-bit delay register, connected to 308, 310, 320. 310 is a 15-bit adder connected to 307, 308, 309, and 311. 311 is a 0 signal insertion switch SW, connected to 310, 312, 320. 312 is a 16-bit subtractor connected to 311, 313, 314. 313 is a 16-bit delay register, which is connected to 312, 314, 315, and 320. 314 is a 17-bit subtractor connected with 313, 315, 316. 317 is a 17-bit delay register, connected to 314, 316, 320. 316 is an 18-bit subtractor connected with 315, 317, 318. 317 is an 18-bit delay register connected with 316, 318, 320. 318 is a 12-bit D/A converter connected to 316, 317, 319, and 320. 319 is a simulated BPF connected with 318 and 321 . 320 is a clock generation circuit, which is connected to 302 , 303 , 305 , 306 , 308 , 309 , 311 , 313 , 315 , 317 , and 318 . 321 is an analog modulated wave output terminal, which is connected with 319.

Next, the operation of this embodiment will be described. In Fig. 9, if first at the leading edge of the 48KHZ clock signal coming from the clock generation circuit 320, a sampling signal is input from the digital baseband transmission signal input terminal 301, then the adder 304 adds the content of the delay register 303 to the input signal 1. The adder 307 adds the content of the delay register 306 to the output of the adder 304, and the adder 310 adds the content of the delay register 309 to the output of the adder 307 and then outputs the result to SW311. On the trailing edge of the 48KHZ clock signal, The output of delay register 308 is transferred to delay register 309, the output of adder 307 is transferred to delay register 308, the output of delay register 305 is transferred to delay register 306, the output of adder 304 is transferred to delay register 305, delay register The output of 302 is transmitted to the delay register 303 , and the input signal from the digital baseband transmission signal input terminal 301 is transmitted to the delay register 302 . In addition, SW311 starts from the leading edge of the 48KHZ clock signal, outputs the output of the adder 310 in one clock time unit of the 96MHZ clock signal, but outputs 0 in the remaining 124 clock time units, thereby outputting the 96MHZ sampling signal. In addition, at the leading edge of the 96MHZ clock signal from the clock generating circuit 320, the subtractor 312 subtracts the content of the delay register 313 from the output of the SW311, the subtractor 314 subtracts the content of the delay register 315 from the output of the subtractor 312, and the subtractor 316 After subtracting the content of the delay register 317 from the output of the subtractor 314, the subtracted result is output to the D/A converter 318, and the output of the subtractor 316 is transmitted to the delay register 317, the subtractor 314 at the trailing edge of the 96MHZ clock signal The output of is transmitted to the delay register 315, and the output of the subtractor 312 is transmitted to the delay register 313. The output of the D/A converter 318 is converted into an analog transmission signal through an analog BPF 319 with a center frequency of 24MHZ.

As above, according to Embodiment 3 of this embodiment, by using a digital filter in the front stage while inserting the digital baseband transmission signal, a band-pass signal of 384KHZ sampling and a center frequency of 24MHZ is obtained, and in the latter stage, use The frequency conversion circuit of Embodiment 1 can try to make the modulation circuit miniaturized and uncontrolled.

(Example 4)

Next, Embodiment 4 of the present invention will be described. Fig. 10 is a block diagram showing the configuration of the frequency conversion circuit in the modulation circuit of this embodiment.

The modulation circuit of the present embodiment is that the sampling frequency is 48KHZ, the frequency conversion of 12 digital baseband transmission signals of bandwidth 16KHZ is sampling frequency 96MHZ (=384KHZ * 250), the digital band-pass transmission signal of center frequency 24MHZ passes through the BPF of center frequency 24MHZ Obtain an analog transmit signal. In this embodiment, the transfer function H (Z) of the digital filter can also be represented by equation (2), and the part working at the sampling frequency of 48KHZ is the same as that of embodiment 1, but the input signal is converted through the 48 KHZ D/A converter The switching capacitor circuit (hereinafter referred to as SC circuit) is used to process the 96MHZ operation after sampling the value signal, thereby suppressing the conversion speed of the D/A converter and realizing low power consumption.

In FIG. 10 , 401 is a digital baseband transmission signal input terminal, which is connected to 402 and 435 . 402 is a 12-bit delay register, connected to 401, 403, 435. 403 is a 12-bit delay register, connected to 402, 404, 435. 404 is a 13-bit adder connected to 401, 403, 405, and 407. 405 is a 13-bit delay register, connected to 404, 406, 435. 406 is a 13-bit delay register, connected to 405, 407, 435. 407 is a 14-bit adder, connected to 404, 405, 406, 408, 410. 408 is a 14-bit delay register, connected to 407, 409, 410, 435. 409 is a 14-bit delay register, connected to 408, 410, 435. 410 is a 15-bit adder connected to 407, 408, 409, and 411. 411 is a 12-bit D/A converter connected with 410, 412, 435. 412 is a 0 signal insertion switch SW, connected to 411, 413, 435. 413 is an analog switch connected to 412 and 414 . 414 is a capacitor with a capacity of 2C, which is connected to 413 and 415 . 415 is an analog switch, connected to 414, 418, 416. 416 is a capacitor with a capacity C, which is connected to 415 , 417 , 418 , and 420 . 417 is an operational amplifier connected to 415 , 416 , 418 , and 420 . 418 is an analog switch, connected with 415, 416, 417, 419, 420. 419 is a capacitor with a capacity of 2C, which is connected to 418 . 420 is an analog switch, connected with 416, 417, 418, 421. 421 is a capacitor with a capacity of 2C, which is connected to 420 and 422 . 422 is an analog switch, connected to 421, 423, 424, 425. 423 is a capacitor with a capacity C, which is connected to 422 , 424 , 425 , and 427 . 424 is an operational amplifier, which is connected to 422, 423, 425, and 427. 425 is an analog switch, connected with 422, 423, 424, 426, 427. 426 is a capacitor with a capacity of 2C, which is connected to 425 . 427 is an analog switch, connected to 423, 424, 426, 428. 428 is a capacitor with a capacity of 2C, which is connected to 427 and 429 . 429 is an analog switch, connected to 428, 430, 431, 432. 430 is a capacitor with a capacity C, which is connected to 429 , 431 , 432 , and 434 . 431 is an operational amplifier connected to 429 , 430 , 431 , and 434 . 432 is an analog switch, connected to 429, 430, 401, 433, 434. 433 is a capacitor with a capacity of 2C, which is connected to 432 . 434 is a simulated BPF, connected with 430, 431, 433, 436. 435 is a clock generating circuit, which is connected to 402 , 403 , 405 , 406 , 408 , 409 , 411 , and 412 . 436 is an analog modulated wave output terminal, which is connected with 434.

Next, the operation of this embodiment will be described. In Fig. 10, if at first by the leading edge of the 48KHZ clock signal that clock generation circuit 435 produces, input 1 sampling signal from digital baseband transmission signal input end 401, then adder 404 adds the content of delay register 403 in the input signal, The adder 407 adds the content of the delay register 406 to the output of the adder 404, and the adder 410 adds the content of the delay register 409 to the output of the adder 407, after the D/A converter 411 is converted into a sampled value signal, Output to SW412, the output of delay register 408 is transmitted to delay register 409 at the trailing edge of 48KHZ clock signal, the output of adder 407 is transmitted to delay register 408, the output of delay register 405 is transmitted to delay register 406, adder 404 The output of is transmitted to the delay register 405, the output of the delay register 402 is transmitted to the delay register 403, and the input signal from the digital baseband transmission signal input terminal 401 is transmitted to the delay register 402. In addition, SW412 starts from the leading edge of the 48KHZ clock signal, outputs the output of the D/A converter 411 in 1 clock time unit of 96MHZ, and outputs 0 in the remaining 124 time units, thereby outputting the 96MHZ sampling signal. Also, at the leading edge of the 96MHZ clock φ1 from the clock generating circuit 435, the capacitor 414 is charged to the output voltage of SW412, the capacitors 419 and 421 are charged to the output voltage of the operational amplifier 417, and the capacitors 426 and 428 are charged to the operational amplifier The output voltage of 424 charges the capacitor 433 to the output voltage of the operational amplifier 431 and maintains it at the trailing edge of the clock signal φ1. Then, at the leading edge of the 96MHZ clock signal φ2 from the clock generating circuit 435, the charges of capacitors 414 and 419 are transferred to capacitor 416, the charges of capacitors 421 and 426 are transferred to capacitor 423, and the charges of capacitors 428 and 433 are transferred to The capacitor 430 is held by the trailing edge of the clock signal φ2, and the analog transmit signal is obtained through the analog BPF 434 whose center frequency is 24MHZ.

According to the above embodiment 4 of the present invention, by inserting the digital baseband transmission signal with a digital filter in the previous stage, the bandpass signal of 384KHZ sampling and center frequency 24MHZ is obtained, and the frequency conversion circuit of embodiment 2 is used in the latter stage, The modulation circuit can be miniaturized and uncontrolled, and the D/A conversion speed can be suppressed and the power consumption can be reduced by using the frequency conversion circuit of the second embodiment.

(Example 5)

Next, Embodiment 5 of the present invention will be described with reference to the block diagram shown in FIG. 11 . The modulation circuit of the present embodiment 5 is to convert the 12-bit digital baseband transmission signal with a sampling frequency of 64KHZ and a bandwidth of 16KHZ into a digital band-pass transmission signal with a sampling frequency of 96MHZ (=384KHZ×250) and a center frequency of 24MHZ to perform D/A conversion , through the BPF with a center frequency of 24MHZ to obtain an analog transmit signal. In the present embodiment 5, at first, the digital filter represented by equation (3) is used to interpolate the input signal to obtain the baseband transmission signal with a sampling frequency of 384KHZ, and then multiply by 1, 0, ... 1, 0, 1, ... And it is converted to a 12-bit digital band-pass transmission signal with a center frequency of 96KHZ, and then the frequency conversion circuit of Embodiment 1 is used for frequency conversion. In Embodiment 3, the sampling frequency conversion ratio generated by Equation (2) is limited by the multiplication of the power of 2, but in Equation (3) it is possible to convert the sampling frequency of integer multiples. $\mathrm{HL}\left(Z\right)=\frac{1-Z^{-6}}{1-Z^{-1}}=1+Z^{-1}+Z^{-2}+Z^{-4}+Z^{-5}\…\…\left(3\right)$

In the formula, Z ^-1 represents the delay of (384KHZ) ^-1 .

In addition, Fig. 12 shows the impulse response waveform of HL (Z), Fig. 13 shows its frequency-gain characteristic curve, Fig. 14 shows the frequency-gain characteristic curve of H (Z), this filter is LPF (low-pass filter ), and since the higher harmonics of the integer multiples of 64KHZ correspond to the notch frequency of H(Z), it can be seen that the input signal is attenuated by more than 70dB.

In FIG. 11 , 501 is a digital baseband transmission signal input terminal, which is connected to 502 , 503 , and 518 . 502 is a 12-bit delay register, connected to 501, 503, 518. 503 is a 13-bit subtractor connected to 501, 502, 504, 505. 504 is a 13-bit delay register, connected to 503, 505, 517. 505 is a 14-bit subtractor connected to 503, 504, 506, 507. 506 is a 14-bit delay register, connected to 505, 507, 517. 507 is a 15-bit subtractor connected with 505, 506, 508, 517. 508 is a 0 times number insertion switch SW, which is connected with 507, 509, 517. 509 is a 16-bit subtractor connected with 508, 510, 511. 510 is a 16-bit delay register, connected to 509, 511, 517. 511 is a 17-bit subtractor connected with 510, 512, 513. 512 is a 17-bit delay register, connected with 511, 513, 517. 513 is an 18-bit subtractor connected with 512, 514, 515. 514 is an 18-bit delay register, connected to 513, 515, 517. 515 is a multiplier, connected to 513, 514, 516. 516 is the frequency conversion circuit of Embodiment 1, which is connected to 515, 517, and 518. 517 is a clock generating circuit, connected to 502, 504, 506, 508, 510, 512, 514, 516. 518 is a horizontal analog modulated wave output terminal, which is connected with 516.

The operation of this embodiment will be described below. In Fig. 11, if at first from the leading edge of the 64KHZ clock signal of the clock generation circuit 517, a sampling signal is input from the digital baseband transmission signal input terminal 501, then the subtractor 503 subtracts the content of the delay register 502 from the input signal, and the subtractor 505 subtracts the content of the delay register 504 from the output of the subtractor 503, and the subtractor 507 subtracts the content of the delay register 506 from the output of the 505 and outputs the result to SW508. On the trailing edge of the 64KHZ clock signal, the The output is transmitted to the delay register 506 , the output of the subtractor 503 is transmitted to the delay register 504 , and the input signal received from the digital baseband transmit signal input terminal 501 is transmitted to the delay register 502 . In addition, SW508 starts from the leading edge of the 64KHZ clock, outputs the output of the subtractor 507 in 1 clock time unit of 384KHZ, but outputs 0 in the remaining 5 clock time units, thereby outputting a sampling signal of 384KHZ. From the leading edge of the 384KHZ clock of clock generation circuit 517 again, subtractor 509 subtracts the content of delay register 510 from the output of SW508, subtractor 511 subtracts the content of delay register 512 from the output of subtractor 509, and subtractor 513 The content of the delay register 514 is subtracted from the output of the subtractor 511, and in the multiplier 515, it is multiplied by {j ⁿ + (-j) ⁿ }/2=1, 0, -1, 0, 1, ... and output , the output of the subtractor 509 is transmitted to the delay register 510 at the trailing edge of the 384KHZ clock signal, the output of the subtractor 511 is transmitted to the delay register 512, and the output of the subtractor 513 is transmitted to the delay register 514. Through the multiplier 515, a band-pass signal with 384KHZ sampling and a center frequency of 24MHZ is obtained. Therefore, in the subsequent frequency conversion circuit 516, a transmit signal is obtained through an analog BPF with a center frequency of 24MHZ.

According to the above embodiment 5 of the present invention, by inserting the digital baseband transmission signal with a digital filter in the previous stage, the band-pass signal of 384MHZ sampling and center frequency 24MHZ is obtained simultaneously, and the frequency conversion circuit of embodiment 1 is used in the subsequent stage. Make the modulation circuit miniaturized and uncontrolled. In addition, in the third embodiment, the sampling frequency conversion ratio of the digital baseband transmission signal is limited by the multiplication of the power of 2, but in the fifth embodiment, the sampling conversion of an integer multiple can be performed.

(Example 6)

Next, Embodiment 6 of the present invention will be described with reference to the block diagram of FIG. 15 . The modulation circuit of the present embodiment will have sampling frequency 64KHZ, the frequency conversion of 12 digital baseband transmission signals of bandwidth 16KHZ is to have sampling frequency 96MHZ (=384KHZ * 250), after the digital bandpass transmission signal of center frequency 24MHZ by means of center frequency is 24MHZ BPF to get the transmit signal. In this embodiment, after the input signal is converted into a 12-bit digital band-pass transmission signal with a sampling frequency of 384KHZ and a center frequency of 96KHZ in the same circuit as that of Embodiment 5 at the previous stage, the circuit of Embodiment 2 is used in the latter stage to The frequency conversion circuit performs frequency conversion.

In FIG. 15 , 601 is a digital baseband transmission signal input terminal, which is connected to 602 , 603 , and 617 . 602 is a 12-bit delay register, connected to 601, 603, 617. 603 is a 13-bit subtractor, connected with 601, 602, 604, 605. 604 is a 13-bit delay register, connected to 603, 605, 617. 605 is a 14-bit subtractor connected to 603, 604, 606, 607. 606 is a 14-bit delay register, connected to 605, 607, 617. 607 is a 15-bit subtractor connected with 605, 606, 608, 617. 608 is a 0 signal insertion switch SW, connected to 607, 609, 617. 609 is a 16-bit subtractor connected with 608, 610, 611. 610 is a 16-bit delay register, connected to 609, 611, 617. 611 is a 17-bit subtractor connected with 610, 612, 613. 612 is a 17-bit delay register, connected to 611, 613, 617. 613 is an 18-bit subtractor connected with 612, 614, 615. 614 is an 18-bit delay register, connected to 613, 615, 617. 615 is a multiplier connected to 613, 614, 616. 616 is the frequency conversion circuit of the second embodiment, connected to 615, 617, 618. 617 is a clock generating circuit, connected to 602, 604, 606, 608, 610, 612, 614, 616. 618 is an analog modulated wave output terminal, which is connected with 616.

The operation of the embodiment of the present invention will be described below. In Fig. 15, if at first from the leading edge of the 64KHZ clock signal of clock generation circuit 617, input 1 sampling signal from digital baseband transmission signal input end 601, then subtracter 603 just subtracts the content of delay register 602 from input signal, Subtractor 605 subtracts the content of delay register 604 from the output of subtractor 603, and subtractor 607 subtracts the content of delay register 606 from the output of subtractor 605, and the result is output to SW608, at the trailing edge of 64KHZ clock signal, subtraction The output of the subtractor 605 is transmitted to the delay register 606, the output of the subtractor 603 is transmitted to the delay register 604, and the input signal from the digital baseband transmit signal input terminal 601 is transmitted to the delay register 602. In addition, SW608 starts from the leading edge of the 64KHZ clock signal, outputs the output of the subtractor 607 in 1 clock time unit of 384KHZ, but outputs 0 in the remaining 5 clock time units, thereby outputting a 384KHZ sampling signal. And then from the 384KHZ clock leading edge of clock generation circuit 617, subtractor 609 subtracts the content of delay register 610 from the output of SW608, subtractor 611 subtracts the content of delay register 612 from the output of subtractor 609, subtractor 613 from Subtract the content of the delay register 614 from the output of the subtractor 611, then multiply {j ⁿ + (-j) ⁿ }/2=1, 0, -1, 0, 1, ... and then output by the multiplier 615, 384KHZ The output of subtractor 609 is transmitted to delay register 610 on the trailing edge of the clock, the output of subtractor 611 is transmitted to delay register 612 , and the output of subtractor 613 is transmitted to delay register 614 . Since the band-pass signal with 384KHZ sampling and center frequency of 24MHZ is obtained through the multiplier 615, the analog transmit signal is obtained through the analog BPF with a center frequency of 24MHZ in the subsequent frequency conversion circuit 616.

According to the above embodiment 6 of the present invention, by interpolating the digital baseband transmission signal in the previous stage through the digital filter, a band-pass signal of 384KHZ sampling and center frequency 24MHZ is obtained, and the frequency conversion circuit of embodiment 2 is used in the latter stage. The modulation circuit can be miniaturized and uncontrolled, and by using the frequency conversion circuit of the second embodiment, the D/A conversion speed can be suppressed and the power consumption can be reduced.

As explained above, according to the present invention, by interpolating the digital baseband transmission signal and raising the sampling frequency, the characteristic curve of the interpolation filter after D/A conversion can be made gentle, and the circuit size can be reduced. In addition, during the interpolation period of the digital baseband transmission signal, one of the frequency high-order harmonic spectrums that are integer multiples of the sampling frequency is extracted for frequency conversion, and D/A conversion is performed after the band-pass signal is generated. Therefore, the subsequent calculation The DC bias voltage in the amplifier, etc. will not cause deterioration such as carrier leakage in the modulated wave, so that the circuit can be made uncontrolled. In addition, since the above-mentioned digital filter for interpolation and frequency conversion is a filter transfer function that constitutes a rectangular impulse response without delay and distortion in the form of a series sum, it can be achieved by using a delay device and an adder-subtractor instead of a multiplier. Realization, also because the numerator of its transfer function works with a low-speed clock, compared with the filter structure of the usual product-sum operation, the number of delayers and adder-subtractors can be greatly reduced, thereby making the circuit smaller and reduce power consumption. In addition, since multiplication and a small number of adder-subtractors are not required, filter operations using integer operations without operational errors can be realized by only increasing the number of digits of the word length of the adder-subtractors.

What the embodiment of the present invention shows is all the modulation circuit situation realized by hardware, but the generation of the baseband signal with low sampling frequency, interpolation processing and the low-speed working part (molecular part) of the frequency conversion circuit may also be possible by using a digital signal processor (DSP ) etc. are realized by software. In this case, the additional circuit of DSP is only suitable for the high-speed working part (denominator part) of the frequency conversion circuit, so the circuit can be miniaturized. In addition, in the application of converting multiple modulation methods and multiple transmission ratios and executing the circuit, only the DSP software can be changed and the additional circuit can be used in common, so the circuit can also be miniaturized from this point.

Claims (6)

1. A frequency conversion circuit in which the sampling _{frequency is} f _s2 , the digital band-pass transmission signal with a center frequency of f _s2 /4 is subjected to L-fold interpolation processing (where L is an odd number) and high-order harmonic extraction (the center frequency is f _s3 /4, f _s3 = L*f _s2 ) , and the numerator of the above-mentioned digital filter transfer function HB(Z) ^NB2 is processed with the sampling frequency f _s2 and the denominator is processed with the sampling frequency f _s3 , and then D/A conversion is performed to obtain an analog transmission signal, $\mathrm{HB}\left(Z\right)=\frac{1-{(-Z^{-2})}^L}{1+Z^{-2}}$ ＝1-Z ^-2 +Z- ^4- …+(-Z ^-2 ) ^L-1 …(1) In the formula, L represents an odd number, and Z ^-1 represents a delay of 1/f _s3 . 2. the frequency conversion circuit described in claim 1, in this circuit, by the described digital filter that the transfer function (HB (Z)) of N ₂ (N is an integer) equation (1) cascaded together will The digital band-pass transmission signal whose sampling frequency is f _s2 and center frequency f _s2 /4 is subjected to L times interpolation processing (wherein, L is an odd number) and high-order harmonic extraction (center frequency is f _s3 /4, f _s3 =L *f _s2 ), use the sampling frequency f _s2 to carry out the arithmetic processing and D/A conversion of the numerator of the above-mentioned digital filter transfer function (HB(Z) ^NB2 ) to obtain the sampled value signal, and then pass through the switched capacitor circuit with the sampling frequency f _s3 /2 processes the denominator of the transfer function (HB(Z) ^NB2 ) to interpolate the above sampled value signal. 3. frequency conversion circuit according to claim 1, the digital filter that the transfer function (HB (Z)) cascading of the above-mentioned equation (1) of N1 (N is an integer) claim 1 gets up according to claim The same processing method of the frequency conversion circuit of 1 performs L-fold interpolation processing (where L is a power _of 2 of 4 or above) and the extraction of high-order harmonic components to obtain the sampling frequency f _s2 , the digital band-pass transmission signal whose center frequency is f _s2 /4, and then make it frequency-converted by the frequency conversion circuit of claim 1. 4. frequency conversion circuit according to claim 2, the digital filter that the transfer function HB (Z) in the equation (1) of N1 (N is an integer) claim 1 is cascaded together, according to claim 2 The same processing method as the frequency conversion circuit performs L times interpolation processing (where L is a power of 2 of 4 or _above ) and extraction of high-order harmonic components to obtain the sampling frequency f _s2 , the digital band-pass transmission signal whose center frequency is f _s2 /4, and then make it frequency-converted by the frequency conversion circuit of claim 2 above. 5. frequency conversion circuit according to claim 1, with the digital filter that the transfer function (HL (Z)) in the following equation (2) of N1 (N is an integer) cascaded together is f to sampling frequency The digital baseband transmission signal of _s1 is carried out L times interpolation process (wherein L is integer), and described filter output is multiplied by {j ⁿ +(-j) ⁿ }/2 (in addition j is complex number=1,0, -1, 0, 1, ... to obtain a digital band-pass transmission signal whose sampling frequency is f _s2 (=L*f _s1 ) and center frequency is f _s2 /4, and then make it use the frequency conversion circuit of claim 1 to perform frequency conversion , $\mathrm{HL}\left(Z\right)=\frac{1-Z^{-L}}{1-Z^{-1}}$ ＝1-Z ^-1 +Z ^-2- …+Z- ^(L-1) …(2) In the formula, L is an integer, and Z ^-1 represents a delay of 1/f _s3 . 6. the frequency conversion circuit described in claim 5, in this circuit, with the digital filter that the transfer function (HL (Z)) of N1 (N is an integer) equation (2) cascaded together is to sampling frequency as The digital baseband transmission signal of f _s1 is interpolated by L times (where L is an integer), and the filter output is multiplied by {j ⁿ +(-j) ⁿ }/2 (where j is a complex number)=1 , 0, -1, 0, 1, ... to obtain the sampling frequency is f _s2 (=L*f _s1 ), the digital band-pass transmission signal that the center frequency is f _s2 /4, then make it with the frequency conversion of above-mentioned claim 2 The circuit performs frequency conversion.

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