CN1082277C - Circuit for frequency converting and modulating - Google Patents
Circuit for frequency converting and modulating Download PDFInfo
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- CN1082277C CN1082277C CN96107781A CN96107781A CN1082277C CN 1082277 C CN1082277 C CN 1082277C CN 96107781 A CN96107781 A CN 96107781A CN 96107781 A CN96107781 A CN 96107781A CN 1082277 C CN1082277 C CN 1082277C
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Abstract
The present invention provides a circuit for frequency converting and a circuit for modulating. In the circuit for modulating of the circuit for frequency converting, a filter having rectangular pulse waves multiplied by pulse response of cosine waves of f3/4 forms a band-pass type taking the f3/4 as a center, and a transferring function is represented in the form of sum of series; the numerator is processed on low-speed sampling frequency f2, the denominator is processed on high-speed sampling frequency f3 (f3 is equal to L multiplied by f2, and the L is an odd), and thus, the adjustment-free structure and the miniaturization of the circuit are tried for; in addition, the output of the numerator processed by the low-speed sampling frequency f2 carries out D/A conversion, and the part of the denominator processed by the high-speed sampling frequency f3 is completed by a switch capacitor. In such a way, the power consumption can be reduced.
Description
The present invention relates to frequency changer circuit and modulation circuit in the radio transmitting apparatus such as automobile telephone, portable phone.
Figure 16 is the pie graph of modulating device in the past.In Figure 16, the 1st, the digital baseband input that transmits is connected with D/A converter 2.The 3rd, low pass mode filter (following represent with LPF) joins with D/A converter 2.The 4th, analog multiplier is connected with LPF3.The 5th, the clock radiating circuit is connected with D/A converter 2.The 6th, oscillator is connected with analog multiplier 4.The 7th, simulation modulated wave output is connected with analog multiplier 4.
Action with regard to the example in the past of the above modulating device that constitutes describes below.If at first from the digital baseband input input digit base band transmit (for example voice signal of D/A conversion, modulator-demodulator (MODEM) signal etc.) that transmits, be transformed into the sampled value signal through D/A converter by 384KHz sampling clock, behind interpolation LPF3, become Analog Baseband again and transmit from clock generating circuit 5.Again with this signal in analog multiplier 4 with from behind the modulated wave that the 24MHz sine wave multiplies each other, frequency conversion is centre frequency 24MHz of oscillator 6 from 7 outputs of simulation modulated wave output.
As described above, even according in the past example, also can be as modulation circuit work.
But in above-mentioned modulation circuit in the past, the output of the sampled value of D/A converter need be taken as the interpolation LPF characteristic of the high order harmonic component frequency spectrum that suppresses to have low sample frequency 384KHz integer multiple frequency very precipitous.In addition, at this moment, make modulated wave produce carrier leak etc. to worsen phenomenon owing to be added in the Dc bias of operational amplifier in the circuit etc., thereby exist the problem that is difficult to make circuit miniaturization and does not have controlization (adjustment-free).
The present invention is intended to can make loop miniaturization and frequency changer circuit and the FM circuit of not having controlization for solving such problem in the past, providing.
The present invention is for achieving the above object, notice and to provide the filter transfer function that postpones distortionless rectangular pulse response with the sum of series form that does not need multiplying, transfer function with the sum of series form constitutes filter, carry out frequency conversion by when interpolating digital transmits, extracting the high order harmonic component frequency spectrum, attempt to make circuit miniaturization and do not have controlization.
Improve sample frequency by the interpolating digital base band transmit, make the indicatrix variation of the interpolation filter after D/A changes slowly just can make circuit miniaturization.In addition, when the interpolation that digital baseband transmits, carry out frequency conversion to obtain carrying out the D/A conversion behind the bandpass signal by a frequency in the frequency high order harmonic component frequency spectrum that extracts the sample frequency integral multiple, therefore added Dc bias will can not make modulated wave produce carrier leak etc. to worsen phenomenon, just can make circuit not have controlization in the operational amplifier afterwards etc.Moreover; carry out the digital filter of above-mentioned interpolation and frequency conversion owing to be the filter transfer function that constitutes the rectangular pulse response of no delay distortion with the form of sum of series; therefore; just can realize with delayer and adder-subtractor without multiplier; also because the molecule of this transfer function with low-speed clock signal work; with by the filter configuration of usually long-pending and (sum of products) computing relatively; might reduce the quantity of delayer and adder-subtractor significantly; therefore, just can attempt to make more miniaturization of circuit, power consumption still less.In addition owing to do not need multiplying and a spot of adder-subtractor, by only the word length (adder-subtractor number) of adder-subtractor being increased several positions, just can carry out no arithmetic eror, with the filter computing of integer arithmetic.
Fig. 1 represents the block diagram that the frequency changer circuit in the embodiment of the invention 1 constitutes.
Fig. 2 represents the timing diagram of the work in the embodiment of the invention 1.
Fig. 3 represents the oscillogram of the impulse response waveform of HB in the embodiment of the invention 1 (Z).
Fig. 4 a and 4b are the performance plots of relation between the frequency of the HB (Z) of expression in the embodiment of the invention 1 and the gain.
Fig. 5 A and 5B be the expression embodiment of the invention 1 in H (Z) frequency and the gain between the relation performance plot.
Fig. 6 A, 6B and 6C are the block diagrams that is expressed as the filter construction of realizing the transfer function in the embodiment of the invention 1.
Fig. 7 is the block diagram of the frequency changer circuit structure in the expression embodiment of the invention 2.
Fig. 8 is the timing diagram of the work of the expression embodiment of the invention 2.
Fig. 9 is the block diagram of modulation circuit part-structure in the expression embodiment of the invention 3.
Figure 10 is the block diagram that is illustrated in modulation circuit part-structure in the embodiment of the invention 4.
Figure 11 is the block diagram that is illustrated in modulation circuit structure in the embodiment of the invention 5.
Figure 12 is the oscillogram that is illustrated in the impulse response waveform of HL in the embodiment of the invention 5 (Z).
Figure 13 be illustrated in HL in the embodiment of the invention 5 (Z) frequency and the gain between the relation performance plot.
Figure 14 be illustrated in H in the embodiment of the invention 5 (Z) frequency and the gain between the relation performance plot.
Figure 15 is the block diagram that is illustrated in frequency changer circuit structure in the embodiment of the invention 6.
Figure 16 represents the block diagram of frequency changer circuit structure in the past.
(embodiment 1)
With reference to the timing diagram of the block diagram of Fig. 1 and Fig. 2 frequency changer circuit in the embodiment of the invention 1 is described below.
The frequency changer circuit of present embodiment 1 is with sample frequency 768KHZ, centre frequency 96KHZ, bandwidth be digital band pass that the logical frequency conversion that transmits of the 12 bit digital bands of 16KHZ is sample frequency 96MHZ (=768KHZ * 125), centre frequency 24MHZ transmit the back, through the D/A conversion, the band pass filter (BPF) by centre frequency 24MHZ obtains analog transmit signal.The transfer function of the digital filter of present embodiment 1 is expressed as follows with (1) formula:
Herein, Z
-1Represent one (96MHZ)
-1Delay.
Fig. 3 is the impulse response waveform of HB (Z), Fig. 4 A and 4B represent its frequency-gain characteristic, Fig. 5 A and 5B represent frequency-gain characteristic of H (Z), this filter is to have the band pass filter that centre frequency is 24MHZ (BPF), because the high order harmonic component frequency spectrum that leaves (at interval) centre frequency 384KHZ integral multiple is equivalent to the trap frequency of H (Z), as seen this frequency spectrum is attenuated more than the 70dB.Fig. 6 A, 6B and 6C are the structures that expression is used for realizing the transfer function of equation (1) expression, herein, Fig. 6 A only is a kind of cascade structure, Fig. 6 B is the structure (configuration) of direct type of the transfer function H B (Z) of Fig. 6 A, and Fig. 6 C is corresponding with Fig. 6 B, but the molecular moiety that is operated in the transfer function H that sample frequency is 768KHZ (Z) is rearranged the prime that becomes to be connected it, and the denominator that is operated in the transfer function H that sample frequency is 96MHZ (Z) partly is rearranged the back level that becomes to be connected it.In the present embodiment, adopt the structure (configuration) of figure C.
In Fig. 1, input 101 is the digital baseband inputs that transmit, and it is connected with clock generating circuit 120 (the following sign flag of only using sometimes) with delay time register 102.102 is 12 delay time registers, is connected with 101,103,120.103 is 12 delay time registers, and it is connected with 102,104,120.104 is 13 adders, is connected with 101,103,105,107.105 is 13 delay time registers, is connected with 104,106,120.106 is 13 delay time registers, and it is connected with 105,107,120.107 is 14 adders, is connected with 104,105,106,108,110.108 is 14 delay time registers, and it is connected with 107,109,110,120.109 is 14 delay time registers, and it is connected with 108,110,120.110 is 15 adders, is connected with 107,108,109,111.111 is that 0 signal inserts switch SW, and it is connected with 110,112,120.112 is 16 subtracters, is connected with 111,113,114.113 is 16 delay time registers, is connected with 112,114,115,120.114 is 17 subtracters, is connected with 113,115,116.115 is 17 delay time registers, is connected with 114,116,120.116 is 18 subtracters, is connected with 115,117,118.117 is 18 bit registers, is connected with 116,118,120.118 is 12 D/A converters, is connected with 116,117,119,120.The 119th, simulation BFF is connected with 118,121.The 120th, clock generating circuit is connected with 102,103,105,106,108,109,111,113,115,117,118.The 121st, simulation harmonic output is connected with 119.
Next the work with regard to present embodiment describes.Among Fig. 1, if at first in the 768KHZ clock signal forward position input that from clock generating circuit 120, comes from transmit 1 sampling (signal) of input of digital baseband, then adder 104 is with the content and the input signal addition of delay time register 103, adder 107 is with the output addition of the content and the adder 104 of delay time register 106, adder 110 with the output of the content of delay time register 109 and adder 107 mutually adduction the result of addition is outputed to SW111, behind the 768KHZ clock, be transferred to delay time register 109 along output with delay time register 108, the output of adder 107 is transferred to delay time register 108, the output of delay time register 105 is transferred to delay time register 106, the output of adder 104 is transferred to delay time register 105, the output of delay time register 102 is transferred to delay time register 103, be transferred to delay time register 102 from the transmit input signal of input 101 of digital baseband.In addition, SW111 begins the output of output adder 110 in a clock time unit of 96KHZ clock signal from 768KHZ clock forward position, exports 0 in remaining 124 clock time, carries out 96MHZ sampling output thus.And then in forward position from the 96MHZ clock signal of clock generating circuit 120, subtracter 112 deducts the content of delay time register 113 from the output of SW111, subtracter 11 4 deducts the content of delay time register 115 from the output of subtracter 112, subtracter 116 deduct after the content of delay time register 117 from the output of subtracter 114 and will subtract the result output to D/A converter 118, the output on the back edge of 96MHZ clock signal with subtracter 116 is transferred to delay time register 117, subtracter 114 export to delay time register 115, the output of subtracter 112 is transferred to delay time register 113.The output of D/A converter 118 forms analog transmit signal through the simulation BPF119 with centre frequency 24MHZ.
Like this, according to embodiments of the invention 1, improve sample frequency by the interpolating digital base band transmit, the characteristic (curve) of simulation BPF119 changes slowly just can make circuit miniaturization.In addition, during digital band pass transmits insertion, a frequency in the high order harmonic component frequency spectrum of the integer multiple frequency by extracting (extraction) sample frequency is carried out conversion, obtain to carry out the D/A conversion behind the bandpass signal, therefore, added Dc bias can not make modulated wave produce carrier leak etc. to worsen phenomenon, just can make circuit realize nothing controlization (adjustment-free) in the operational amplifier etc. afterwards.
Moreover, carry out the digital filter of above-mentioned interpolation and frequency conversion, constitute the filter transfer function of the rectangular pulse response of no delay distortion by the form of sum of series, can not need multiplier and realize that with delayer and adder-subtractor the digital filter of the enough no delay distortion of energy does not need to adjust the frequency conversion of (not having control).In addition, although this digital filter sample frequency is 96MHZ, because its half processing is to move with 768KHZ, so each grade HB (Z) only needs 3 delayers, 2 subtracters, in other words, all need 9 delayers, 6 subtracters good, just can realize little, the little power consumption of size.In addition, if subtracter is prepared maximum 18 word lengths, just can realize error free computing.
(embodiment 2)
Next, with reference to the block diagram of Fig. 7 and the timing diagram of Fig. 8 the frequency changer circuit in the embodiment of the invention 2 is described.
The frequency changer circuit of present embodiment is to be that 768KHZ, centre frequency are that 96KHZ, bandwidth are that the 12 bit digital base band transmit frequency conversions of 16KHZ are logical the transmitting of band of sample frequency 96MHZ (=768KHZ * 250) centre frequency 24MHZ with sample frequency, is that the BPF of 24MHZ is transmitted through centre frequency.The transfer function H of the digital filter of present embodiment (Z) also is to represent with above-mentioned equation (1), identical with sample frequency 768KHZ part of work filter with embodiment 1, but input signal uses switched-capacitor circuit (to call SC circuit in the following text) to carry out the processing of 96MHZ action after being converted into the sampled value signal through the 768KHZD/A transducer, thereby suppresses conversion speed, the minimizing power consumption of D/A converter.
In Fig. 7, the 201st, the digital baseband input that transmits is connected with 202,235.202 is 12 delay time registers, is connected with 201,203,235.203 is 12 delay time registers, is connected with 202,204,235.204 is 13 adders, is connected with 201,203,205,207.205 is 13 delay time registers, is connected with 204,206,235.206 is 13 delay time registers, is connected with 205,207,235.207 is 14 adders, is connected with 204,205,206,208,210.208 is 14 delay time registers, is connected with 207,209,210,235.209 is 14 delay time registers, is connected with 208,210,235.210 is 15 adders, is connected with 207,208,209,211.211 are 12 D/A converters, are connected with 210,212,235.212 is that 0 signal inserts switch SW, is connected with 211,213,235.The 213rd, analog switch is connected with 212,214.The 214th, capacitance is the capacitor of 2C, is connected with 213,215.The 215th, analog switch is connected with 214,218,216.The 216th, capacity is the capacitor of C, is connected with 215,217,218,220.The 217th, operational amplifier is connected with 215,216,218,220.The 218th, analog switch is connected with 215,216,217,220.The 219th, capacity is the capacitor of 2C, is connected with 218.The 220th, analog switch is connected with 216,217,218,221.The 221st, capacity is the capacitor of 2C, is connected with 220,222.The 222nd, analog switch is connected with 221,223,224,225.The 223rd, capacity is the capacitor of C, is connected with 222,224,225,227.The 224th, operational amplifier is connected with 222,223,225,227.The 225th, analog switch is connected with 222,223,224,225,227.The 226th, capacity is the capacitor of 2C, is connected with 225.The 227th, analog switch is connected with 223,224,226,228.The 228th, capacity is the capacitor of 2C, is connected with 227,229.The 229th, analog switch is connected with 228,230,231,232.The 230th, capacity is the capacitor of C, is connected with 229,231,232,234.The 231st, operational amplifier is connected with 229,230,231,234.The 232nd, analog switch is connected with 229,230,201,233,234.The 233rd, capacity is the capacitor of 2C, is connected with 232.The 234th, simulation BPF is connected with 230,231,233,236.The 235th, clock generating circuit is connected with 202,203,205,206,208,209,211,212.The 236th, simulation harmonic output is connected with 234.
Action with regard to present embodiment describes below.In Fig. 7, if at first from the forward position of the 768KHZ clock signal of clock generating circuit 235 from digital baseband 1 sampled signal of input 201 inputs that transmits, then adder 204 is added to the content of delay time register 203 in the input signal, adder 207 is added to the content of delay time register 206 in the output of adder 204, adder 210 is added to the content of delay time register 209 in 207 the output, and with the result of addition output to convert the sampled value signal in the D/A converter 211 to after, output to SW212, be transferred to delay time register 209 in the output of the trailing edge delay register 208 of 768KHZ clock signal, the output of adder 207 is transferred to delay time register 208, the output of delay time register 205 is transferred to delay time register 206, the output of adder 204 is transferred to delay time register 205, the output of delay time register 202 is transferred to delay time register 203, be transferred to delay time register 202 from the transmit input signal of input 201 of digital band pass.In addition, from the forward position of 768KHZ clock, in 1 clock time unit of 96MHZ clock signal, the output of SW212 output D/A converter 211, but in remaining 124 clock time unit, export 0, export the 96MHZ sampled signal thus.In addition, forward position at the 96MHZ clock φ 1 that is produced by clock generating circuit 235, respectively capacitor 214 is charged to the output voltage of SW212, the output voltage that capacitor 219 and 221 is charged to operational amplifier 217, the output voltage that capacitor 226 and 228 is charged to operational amplifier 224, the output voltage that capacitor 233 is charged to operational amplifier 231, and these states is remained on the back edge of clock φ 1.Follow forward position at the 96MHZ clock φ 2 that is produced by clock generating circuit 235, respectively with the charge transfer of capacitor 214 and 219 to capacitor 216, with the charge transfer of capacitor 221 and 226 to capacitor 223, with the capacitive transmission of capacitor 228 and 233 to capacitor 230, and remain on the back edge of clock φ 2, be that the simulation BPF234 of 24MHZ obtains analog transmit signal through centre frequency.
As above, the same if adopt the embodiment of the invention 2 with embodiment 1, when seeking circuit miniaturization and not having controlization, can also carry out frequency conversion.In addition, according to top equation (1), when interpolation that transmits at digital baseband and high order harmonic component are extracted out, on the 768KHZ frequency, carry out the D/A conversion behind the molecular moiety in the equation (1) by carrying out with digital circuit, with the denominator part in the SC circuit execution equation (1) that does not have controlization, just can suppress D/A conversion speed minimizing power consumption.
(embodiment 3)
Next, describe with regard to embodiments of the invention 3.Fig. 9 is the block diagram of frequency changer circuit in the modulation circuit of expression present embodiment.
The modulation circuit of present embodiment, is after the digital band pass of sample frequency 96MHZ (=384KHZ * 250), centre frequency 24MHZ transmits with the 12 bit digital base band transmit of sample frequency 48KHZ, bandwidth 16KHZ through frequency conversion, carry out the D/A conversion, the BPF of process centre frequency 24MHZ has just obtained analog transmit signal.The transfer function H of the digital filter of present embodiment (Z) is represented with equation (2).
Herein, Z
-1Expression (384KHZ)
-1Delay.
In Fig. 9, the 301st, the digital baseband input that transmits is connected with 302,320.302 is 12 delay time registers, is connected with 301,303,320.303 is 12 delay time registers, is connected with 302,304,320.304 is 13 adders, is connected with 301,303,305,307.305 is 13 delay time registers, is connected with 304,306,320.306 is 13 delay time registers, is connected with 305,307,320.307 is 14 adders, is connected with 304,305,306,308,320.308 is 14 delay time registers, is connected with 307,309,310,320.309 is 14 delay time registers, is connected with 308,310,320.310 is 15 adders, is connected with 307,308,309,311.311 is that 0 signal inserts switch SW, is connected with 310,312,320.312 is 16 subtracters, is connected with 311,313,314.313 is 16 delay time registers, is connected with 312,314,315,320.314 is 17 subtracters, is connected with 313,315,316.317 is 17 delay time registers, is connected with 314,316,320.316 is 18 subtracters, is connected with 315,317,318.317 is 18 delay time registers, is connected with 316,318,320.318 is 12 D/A converters, is connected with 316,317,319,320.The 319th, simulation BPF is connected with 318,321.The 320th, clock generating circuit is connected with 302,303,305,306,308,309,311,313,315,317,318.The 321st, simulation modulated wave output is connected with 319.
Next the action to present embodiment describes.In Fig. 9, if at first in forward position from the 48KHZ clock signal of clock generating circuit 320, from digital baseband 1 sampled signal of input 301 input that transmits, then adder 304 is added to the content of delay time register 303 in the input signal, adder 307 is added to the content of delay time register 306 in the output of adder 304, adder 310 outputs to SW311 with the result after the content of delay time register 309 being added to the output of adder 307, on the back edge of 48KHZ clock signal, the output of delay time register 308 is transferred to delay time register 309, the output of adder 307 is transferred to delay time register 308, the output of delay time register 305 is transferred to delay time register 306, the output of adder 304 is transferred to delay time register 305, the output of delay time register 302 is transferred to delay time register 303, be transferred to delay time register 302 from the transmit input signal of input 301 of digital baseband.In addition, SW311 is from from 48KHZ clock signal forward position, in the output of 1 clock time unit's output adder 310 of 96MHZ clock signal, but in remaining 124 clock time units' output 0, exports the 96MHZ sampled signal thus.In addition, in 96MHZ clock signal forward position from clock generating circuit 320, subtracter 312 deducts the content of delay time register 313 from the output of SW311, subtracter 314 deducts the content of delay time register 315 from the output of subtracter 312, subtracter 316 from the output of subtracter 314, deduct will subtract after the content of delay time register 317 the result output to D/A converter 318, be transferred to delay time register 317 at the back of 96MHZ clock signal along subtracter 316 outputs, the output of subtracter 314 is transferred to delay time register 315, the output of subtracter 312 is transferred to delay time register 313.The output of D/A converter 318 becomes analog transmit signal through the simulation BPF319 of centre frequency 24MHZ.
As above, embodiment 3 according to present embodiment, by in prime, with digital filter when inserting digital baseband and transmitting, obtain bandpass signal sampling, centre frequency 24MHZ of 384KHZ,, use the frequency changer circuit of embodiment 1 in the back level, just can attempt to make the modulation circuit miniaturization, not have controlization.
(embodiment 4)
Next, the embodiment of the invention 4 is described.Figure 10 be the expression present embodiment modulation circuit in the frequency changer circuit block diagram.
The modulation circuit of present embodiment is to be that the 12 bit digital base band transmit frequency conversions of 48KHZ, bandwidth 16KHZ are sample frequency 96MHZ (=384KHZ * 250) with sample frequency, and the digital band pass of centre frequency 24MHZ transmits after the BPF of centre frequency 24MHZ obtains analog transmit signal.In the present embodiment, the also available equation of the transfer function H of digital filter (Z) (2) expression, the part that is operated in sample frequency 48KHZ is identical with embodiment 1, but input signal is converted to behind the sampled value signal processing of carrying out the 96MHZ action through switched-capacitor circuit (below be labeled as SC circuit) through 48 KHZ D/A converters, thereby the conversion speed that will suppress D/A converter realizes low power consumption.
In Figure 10, the 401st, the digital baseband input that transmits is connected with 402,435.402 is 12 delay time registers, is connected with 401,403,435.403 is 12 delay time registers, is connected with 402,404,435.404 is 13 adders, is connected with 401,403,405,407.405 is 13 delay time registers, is connected with 404,406,435.406 is 13 delay time registers, is connected with 405,407,435.407 is 14 adders, is connected with 404,405,406,408,410.408 is 14 delay time registers, is connected with 407,409,410,435.409 is 14 delay time registers, is connected with 408,410,435.410 is 15 adders, is connected with 407,408,409,411.411 is 12 D/A converters, is connected with 410,412,435.412 is that 0 signal inserts switch SW, is connected with 411,413,435.The 413rd, analog switch is connected with 412,414.The 414th, capacity is the capacitor of 2C, is connected with 413,415.The 415th, analog switch is connected with 414,418,416.The 416th, capacity is the capacitor of C, is connected with 415,417,418,420.The 417th, operational amplifier is connected with 415,416,418,420.The 418th, analog switch is connected with 415,416,417,419,420.The 419th, capacity is the capacitor of 2C, is connected with 418.The 420th, analog switch is connected with 416,417,418,421.The 421st, capacity is the capacitor of 2C, is connected with 420,422.The 422nd, analog switch is connected with 421,423,424,425.The 423rd, capacity is the capacitor of C, is connected with 422,424,425,427.The 424th, operational amplifier is connected with 422,423,425,427.The 425th, analog switch is connected with 422,423,424,426,427.The 426th, capacity is the capacitor of 2C, is connected with 425.The 427th, analog switch is connected with 423,424,426,428.The 428th, capacity is the capacitor of 2C, is connected with 427,429.The 429th, analog switch is connected with 428,430,431,432.The 430th, capacity is the capacitor of C, is connected with 429,431,432,434.The 431st, operational amplifier is connected with 429,430,431,434.The 432nd, analog switch is connected with 429,430,401,433,434.The 433rd, capacity is the capacitor of 2C, is connected with 432.The 434th, simulation BPF is connected with 430,431,433,436.The 435th, clock generating circuit is connected with 402,403,405,406,408,409,411,412.The 436th, simulation modulated wave output is connected with 434.
Next the action to present embodiment describes.In Figure 10, if at first in the forward position of the 48KHZ clock signal that takes place by clock generating circuit 435 from digital baseband 1 sampled signal of input 401 inputs that transmits, then adder 404 is added to the content of delay time register 403 in the input signal, adder 407 is added to the content of delay time register 406 in the output of adder 404, adder 410 is added to the content of delay time register 409 in the output of adder 407, after D/A converter 411 is converted to the sampled value signal, output to SW412, output at the trailing edge delay register 408 of 48KHZ clock signal is transferred to delay time register 409, and the output of adder 407 is transferred to delay time register 408, the output of delay time register 405 is transferred to delay time register 406, the output of adder 404 is transferred to delay time register 405, the output of delay time register 402 is transferred to delay time register 403, be transferred to delay time register 402 from the transmit input signal of input 401 of digital baseband.In addition, SW412 in the output of 1 clock time unit of 96MHZ output D/A converter 411, and in remaining 124 chronomere's output 0, exports the 96MHZ sampled signal from from 48KHZ clock signal forward position thus.Also have, in forward position from the 96MHZ clock φ 1 of clock generating circuit 435, respectively capacitor 414 is charged to the output voltage of SW412, capacitor 419 and 421 is charged to the output voltage of operational amplifier 417, capacitor 426 and 428 is charged to the output voltage of operational amplifier 424, capacitor 433 is charged to the output voltage of operational amplifier 431, and back along keeping with clock signal φ 1.Then, in forward position from the 96MHZ clock signal φ 2 of clock generating circuit 435, charge transfer with capacitor 414 and 419 arrives capacitor 416 respectively, the charge transfer of capacitor 421 and 426 is arrived capacitor 423, the charge transfer of capacitor 428 and 433 is arrived capacitor 430, and back along keeping with clock signal psi 2, be that the simulation BPF434 of 24MHZ obtains analog transmit signal through centre frequency.
According to the above embodiment of the invention 4, by in prime digital baseband being transmitted with in the digital filter insertion, obtain 384KHZ bandpass signal sampling, centre frequency 24MHZ, and at back grade of frequency changer circuit that uses embodiment 2, just can make the modulation circuit miniaturization and not have controlization, can suppress the D/A conversion speed and reduce power consumption by the frequency changer circuit that uses embodiment 2 in addition.
(embodiment 5)
Below, with reference to the block diagram of Figure 11 the embodiment of the invention 5 is described.The modulation circuit of present embodiment 5, be that 12 bit digital base band transmit frequency conversions with sample frequency 64KHZ, bandwidth 16KHZ are to carry out the D/A conversion after the digital band pass of sample frequency 96MHZ (=384KHZ * 250), centre frequency 24MHZ transmits, through the BPF of centre frequency 24MHZ, thereby obtain analog transmit signal.In present embodiment 5, at first use the digital filter of equation (3) expression, after the interpolation input signal obtains in the base band transmit that sample frequency is 384KHZ, multiply by 1,0 ... 1,0,1 ... and being transformed into logical the transmitting of 12 bit digital bands that centre frequency is 96KHZ, the frequency changer circuit with embodiment 1 carries out frequency conversion then.In embodiment 3, the sample frequency conversion ratio that is produced by equation (2) is subjected to the restriction of doubly taking advantage of of 2 powers, but is the conversion that might carry out the sample frequency of integer multiple in equation (3).
In the formula, Z
-1Expression (384KHZ)
-1Delay.
In addition, Figure 12 represents the impulse response waveform of HL (Z), Figure 13 represents its frequency-gain characteristic curve figure, Figure 14 represents frequency-gain characteristic curve figure of H (Z), this filter is LPF (low pass filter), and since the high order harmonic component of the frequency of the integral multiple of 64KHZ corresponding to the trap frequency of H (Z), so as can be known more than the attenuated input signal 70dB.
In Figure 11, the 501st, the digital baseband input that transmits is connected with 502,503,518.502 is 12 delay time registers, is connected with 501,503,518.503 is 13 subtracters, is connected with 501,502,504,505.504 is 13 delay time registers, is connected with 503,505,517.505 is 14 subtracters, is connected with 503,504,506,507.506 is 14 delay time registers, is connected with 505,507,517.507 is 15 subtracters, is connected with 505,506,508,517.508 is 0 times of number insertion switch SW, is connected with 507,509,517.509 is 16 subtracters, is connected with 508,510,511.510 is 16 delay time registers, is connected with 509,511,517.511 is 17 subtracters, is connected with 510,512,513.512 is 17 delay time registers, is connected with 511,513,517.513 is 18 subtracters, is connected with 512,514,515.514 is 18 delay time registers, is connected with 513,515,517.The 515th, multiplier is connected with 513,514,516.The 516th, the frequency changer circuit of embodiment 1 is connected with 515,517,518.The 517th, clock generating circuit is connected with 502,504,506,508,510,512,514,516.The 518th, horizontal plan modulated wave output is connected with 516.
To the action of present embodiment be described below.In Figure 11, if at first in 64KHZ clock signal forward position from clock generating circuit 517, from the digital baseband sampled signal of input 501 input that transmits, then subtracter 503 deducts the content of delay time register 502 from input signal, subtracter 505 deducts the content of delay time register 504 from the output of subtracter 503, subtracter 507 deducts the content of delay time register 506 and the result is outputed to SW508 from 505 output, back edge in the 64KHZ clock signal, the output of subtracter 505 is transferred to delay time register 506, the output of subtracter 503 is transferred to delay time register 504, is transferred to delay time register 502 from the digital baseband input signal that input 501 receives that transmits.SW508 is from the forward position from the 64KHZ clock in addition, in the output of 1 clock time unit's output subtracter 507 of 384KHZ, but remaining 5 clock times output 0, exports the sampled signal of 384KHZ thus.Again in forward position from the 384KHZ clock of clock generating circuit 517, subtracter 509 deducts the content of delay time register 510 from the output of SW508, subtracter 511 deducts the content of delay time register 512 from the output of subtracter 509, subtracter 513 deducts the content of delay time register 514 from the output of subtracter 511, in multiplier 515, multiply by { j
n+ (j)
n}/2=1,0 ,-1,0,1 ... back output is transferred to delay time register 510 in the back output along subtracter 509 of 384KHZ clock signal, and the output of subtracter 511 is transferred to delay time register 512, and the output of subtracter 513 is transferred to delay time register 514.By multiplier 515, obtain the bandpass signal of 384KHZ sampling, centre frequency 24MHZ again, therefore, the simulation BPF through centre frequency 24MHZ in the frequency changer circuit 516 is afterwards transmitted.
According to the above embodiment of the invention 5, transmit by inserting digital baseband with digital filter in prime, obtain the bandpass signal of 384MHZ sampling, centre frequency 24MHZ simultaneously, and use the frequency changer circuit of embodiment 1, just can make modulation circuit miniaturization and nothing controlization in the back level.In addition, in embodiment 3, the sample frequency conversion ratio that digital baseband transmits is subjected to the restriction of doubly taking advantage of of 2 powers, but in embodiment 5, can carry out the sample conversion of integral multiple.
(embodiment 6)
Next, the block diagram with reference to Figure 15 describes the embodiment of the invention 6.The modulation circuit of present embodiment, to have sample frequency 64KHZ, the 12 bit digital base band transmit frequency conversions of bandwidth 16KHZ are that the BPF of 24MHZ obtains to transmit for the back that transmits of the digital band pass with sample frequency 96MHZ (=384KHZ * 250), centre frequency 24MHZ by means of centre frequency.In the present embodiment, be after in the identical circuit of prime and embodiment 5, input signal being converted to 12 bit digital bands with sample frequency 384KHZ, centre frequency 96KHZ are logical and transmitting, carry out frequency conversion in the back level by means of the frequency changer circuit of embodiment 2.
In Figure 15, the 601st, the digital baseband input that transmits is connected with 602,603,617.602 is 12 delay time registers, is connected with 601,603,617.603 is 13 subtracters, is connected with 601,602,604,605.604 is 13 delay time registers, is connected with 603,605,617.605 is 14 subtracters, is connected with 603,604,606,607.606 is 14 delay time registers, with 605,607,, 617 be connected.607 is 15 subtracters, is connected with 605,606,608,617.608 is that 0 signal inserts switch SW, is connected with 607,609,617.609 is 16 subtracters, is connected with 608,610,611.610 is 16 delay time registers, is connected with 609,611,617.611 is 17 subtracters, is connected with 610,612,613.612 is 17 delay time registers, is connected with 611,613,617.613 is 18 subtracters, is connected with 612,614,615.614 is 18 delay time registers, is connected with 613,615,617.The 615th, multiplier is connected with 613,614,616.The 616th, the frequency changer circuit of embodiment 2 is connected with 615,617,618.The 617th, clock generating circuit is connected with 602,604,606,608,610,612,614,616.The 618th, simulation modulated wave output is connected with 616.
Action with regard to the embodiment of the invention describes below.In Figure 15, if at first from the forward position of the 64KHZ clock signal of clock generating circuit 617 from digital baseband 1 sampled signal of input 601 inputs that transmits, then subtracter 603 just deducts the content of delay time register 602 from input signal, subtracter 605 deducts the content of delay time register 604 from the output of subtracter 603, subtracter 607 deducts the content of delay time register 606 from the output of subtracter 605, and the result outputed to SW608, back edge in the 64KHZ clock signal, the output of subtracter 605 is transferred to delay time register 606, the output of subtracter 603 is transferred to delay time register 604, is transferred to delay time register 602 from the transmit input signal of input 601 of digital baseband.In addition, SW608 is from from 64KHZ clock signal forward position, in the output of 1 clock time unit's output subtracter 607 of 384KHZ, but in remaining 5 clock time units' output 0, exports the 384KHZ sampled signal thus.And then in 384KHZ clock forward position from clock generating circuit 617, subtracter 609 deducts the content of delay time register 610 from the output of SW608, subtracter 611 deducts the content of delay time register 612 from the output of subtracter 609, subtracter 613 deducts the content of delay time register 614 from the output of subtracter 611, multiply by { j with multiplier 615 again
n+ (j)
n}/2=1,0 ,-1,0,1 ... back output, the back output along subtracter 609 of 384KHZ clock is transferred to delay time register 610, and the output of subtracter 611 is transferred to delay time register 612, and the output of subtracter 613 is transferred to delay time register 614.Owing to the bandpass signal that obtains 384KHZ sampling, centre frequency 24MHZ by multiplier 615, so the simulation BPF by centre frequency 24MHZ obtains analog transmit signal in frequency changer circuit 616 thereafter.
According to the above embodiment of the invention 6, by through digital filter in prime interpolating digital base band transmit, obtain the bandpass signal of 384KHZ sampling, centre frequency 24MHZ, use the frequency changer circuit of embodiment 2 in the back level, just can make the modulation circuit miniaturization and not have controlization, in addition, by using the frequency changer circuit of embodiment 2, can suppress the D/A conversion speed and reduce power consumption.
As discussed above, according to the present invention, sample frequency is raise by the interpolating digital base band transmit, the characteristic curve of the interpolation filter after the D/A conversion is slowed down, thereby seek circuit miniaturization.In addition, during the interpolation that digital baseband transmits, undertaken carrying out the D/A conversion after frequency conversion, the generation bandpass signal by one in the frequency high order harmonic component frequency spectrum of extracting the sample frequency integral multiple out, therefore, be added in Dc bias in thereafter the operational amplifier etc. and just can not make modulated wave produce carrier leak etc. to worsen phenomenon, thereby can make circuit not have controlization.In addition, carry out the digital filter of above-mentioned interpolation and frequency conversion, owing to be the filter transfer function that constitutes the rectangular pulse response of no delay distortion with the form of sum of series, so just can realize with delayer and adder-subtractor without multiplier, also since the molecule of its transfer function with low-speed clock work, with the filter construction of common long-pending and computing relatively, can reduce the quantity of delayer and adder-subtractor significantly, thereby just can make circuit miniaturization and reduce power consumption more.In addition, owing to do not need multiplication and a spot of adder-subtractor, the figure place that only increases the word length of adder-subtractor just can realize no arithmetic eror, the filter computing of usefulness integer arithmetic.
Shown in the embodiment of the invention all is with hard-wired modulation circuit situation, but the generation of the low baseband signal of sample frequency, interpolation is handled and the tick-over part (molecular moiety) of frequency changer circuit also may realize with software mode by use digital signal processor (DSP) etc.The adjunct circuit of DSP owing to the high speed operation part (denominator part) that only is suitable for frequency changer circuit, thereby can make circuit miniaturization in this case.In addition, changing multiple modulation system, multiple transmission ratio and carrying out in the purposes of this circuit, just can use adjunct circuit jointly, therefore also can make circuit miniaturization according to this point owing to can only change the software of DSP.
Claims (6)
1. frequency changer circuit is in this circuit, by with N
2(N
2Being integer) digital filter that cascades up of transfer function (HB (Z)) in the individual equation (1) is f with sample frequency
S2, centre frequency is f
S2/ 4 digital band pass transmits and carries out L times of interpolation and handle (wherein L is an odd number) and high order harmonic component extraction (centre frequency is f
S3/ 4, f
S3=L*f
S2), and with above-mentioned digital filter transfer function HB (Z)
NB2Molecule with sample frequency f
S2, denominator is with sample frequency f
S3Carry out the D/A conversion after handling, obtain an analog transmit signal,
＝1-Z
-2+Z
-4-…+(-Z
-2)
L-1…(1)
In the formula, L represents odd number, Z
-1Expression 1/f
S3Delay.
2. the described frequency changer circuit of claim 1 is in this circuit, by with N
2The described digital filter that the transfer function (HB (Z)) of (N is an integer) individual equation (1) cascades up is f with sample frequency
S2, centre frequency f
S2/ 4 digital band pass transmits and carries out L times of interpolation and handle (wherein, L is an odd number) and high order harmonic component extraction (centre frequency is f
S3/ 4, f
S3=L*f
S2) time, use sample frequency f
S2Carry out above-mentioned digital filter transfer function (HB (Z)
NB2) the calculation process of molecule and the D/A conversion to obtain the sampled value signal, again through switched-capacitor circuit sample frequency f
S3/ 2 couples of transfer function (HB (Z)
NB2) denominator handle with the above-mentioned sampled value signal of interpolation.
3. frequency changer circuit according to claim 1, the digital filter that the transfer function (HB (Z)) of the above-mentioned equation (1) of the individual claim 1 of N1 (N is an integer) is cascaded up according to the same processing method of the frequency changer circuit of claim 1 with sample frequency f
S1Digital baseband transmit and carry out the extraction that L times of interpolation handled (wherein L is 4 or above 2 exponential) and high order harmonic component composition, be f to obtain sample frequency
S2, centre frequency is f
S2/ 4 digital band pass transmits, and makes its frequency changer circuit with claim 1 carry out frequency conversion then.
4. frequency changer circuit according to claim 2, the digital filter that the transfer function H B (Z) in the equation (1) of N1 (N is an integer) claim 1 is cascaded up, according to the processing method identical with the frequency changer circuit of claim 2 to sample frequency f
S1Digital band pass transmit and carry out extraction that L times of interpolation handle (wherein L is 4 or above 2 exponential) and high order harmonic component composition to obtain sample frequency f
S2, centre frequency is f
S2/ 4 digital band pass transmits, and makes its frequency changer circuit with above-mentioned claim 2 carry out frequency conversion then.
5. frequency changer circuit according to claim 1 is f with the digital filter that the transfer function (HL (Z)) in N1 (N is an integer) following equation (2) is cascaded up to sample frequency
S1Digital baseband transmit and carry out L times of interpolation and handle (wherein L is an integer), and { j is multiply by in described filter output
n+ (j)
n}/2 (j is plural number=1,0 ,-1,0,1 in addition ... to obtain sample frequency is f
S2(=L*f
S1), centre frequency is f
S2/ 4 digital band pass transmits, and makes its frequency changer circuit with above-mentioned claim 1 carry out frequency conversion then,
＝1-Z
-1+Z
-2-…+Z
-(L-1)…(2)
In the formula, L is an integer, Z
-1Expression 1/f
S3Delay.
6. the described frequency changer circuit of claim 5 in this circuit, is f with the digital filter that the transfer function (HL (Z)) of N1 (N is an integer) equation (2) is cascaded up to sample frequency
S1Digital baseband transmit and carry out L times of interpolation and handle (wherein L is an integer), and { j is multiply by in described filter output
n+ (j)
n}/2 (j is a plural number herein)=1,0 ,-1,0,1 ... to obtain sample frequency is f
S2(=L*f
S1), centre frequency is f
S2/ 4 digital band pass transmits, and makes its frequency changer circuit with above-mentioned claim 2 carry out frequency conversion then.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN96107781A CN1082277C (en) | 1996-05-30 | 1996-05-30 | Circuit for frequency converting and modulating |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN96107781A CN1082277C (en) | 1996-05-30 | 1996-05-30 | Circuit for frequency converting and modulating |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1167365A CN1167365A (en) | 1997-12-10 |
| CN1082277C true CN1082277C (en) | 2002-04-03 |
Family
ID=5119763
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96107781A Expired - Fee Related CN1082277C (en) | 1996-05-30 | 1996-05-30 | Circuit for frequency converting and modulating |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1082277C (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4855894A (en) * | 1987-05-25 | 1989-08-08 | Kabushiki Kaisha Kenwood | Frequency converting apparatus |
| EP0631377A2 (en) * | 1993-06-24 | 1994-12-28 | Robert Bosch Gmbh | Method for frequency modulation |
-
1996
- 1996-05-30 CN CN96107781A patent/CN1082277C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4855894A (en) * | 1987-05-25 | 1989-08-08 | Kabushiki Kaisha Kenwood | Frequency converting apparatus |
| EP0631377A2 (en) * | 1993-06-24 | 1994-12-28 | Robert Bosch Gmbh | Method for frequency modulation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1167365A (en) | 1997-12-10 |
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