CN108226744A - Board test method, device and board - Google Patents
Board test method, device and board Download PDFInfo
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- CN108226744A CN108226744A CN201611197609.8A CN201611197609A CN108226744A CN 108226744 A CN108226744 A CN 108226744A CN 201611197609 A CN201611197609 A CN 201611197609A CN 108226744 A CN108226744 A CN 108226744A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2836—Fault-finding or characterising
- G01R31/2837—Characterising or performance testing, e.g. of frequency response
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2815—Functional tests, e.g. boundary scans, using the normal I/O contacts
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K17/00—Methods or arrangements for effecting co-operative working between equipments covered by two or more of main groups G06K1/00 - G06K15/00, e.g. automatic card files incorporating conveying and reading operations
- G06K17/0022—Methods or arrangements for effecting co-operative working between equipments covered by two or more of main groups G06K1/00 - G06K15/00, e.g. automatic card files incorporating conveying and reading operations arrangements or provisious for transferring data to distant stations, e.g. from a sensing device
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- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The present invention proposes a kind of board test method, device and board, method and includes：Obtain No. SN of awaiting board card；Obtain the first data and the second data that awaiting board card is pre-stored；No. SN is verified using the first data and the second data；When being verified, board under test card is tested.By the present invention can by No. SN realize to the test of board, storage, transport, using, the tracking of processes such as scrap, ensure the trackability of board, meanwhile, it is capable to ensure the accuracy of test result.
Description
Technical field
The present invention relates to a kind of hardware circuit board card technique field more particularly to board test method, device and boards.
Background technology
In general, after the completion of hardware circuit board blocking is made, need to test board using test software, with inspection panel
Whether the functions such as the interface of card and communication, numeral input acquisition, numeral output, simulation input acquisition, simulation output are normal, and by
Appointees record test result, and mark of conformity is sticked to the board of test passes so that delivery uses.
In addition, in order to realize that board traces, bar code or Quick Response Code mark are pasted usually on board, by scanning bar shaped
Code or 2 D code information identification board information.
However, it is existing by way of manually pasting mark of conformity to the board after test, tested plate can not be supervised
Block whether consistent with the board for being labeled with mark of conformity, and the mistakes such as test leakage are susceptible in test process, lead to board
It tests insufficient.
Furthermore board retrospect is carried out by pasting bar code or Quick Response Code mark, due to bar code or Quick Response Code mark
It can be pasted after board is tested, the data in board production process can not be recorded, for example, board is in SMT (Surface
Mount Technology, surface mounting technology), THT (Through Hole Technology, Through-Hole Technology) process
The component data of middle assembling can not be by scanning bar code or Quick Response Code identification, also can not be with the MES of factory
(Manufacturing Execution System, manufacturing execution system) database binding.Moreover, the item pasted on board
Shape code or Quick Response Code mark easily become blurred due to the long-time service of board, cause board that can not trace.
Invention content
The purpose of the present invention is intended to solve one of the technical issues of above-mentioned at least to a certain extent.
For this purpose, first purpose of the present invention is to propose a kind of board test method, this method can be realized to board
Test, storage, transport, using, the tracking of processes such as scrap, ensure the accuracy of test result and the trackability of board.
Second object of the present invention is to propose a kind of board test device.
Third object of the present invention is to propose a kind of board.
To achieve these goals, first aspect present invention embodiment proposes a kind of board test method, including：It obtains
No. SN of awaiting board card；Obtain the first data and the second data that awaiting board card is pre-stored；Utilize the first data and the second data
No. SN is verified；When being verified, board under test card is tested.
The board test method that the embodiment of the present invention proposes, is prestored by No. SN and awaiting board card obtaining awaiting board card
The first data and the second data of storage, verify No. SN using the first data and the second data, and when being verified, right
Awaiting board card is tested.Thereby, it is possible to by No. SN realize to the test of board, storage, transport, using, the processes such as scrap
Tracking, ensure the trackability of board, meanwhile, it is capable to ensure the accuracy of test result.
To achieve these goals, second aspect of the present invention embodiment proposes a kind of board test device, including：First
Acquisition module, for obtaining awaiting board card No. SN；Second acquisition module, for obtaining the first data that awaiting board card is pre-stored
With the second data；Authentication module, for being verified using the first data and the second data to No. SN；Test module, for working as
When being verified, board under test card is tested.
The board test device that the embodiment of the present invention proposes, is prestored by No. SN and awaiting board card obtaining awaiting board card
The first data and the second data of storage, verify No. SN using the first data and the second data, and when being verified, right
Awaiting board card is tested.Thereby, it is possible to by No. SN realize to the test of board, storage, transport, using, the processes such as scrap
Tracking, ensure the trackability of board, meanwhile, it is capable to ensure the accuracy of test result.
To achieve these goals, third aspect present invention embodiment proposes a kind of board, including：SN is printed on board
Number；Board is dual-CPU architecture, including the first CPU and the 2nd CPU, wherein, the first CPU, for being based on the first Encryption Algorithm, root
According to No. SN the first data of generation；2nd CPU, for being based on the second Encryption Algorithm, according to No. SN the second data of generation；First SN is deposited
Reservoir, it is corresponding with the first CPU, for preserving the first data of the first CPU generations；2nd SN memories, it is corresponding with the 2nd CPU,
For preserving the second data of the 2nd CPU generations, wherein, the first data and the second data are used to verify No. SN.
The board that the embodiment of the present invention proposes by being printed on No. SN on board, and board is set as to include the first CPU
With the dual-CPU architecture of the 2nd CPU, the first CPU is used for based on the first Encryption Algorithm according to No. SN the first data of generation, the 2nd CPU
For being based on the second Encryption Algorithm according to No. SN the second data of generation, respectively the first CPU and the 2nd CPU settings corresponding first
SN memories and the 2nd SN memories, to be separately stored for the first data and the second data verified to No. SN.As a result,
It can ensure the trackability of board and the accuracy of board test result.
Description of the drawings
Above-mentioned and/or additional aspect and advantage of the invention will become from the following description of the accompanying drawings of embodiments
Significantly and it is readily appreciated that, wherein：
Fig. 1 is the flow diagram for the board test method that one embodiment of the invention proposes；
Fig. 2 is the flow diagram verified using the first data and the second data to No. SN；
Fig. 3 is the flow diagram for the board test method that another embodiment of the present invention proposes；
Fig. 4 is the flow diagram for the board test method that further embodiment of this invention proposes；
Fig. 5 is the flow diagram for the board test method that yet another embodiment of the invention proposes；
Fig. 6 is the structure diagram for the board test device that one embodiment of the invention proposes；
Fig. 7 is the structure diagram for the board test device that another embodiment of the present invention proposes；
Fig. 8 is the structure diagram for the board test device that further embodiment of this invention proposes；
Fig. 9 is the structure diagram for the board test device that yet another embodiment of the invention proposes；
Figure 10 is the structure diagram for the board test device that a further embodiment of the present invention proposes；
Figure 11 is the structure diagram for the board that one embodiment of the invention proposes.
Specific embodiment
The embodiment of the present invention is described below in detail, the example of the embodiment is shown in the drawings, wherein from beginning to end
Same or similar label represents same or similar element or the element with same or like function.Below with reference to attached
The embodiment of figure description is exemplary, it is intended to for explaining the present invention, and is not considered as limiting the invention.On the contrary,
The embodiment of the present invention includes falling into all changes in the range of the spirit and intension of attached claims, modification and equivalent
Object.
Below with reference to the accompanying drawings board test method, device and the board of the embodiment of the present invention are described.
In general, after the completion of the production of hardware circuit board, need to test board using relevant test software, with
Whether the various functions for examining board are normal, and record test result by appointees, and qualification is sticked to the board of test passes
Mark.In addition, in order to realize that board traces, bar code or Quick Response Code mark are pasted usually on board, by scanning bar code
Or 2 D code information identification board information.
However, it is existing by way of manually pasting mark of conformity to the board after test, it is susceptible to because of human error
The problem of causing mark of conformity patch wrong, and whether can not supervise tested board consistent with the board for being labeled with mark of conformity.
In addition, since bar code or Quick Response Code mark can only be pasted after board is tested, can not record in board production process
Data can not also be bound with the MES data library of factory.Moreover, pasted on board bar code or Quick Response Code mark, it is easy because
The long-time service of board and become blurred, cause board that can not trace.
In order to make up for the deficiencies of the prior art, the present invention proposes a kind of board test method, and this method can be applied to rail
The board of road field of traffic is tested automatically and board trace back process, to realize the trackability of board, and ensures test result
Accuracy.
Fig. 1 is the flow diagram for the board test method that one embodiment of the invention proposes.
As shown in Figure 1, the board test method includes：
S11：Obtain No. SN of awaiting board card.
In the present embodiment, before being tested using testing tool board, testing tool first has to obtain awaiting board card
SN (Serial Number, product ID) number.
Specifically, testing tool can scan No. SN be printed in awaiting board card by board code reader, to obtain SN
Number.
Wherein, No. SN of awaiting board card is made of board type, hardware version and board ID number.The SN of awaiting board card
Number it is to generate and be printed on bottom plate in the production process of awaiting board card.
In the production process of awaiting board card, after the completion of the bottom plate manufacture of awaiting board card, SN number servers generation one
A No. SN suitable for the awaiting board card, and be printed on bottom plate, it is then further continued for that other components are installed.
SN number servers are in the SN for generating awaiting board card, first according to the board type of awaiting board card, hardware version
This, sequentially uses not used board ID numbers to be numbered as the ID of the awaiting board card.Again by board type, hardware version and plate
Block ID number composition awaiting board cards No. SN.
For example, it is assumed that board type A, B, C, D ... represent, hardware version a, b of board, c, d ... represent,
Board ID numbers are represented with 10 for Arabic numerals.Assuming that the current board type of awaiting board card produced is A, hardware version
This is B, and the ID numbers of the board of type-A B versions have been assigned to 0000000089, and the ID numbers being not used by are followed successively by
0000000090、0000000091、0000000092、…、9999999999.The then type-A B versions for currently producing
Awaiting board card, SN number servers distribute board ID numbers 0000000090 for the awaiting board card first, to be measured further according to this
The board type of board, hardware version and board ID numbers form No. SN of the awaiting board card, are AB0000000090, and by group
Into SN codes be printed on the bottom plate of the awaiting board card.
In the production process of awaiting board card, after being printed on bottom plate for No. SN of awaiting board card, you can continue to install
Other components.
It should be noted that when installing other components, other components for being installed, which cannot be blocked on bottom plate, to be printed
No. SN, during ensureing to test board under test card, board code reader successful scan and can obtain the SN of the awaiting board card
Number.
S12：Obtain the first data and the second data that awaiting board card is pre-stored.
Wherein, awaiting board card takes two dual processors (Central Processing Unit, central processing unit) frame using two
Structure, each CPU correspond to a SN memory, are respectively used to the first data of storage and the second data.
In the present embodiment, after No. SN of awaiting board card is obtained, it is also necessary to which each CPU for obtaining awaiting board card is corresponding
The first data and the second data being pre-stored in SN memories.
It specifically, can be pre- by communications cable acquisition awaiting board card by the terminal (for example, computer) of testing results tool
The first data and the second data of storage.
It should be noted that the first data and the second data that awaiting board card is pre-stored are by the dual processors in awaiting board card
Generation is calculated, and be stored in the SN memories of corresponding CPU using different Encryption Algorithm.Specific generation and storing process will
It provides in subsequent content, is not described in detail herein.
S13：No. SN is verified using the first data and the second data.
In the present embodiment, the first data and the second number that awaiting board card is pre-stored are obtained in the terminal of testing results tool
According to later, you can relevant calibration tool is utilized, according to the first data of acquisition and the second data to the awaiting board card of acquisition
No. SN is verified.
Specifically, referring to Fig. 2, Fig. 2 is the flow diagram verified using the first data and the second data to No. SN.
As shown in Fig. 2, being verified using the first data and the second data to No. SN, may comprise steps of：
S21：No. SN is calculated based on the first Encryption Algorithm, to generate the first result.
S22：No. SN is calculated based on the second Encryption Algorithm, to generate the second result.
It in the present embodiment, is verified in order to No. SN to awaiting board card, needs to be utilized respectively the first Encryption Algorithm
No. SN of acquisition is calculated, to generate the first result；No. SN is calculated using the second Encryption Algorithm, to generate second
As a result.
Wherein, the first Encryption Algorithm and the second Encryption Algorithm include but not limited to MD5 (Message-Digest
Algorithm5, Message-Digest Algorithm 5), RSA public key encryption algorithms, DES (Data Encryption Algorithm, data
Encryption Algorithm), 3DES (Triple Data Encryption Algorithm, triple data encryption algorithm), AES
(Advanced Encryption Standard, Advanced Encryption Standard) and ECC (Elliptic Curves
Cryptography, elliptic curve cipher coding theory) in one kind, and the first Encryption Algorithm and the second Encryption Algorithm add to be different
Close algorithm.
It should be noted that in order to ensure the accuracy of SN verification results, encrypt and calculate used by the first result of generation
Encryption Algorithm is consistent used by the first data that method should be pre-stored with awaiting board card.Similarly, used by generating the second result
Encryption Algorithm is consistent used by the second data that Encryption Algorithm should be pre-stored with awaiting board card.
In addition, it is necessary to illustrate, in no particular order, the two can be same for step S21 and S22 the execution sequence in the present embodiment
Shi Zhihang can also be carried out, the invention is not limited in this regard successively.
S23：When the first result is consistent with the first data, and the second result is consistent with the second data, No. SN verification is determined
Pass through.
In the present embodiment, the first result, base are obtained to No. SN of awaiting board card calculate based on the first Encryption Algorithm
After the second Encryption Algorithm carries out No. SN of awaiting board card to calculate and obtains the second result, by the first result and the first of acquisition
Data comparison, the second result and the second data comparison obtained.When the first result is consistent with the first data, and the second result and the
When two data are consistent, it may be determined that SN is verified.
For example, it is assumed that the first data that awaiting board card is pre-stored using RSA Algorithm, the second data using
ECC algorithm, then the first Encryption Algorithm be RSA Algorithm, the second Encryption Algorithm ECC algorithm.First, based on RSA Algorithm to acquisition
No. SN of awaiting board card is calculated, and generates the first result；No. SN of awaiting board card is calculated based on ECC algorithm, is generated
Second result.And then by the first result of generation with the first data comparison, by the second result with the second data comparison.If first
As a result it is consistent with the first data, and the second result is consistent with the second data, then shows that No. SN of the awaiting board card is verified；If
First result is consistent with the first data, the second result and the second data are inconsistent, alternatively, the first result differs with the first data
Cause, the second result it is consistent with the second data, alternatively, the first result and the first data are inconsistent, the second result and the second data not
Unanimously, then show the awaiting board card authentication failed.
S14：When being verified, board under test card is tested.
In the present embodiment, after the verification to No. SN of awaiting board card is completed, you can judged whether according to verification result
The awaiting board card is tested.If No. SN of awaiting board card is verified, board under test card is tested；If awaiting board card
No. SN verification do not pass through, then board under test card is not tested.
It should be noted that be to be performed automatically by the testing tool installed in terminal to the test of awaiting board card, it can
Ensure that test process is not influenced by human factor, and then ensure the accuracy of test result.
The board test method of the embodiment of the present invention is pre-stored by No. SN and awaiting board card obtaining awaiting board card
First data and the second data, verify No. SN using the first data and the second data, and when being verified, to be measured
Board is tested.Thereby, it is possible to by No. SN realize to the test of board, storage, transport, using, scrap etc. processes with
Track, ensures the trackability of board, meanwhile, it is capable to ensure the accuracy of test result.
Fig. 3 is the flow diagram for the board test method that another embodiment of the present invention proposes.
As shown in figure 3, based on above-described embodiment, before step S12, which further includes：
S15：It will be in the first data and the second data recording to the SN memories of awaiting board card.
It had mentioned above, awaiting board card is dual-CPU architecture, and each CPU corresponds to a SN memory, is respectively used to deposit
Store up the first data and the second data.
It specifically, will be in the corresponding first SN memories of the first data recording to the first CPU；By the second data recording to
In the corresponding 2nd SN memories of two CPU.
More specifically, when by the corresponding first SN memories of the first data recording to the first CPU, need to obtain to be measured
No. SN of board, and the first data are generated, and then will be in the first data recording to the first SN memories based on the first Encryption Algorithm.
Similarly, it when by the corresponding 2nd SN memories of the second data recording to the 2nd CPU, also needs to obtain to be measured
No. SN of board, and the second data are generated, and then will be in the second data recording to the 2nd SN memories based on the second Encryption Algorithm.
Wherein, No. SN of awaiting board card is made of board type, hardware version and board ID number；First Encryption Algorithm
Include but not limited to one kind in MD5, RSA, DES, 3DES, AES and ECC, and the first Encryption Algorithm with the second Encryption Algorithm
It is different Encryption Algorithm from the second Encryption Algorithm.
For example, it is assumed that the first Encryption Algorithm be RSA Algorithm, the second Encryption Algorithm be ECC algorithm, the board under test of acquisition
No. SN of card is AB0000000090.Then after obtaining No. SN of awaiting board card, based on RSA Algorithm to AB0000000090
The first data of generation are encrypted, AB0000000090 are encrypted based on ECC algorithm the second data of generation.Replication tool will
The first data and the second data of generation are burned onto the corresponding first SN memories of the first CPU and the 2nd CPU corresponding the respectively
In two SN memories.
It should be noted that in the present embodiment, No. SN of awaiting board card is also to scan awaiting board card by board code reader
Bottom plate after obtain, No. SN is repeatedly obtained by Multiple-Scan, is verified caused by when can avoid scanning wrong inaccurate
Problem.
In addition, it is necessary to explanation, the scanning recognition of No. SN, the generation of the first data and the second data and the first number
It is controlled according to the burning process with the second data by replication tool, staff is only responsible for connecing for board code reader and replication tool
The fixed work of mouth.
The board test method of the present embodiment, by obtain the first data for being pre-stored of awaiting board card and the second data it
Before, by the first data and the second data recording to the SN memories of awaiting board card, for verifying No. SN of awaiting board card, energy
Enough solve it is existing using bar code or Quick Response Code mark carry out board identification technology in, due to bar code or Quick Response Code mark mill
Caused by damage the problem of None- identified.
Fig. 4 is the flow diagram for the board test method that further embodiment of this invention proposes.
As shown in figure 4, based on above-described embodiment, after step s 14, which further includes：
S16：Obtain test result.
In the present embodiment, after being tested using testing tool board under test card, testing tool is recorded and is protected automatically
Deposit test result.In order to analyze test result, need to obtain test result.
It should be noted that the test of awaiting board card and test result recording process are automatically performed by testing tool, nothing
It need to manually participate in, the human error in test process and recording process can be avoided, ensure the accuracy of test result.
S17：Test result and No. SN are bound, and preserved to data server.
In the present embodiment, after test result is obtained, you can test result is bound, and is preserved to data server,
For inquiring the test information of awaiting board card and test result later, ensure the trackability of awaiting board card test process.
Optionally, in one embodiment of the invention, as shown in figure 5, after step S16, the board test method
It can also include：
S18：Corresponding result label is sticked for awaiting board card according to test result.
In the present embodiment, after test result is obtained, can corresponding knot be sticked for awaiting board card according to test result
Fruit label.
Specifically, it can be labelled by operating air device machinery for awaiting board card.When test result shows awaiting board card
Each function and during normal interface, awaiting board card sticks qualified label by test, air device machinery for awaiting board card；Work as test
The result shows that when each function or interface of awaiting board card have abnormal, for awaiting board card not by test, air device machinery is to be measured
Board sticks unqualified label.
Further, after corresponding result label is sticked for awaiting board card, staff can be according to being labelled
By awaiting board card classification storage, used for delivery.
The board test method of the present embodiment, by being awaiting board card according to test result after test result is obtained
Corresponding result label is sticked, the wrong possibility of result label patch can be reduced.
It should be noted that the execution sequence of step S17 and step S18 in the present embodiment is in no particular order, can obtain
Any time after test result is taken to carry out, can be carried out at the same time or is successively carried out, the invention is not limited in this regard.
By obtaining test result, test result and No. SN are bound, and protects for the board test method of the embodiment of the present invention
It deposits to data server, can be further ensured that the test process of awaiting board card and the trackability of test result.
In order to realize above-described embodiment, the invention also provides a kind of board test device, Fig. 6 is one embodiment of the invention
The structure diagram of the board test device of proposition.
As shown in fig. 6, the board test device 60 includes：First acquisition module 610, the second acquisition module 620, verification mould
Block 630 and test module 640.Wherein,
First acquisition module 610, for obtaining awaiting board card No. SN.
Specifically, the first acquisition module 610 is used for：
No. SN be printed on by the scanning of board code reader in awaiting board card, to obtain No. SN.
Wherein, No. SN of awaiting board card is made of board type, hardware version and board ID number.
Second acquisition module 620, for obtaining the first data and the second data that awaiting board card is pre-stored.
Wherein, awaiting board card takes two dual-CPU architecture using two, and each CPU corresponds to a SN memory, is respectively used to
Store the first data and the second data.
Authentication module 630, for being verified using the first data and the second data to No. SN.
Specifically, as shown in fig. 7, authentication module 630 includes：
First authentication unit 631 calculates No. SN for being based on the first Encryption Algorithm, to generate the first result.
Second authentication unit 632 calculates No. SN for being based on the second Encryption Algorithm, to generate the second result.
Wherein, the first Encryption Algorithm and the second Encryption Algorithm include but not limited to MD5, RSA, DES, 3DES, AES and
One kind in ECC, and the first Encryption Algorithm is different Encryption Algorithm from the second Encryption Algorithm.
Determination unit 633, for when the first result it is consistent with the first data, and when the second result is consistent with the second data,
Determine that No. SN is verified.
Test module 640, for when being verified, testing board under test card.
It should be noted that this implementation is also applied for the explanation of board test method embodiment in previous embodiment
The board test device of example, realization principle is similar, and details are not described herein again.
The board test device of the embodiment of the present invention is pre-stored by No. SN and awaiting board card obtaining awaiting board card
First data and the second data, verify No. SN using the first data and the second data, and when being verified, to be measured
Board is tested.Thereby, it is possible to by No. SN realize to the test of board, storage, transport, using, scrap etc. processes with
Track, ensures the trackability of board, meanwhile, it is capable to ensure the accuracy of test result.
Fig. 8 is the structure diagram for the board test device that further embodiment of this invention proposes.
As shown in fig. 7, on the basis of as shown in Figure 6, which further includes：
Burning module 650, for before the first data and the second data that awaiting board card is pre-stored are obtained, first to be counted
According in the SN memories with the second data recording to awaiting board card.
Wherein, awaiting board card is dual-CPU architecture, and each CPU corresponds to a SN memory, is respectively used to the first number of storage
According to the second data.
Specifically, burning module 650 is used for：
It will be in the corresponding first SN memories of the first data recording to the first CPU；
It will be in the corresponding 2nd SN memories of the second data recording to the 2nd CPU.
More specifically, burning module 650 is used for：
No. SN of awaiting board card is obtained, and the first data are generated based on the first Encryption Algorithm, by the first data recording to the
In one SN memories；
No. SN of awaiting board card is obtained, and the second data are generated based on the second Encryption Algorithm；By the second data recording to
In two SN memories.
Wherein, No. SN of awaiting board card is made of board type, hardware version and board ID number；First Encryption Algorithm
Include but not limited to one kind in MD5, RSA, DES, 3DES, AES and ECC, and the first Encryption Algorithm with the second Encryption Algorithm
It is different Encryption Algorithm from the second Encryption Algorithm.
It should be noted that this implementation is also applied for the explanation of board test method embodiment in previous embodiment
The board test device of example, realization principle is similar, and details are not described herein again.
The board test device of the embodiment of the present invention, by obtaining the first data and the second number that awaiting board card is pre-stored
According to before, by the first data and the second data recording to the SN memories of awaiting board card, for verifying the SN of awaiting board card
Number, can solve it is existing using bar code or Quick Response Code mark carry out board identification technology in, due to bar code or Quick Response Code
Caused by mark abrasion the problem of None- identified.
Fig. 9 is the structure diagram for the board test device that yet another embodiment of the invention proposes.
As shown in figure 9, on the basis of as shown in Figure 6, which can also include：
Third acquisition module 660, for after testing board under test card, obtaining test result.
Preserving module 670 for test result and No. SN to be bound, and is preserved to data server.
Optionally, as shown in Figure 10, on the basis of as shown in Figure 9, which can also include：
Processing module 680, for after test result is obtained, corresponding knot to be sticked for awaiting board card according to test result
Fruit label.
It should be noted that this implementation is also applied for the explanation of board test method embodiment in previous embodiment
The board test device of example, realization principle is similar, and details are not described herein again.
By obtaining test result, test result and No. SN are bound, and protects for the board test device of the embodiment of the present invention
It deposits to data server, can be further ensured that the test process of awaiting board card and the trackability of test result.
Based on above-described embodiment, the present invention also proposes a kind of board, and Figure 11 is the board that one embodiment of the invention proposes
Structure diagram.
As shown in figure 11, board 110 includes：
No. SN is printed on board.
Board is dual-CPU architecture, including the first CPU1101 and the 2nd CPU1102.Wherein,
First CPU1101, for being based on the first Encryption Algorithm, according to No. SN the first data of generation.
2nd CPU1102, for being based on the second Encryption Algorithm, according to No. SN the second data of generation.
It can communicate between first CPU1101 and the 2nd CPU1102.
First SN memories 1103, it is corresponding with the first CPU1101, for preserving the first data of the first CPU1101 generations.
2nd SN memories 1104, it is corresponding with the 2nd CPU1102, for preserving the second data of the 2nd CPU1102 generations.
Wherein, the first data and the second data are used to verify No. SN.
The board of the embodiment of the present invention by being printed on No. SN on board, and board is set as to include the first CPU and
The dual-CPU architecture of two CPU, the first CPU are used for based on the first Encryption Algorithm according to No. SN the first data of generation, and the 2nd CPU is used for
Based on the second Encryption Algorithm according to No. SN the second data of generation, respectively the first CPU and the 2nd CPU set corresponding first SN to deposit
Reservoir and the 2nd SN memories, to be separately stored for the first data and the second data verified to No. SN.Thereby, it is possible to
Ensure the trackability of board and the accuracy of board test result.
It should be noted that in the description of the present invention, term " first ", " second " etc. are only used for description purpose, without
It is understood that indicate or implying relative importance.In addition, in the description of the present invention, unless otherwise indicated, the meaning of " multiple "
It is two or more.
Any process described otherwise above or method description are construed as in flow chart or herein, represent to include
Module, segment or the portion of the code of the executable instruction of one or more the step of being used to implement specific logical function or process
Point, and the range of the preferred embodiment of the present invention includes other realization, wherein can not press shown or discuss suitable
Sequence, including according to involved function by it is basic simultaneously in the way of or in the opposite order, to perform function, this should be of the invention
Embodiment person of ordinary skill in the field understood.
It should be appreciated that each section of the present invention can be realized with hardware, software, firmware or combination thereof.Above-mentioned
In embodiment, software that multiple steps or method can in memory and by suitable instruction execution system be performed with storage
Or firmware is realized.If for example, with hardware come realize in another embodiment, can be under well known in the art
Any one of row technology or their combination are realized：With for the logic gates to data-signal realization logic function
Discrete logic, have suitable combinational logic gate circuit application-specific integrated circuit, programmable gate array (PGA), scene
Programmable gate array (FPGA) etc..
Those skilled in the art are appreciated that realize all or part of step that above-described embodiment method carries
Suddenly it is that relevant hardware can be instructed to complete by program, the program can be stored in a kind of computer-readable storage medium
In matter, the program when being executed, one or a combination set of the step of including embodiment of the method.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing module, it can also
That each unit is individually physically present, can also two or more units be integrated in a module.Above-mentioned integrated mould
The form that hardware had both may be used in block is realized, can also be realized in the form of software function module.The integrated module is such as
Fruit is realized in the form of software function module and is independent product sale or in use, can also be stored in a computer
In read/write memory medium.
Storage medium mentioned above can be read-only memory, disk or CD etc..
In the description of this specification, reference term " one embodiment ", " example ", " is specifically shown " some embodiments "
The description of example " or " some examples " etc. means specific features, structure, material or the spy for combining the embodiment or example description
Point is contained at least one embodiment of the present invention or example.In the present specification, schematic expression of the above terms are not
It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office
It is combined in an appropriate manner in one or more embodiments or example.In addition, without conflicting with each other, the skill of this field
Art personnel can tie the different embodiments or examples described in this specification and the feature of different embodiments or examples
It closes and combines.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is impossible to limitation of the present invention is interpreted as, those of ordinary skill in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, changes, replacing and modification.
Claims (23)
1. a kind of board test method, which is characterized in that including：
Obtain No. SN of awaiting board card；
Obtain the first data and the second data that the awaiting board card is pre-stored；
Described No. SN is verified using first data and second data；
When being verified, the awaiting board card is tested.
2. the method as described in claim 1, which is characterized in that using first data and second data to the SN
It number is verified, including：
Described No. SN is calculated based on the first Encryption Algorithm, to generate the first result；
Described No. SN is calculated based on the second Encryption Algorithm, to generate the second result；
When first result is consistent with first data, and second result is consistent with second data, determine
Described No. SN is verified.
3. the method as described in claim 1, which is characterized in that No. SN of awaiting board card is obtained, including：
No. SN be printed on by the scanning of board code reader in the awaiting board card, to obtain described No. SN.
4. the method as described in claim 1, which is characterized in that obtaining the first data that the awaiting board card is pre-stored and the
Before two data, further include：
It will be in first data and second data recording to the SN memories of the awaiting board card.
5. method as claimed in claim 4, which is characterized in that the awaiting board card is dual-CPU architecture, and each CPU is corresponding
One SN memory, by first data and second data recording to the SN memories of the awaiting board card, including：
It will be in first data recording to the corresponding first SN memories of the first CPU；
It will be in second data recording to the corresponding 2nd SN memories of the 2nd CPU.
6. method as claimed in claim 5, which is characterized in that by first data recording to the first CPU corresponding first
In SN memories, including：
No. SN of the awaiting board card is obtained, and first data are generated based on the first Encryption Algorithm；
It will be in first data recording to the first SN memories.
7. method as claimed in claim 5, which is characterized in that by second data recording to the 2nd CPU corresponding second
In SN memories, including：
No. SN of the awaiting board card is obtained, and second data are generated based on the second Encryption Algorithm；
It will be in second data recording to the 2nd SN memories.
8. such as claim 1-7 any one of them methods, which is characterized in that No. SN of the awaiting board card by board type,
Hardware version and board ID number compositions.
9. method as claimed in claim 2, which is characterized in that first Encryption Algorithm and second Encryption Algorithm include
One kind in MD5, RSA, DES, 3DES, AES and ECC, and first Encryption Algorithm and second Encryption Algorithm are not
Same Encryption Algorithm.
10. the method as described in claim 1, which is characterized in that after testing the awaiting board card, further include：
Obtain test result；
The test result and described No. SN are bound, and preserved to data server.
11. method as claimed in claim 10, which is characterized in that after test result is obtained, further include：
Corresponding result label is sticked for the awaiting board card according to the test result.
12. a kind of board test device, which is characterized in that including：
First acquisition module, for obtaining awaiting board card No. SN；
Second acquisition module, for obtaining the first data and the second data that the awaiting board card is pre-stored；
Authentication module, for being verified using first data and second data to described No. SN；
Test module, for when being verified, testing the awaiting board card.
13. device as claimed in claim 12, which is characterized in that the authentication module, including：
First authentication unit calculates described No. SN for being based on the first Encryption Algorithm, to generate the first result；
Second authentication unit calculates described No. SN for being based on the second Encryption Algorithm, to generate the second result；
Determination unit, it is consistent with first data for working as first result, and second result and the described second number
According to it is consistent when, determine that described No. SN is verified.
14. device as claimed in claim 12, which is characterized in that first acquisition module is used for：
No. SN be printed on by the scanning of board code reader in the awaiting board card, to obtain described No. SN.
15. device as claimed in claim 12, which is characterized in that further include：
Burning module, for before the first data and the second data that the awaiting board card is pre-stored are obtained, by described first
In data and second data recording to the SN memories of the awaiting board card.
16. device as claimed in claim 15, which is characterized in that the awaiting board card is dual-CPU architecture, and each CPU is right
A SN memory is answered, the burning module is used for：
It will be in first data recording to the corresponding first SN memories of the first CPU；
It will be in second data recording to the corresponding 2nd SN memories of the 2nd CPU.
17. device as claimed in claim 16, which is characterized in that the burning module is used for：
No. SN of the awaiting board card is obtained, and first data are generated based on the first Encryption Algorithm；
It will be in first data recording to the first SN memories.
18. device as claimed in claim 16, which is characterized in that the burning module is used for：
No. SN of the awaiting board card is obtained, and second data are generated based on the second Encryption Algorithm；
It will be in second data recording to the 2nd SN memories.
19. such as claim 12-18 any one of them devices, which is characterized in that No. SN of the awaiting board card is by board class
Type, hardware version and board ID number compositions.
20. device as claimed in claim 13, which is characterized in that first Encryption Algorithm and the second Encryption Algorithm packet
One kind in MD5, RSA, DES, 3DES, AES and ECC is included, and first Encryption Algorithm is with second Encryption Algorithm
Different Encryption Algorithm.
21. device as claimed in claim 12, which is characterized in that further include：
Third acquisition module, for after testing the awaiting board card, obtaining test result；
Preserving module for the test result and described No. SN to be bound, and is preserved to data server.
22. device as claimed in claim 21, which is characterized in that further include：
Processing module for after test result is obtained, is sticked according to the test result for the awaiting board card corresponding
As a result label.
23. a kind of board, which is characterized in that including：
No. SN is printed on the board；
The board is dual-CPU architecture, including the first CPU and the 2nd CPU,
Wherein, the first CPU, for being based on the first Encryption Algorithm, according to described No. SN the first data of generation；
2nd CPU, for being based on the second Encryption Algorithm, according to described No. SN the second data of generation；
First SN memories, it is corresponding with the first CPU, for preserving the first data of the first CPU generations；
2nd SN memories, it is corresponding with the 2nd CPU, for preserving the second data of the 2nd CPU generations, wherein, institute
The first data and second data are stated for being verified to described No. SN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611197609.8A CN108226744A (en) | 2016-12-22 | 2016-12-22 | Board test method, device and board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611197609.8A CN108226744A (en) | 2016-12-22 | 2016-12-22 | Board test method, device and board |
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| CN108226744A true CN108226744A (en) | 2018-06-29 |
Family
ID=62656073
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| Application Number | Title | Priority Date | Filing Date |
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| CN201611197609.8A Pending CN108226744A (en) | 2016-12-22 | 2016-12-22 | Board test method, device and board |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109783299A (en) * | 2018-12-03 | 2019-05-21 | 北京深思数盾科技股份有限公司 | A kind of production test method and apparatus for core board |
| CN111901186A (en) * | 2020-06-12 | 2020-11-06 | 苏州浪潮智能科技有限公司 | Low-speed signal board card testing device and method based on switch |
| CN112766433A (en) * | 2020-12-30 | 2021-05-07 | 重庆盛泰光电有限公司 | Automatic product tracing system |
| CN114325316A (en) * | 2021-12-24 | 2022-04-12 | 北京锐安科技有限公司 | Board card testing method and device, electronic equipment and storage medium |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001013211A (en) * | 1999-06-29 | 2001-01-19 | Ando Electric Co Ltd | Test burn-in board control method and burn-in testing system |
| CN101295001A (en) * | 2007-04-28 | 2008-10-29 | 平成科贸股份有限公司 | Printed circuit board detecting method and system thereof |
| CN101782615A (en) * | 2010-03-08 | 2010-07-21 | 福建捷联电子有限公司 | SFIF code pre-reading method for ICT testing station |
| CN101894285A (en) * | 2010-01-26 | 2010-11-24 | 珠海天威技术开发有限公司 | Radio frequency chip, consumable material container, data writing method and verifying method |
| CN103149527A (en) * | 2013-04-02 | 2013-06-12 | 精成科技电子(东莞)有限公司 | Printed circuit board (PCB) detecting device and corresponding method |
| CN103424683A (en) * | 2012-05-18 | 2013-12-04 | 鸿富锦精密工业（深圳）有限公司 | Mainboard test system and method |
| CN104181452A (en) * | 2013-05-22 | 2014-12-03 | 富泰华工业（深圳）有限公司 | Circuit board test system and method |
| CN104297665A (en) * | 2014-04-15 | 2015-01-21 | 苏佳宁 | ATE load board management assembly for chip quantity production test |
| CN104537299A (en) * | 2014-12-10 | 2015-04-22 | 深圳先进技术研究院 | Method and system for detecting electronic device, and related apparatuses |
-
2016
- 2016-12-22 CN CN201611197609.8A patent/CN108226744A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001013211A (en) * | 1999-06-29 | 2001-01-19 | Ando Electric Co Ltd | Test burn-in board control method and burn-in testing system |
| CN101295001A (en) * | 2007-04-28 | 2008-10-29 | 平成科贸股份有限公司 | Printed circuit board detecting method and system thereof |
| CN101894285A (en) * | 2010-01-26 | 2010-11-24 | 珠海天威技术开发有限公司 | Radio frequency chip, consumable material container, data writing method and verifying method |
| CN101782615A (en) * | 2010-03-08 | 2010-07-21 | 福建捷联电子有限公司 | SFIF code pre-reading method for ICT testing station |
| CN103424683A (en) * | 2012-05-18 | 2013-12-04 | 鸿富锦精密工业（深圳）有限公司 | Mainboard test system and method |
| CN103149527A (en) * | 2013-04-02 | 2013-06-12 | 精成科技电子(东莞)有限公司 | Printed circuit board (PCB) detecting device and corresponding method |
| CN104181452A (en) * | 2013-05-22 | 2014-12-03 | 富泰华工业（深圳）有限公司 | Circuit board test system and method |
| CN104297665A (en) * | 2014-04-15 | 2015-01-21 | 苏佳宁 | ATE load board management assembly for chip quantity production test |
| CN104537299A (en) * | 2014-12-10 | 2015-04-22 | 深圳先进技术研究院 | Method and system for detecting electronic device, and related apparatuses |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109783299A (en) * | 2018-12-03 | 2019-05-21 | 北京深思数盾科技股份有限公司 | A kind of production test method and apparatus for core board |
| CN111901186A (en) * | 2020-06-12 | 2020-11-06 | 苏州浪潮智能科技有限公司 | Low-speed signal board card testing device and method based on switch |
| CN111901186B (en) * | 2020-06-12 | 2022-07-08 | 苏州浪潮智能科技有限公司 | Low-speed signal board card testing device and method based on switch |
| CN112766433A (en) * | 2020-12-30 | 2021-05-07 | 重庆盛泰光电有限公司 | Automatic product tracing system |
| CN112766433B (en) * | 2020-12-30 | 2024-02-27 | 盛泰光电科技股份有限公司 | Automatic product tracing system |
| CN114325316A (en) * | 2021-12-24 | 2022-04-12 | 北京锐安科技有限公司 | Board card testing method and device, electronic equipment and storage medium |
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