CN108206919A - Pixel circuit and imaging system - Google Patents

Pixel circuit and imaging system Download PDF

Info

Publication number
CN108206919A
CN108206919A CN201711360109.6A CN201711360109A CN108206919A CN 108206919 A CN108206919 A CN 108206919A CN 201711360109 A CN201711360109 A CN 201711360109A CN 108206919 A CN108206919 A CN 108206919A
Authority
CN
China
Prior art keywords
coupled
row
signal
circuit
precharge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201711360109.6A
Other languages
Chinese (zh)
Other versions
CN108206919B (en
Inventor
王睿
代铁军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omnivision Technologies Inc
Original Assignee
Omnivision Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omnivision Technologies Inc filed Critical Omnivision Technologies Inc
Publication of CN108206919A publication Critical patent/CN108206919A/en
Application granted granted Critical
Publication of CN108206919B publication Critical patent/CN108206919B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/70—Circuitry for compensating brightness variation in the scene
    • H04N23/72—Combination of two or more compensation controls
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/70—Circuitry for compensating brightness variation in the scene
    • H04N23/73—Circuitry for compensating brightness variation in the scene by influencing the exposure time
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/58—Control of the dynamic range involving two or more exposures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/58—Control of the dynamic range involving two or more exposures
    • H04N25/581—Control of the dynamic range involving two or more exposures acquired simultaneously
    • H04N25/583—Control of the dynamic range involving two or more exposures acquired simultaneously with different integration times
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/58—Control of the dynamic range involving two or more exposures
    • H04N25/581—Control of the dynamic range involving two or more exposures acquired simultaneously
    • H04N25/585—Control of the dynamic range involving two or more exposures acquired simultaneously with pixels having different sensitivities within the sensor, e.g. fast or slow pixels or pixels having different sizes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/74—Circuitry for scanning or addressing the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/79—Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

Present application is related to a kind of pixel circuit and imaging system.Pixel circuit includes transfering transistor, and the transfering transistor is coupled between photodiode and floating diffusion region image charge being transferred to the floating diffusion region.Precharge shifted signal represents the row comprising the transfering transistor and the difference between what is read do not go together.The selection circuit is coupled to make a choice to control the transfering transistor between first and second transfer control signal.The selection circuit is coupled to enable signal output the first transfer control signal in response to precharge during the read operation do not gone together.The precharge enables signal and is generated in response to precharge shifted signal with exposing the comparison of value signal.The selection circuit is coupled to enable signal output the second transfer control signal in response to sampling during the read operation of the row comprising the transfering transistor.

Description

Pixel circuit and imaging system
Technical field
The present invention relates generally to imaging sensor, and more specifically, and the present invention relates to high dynamic range images sensings Device.
Background technology
Image capture apparatus includes imaging sensor and imaging len.Imaging len focus the light on imaging sensor with Image is formed, and imaging sensor converts the light to electric signal.Electric signal is output to host electronic system from image capture apparatus Other components.Electronic system can be such as mobile phone, computer, digital camera or medical treatment device.
As pixel circuit becomes smaller, it is desirable that imaging sensor is in big luminescent condition range (from light conditions to light Condition change) in operation become more to be difficult to realize.This service ability is generally referred to as having high dynamic range imaging, and (HDRI is replaced Generation ground only HDR).High dynamic range imaging is the feature that many applications are highly desirable to, such as (for example) automobile and machine regard Feel.In normal image acquisition equipment, pixel circuit needs multiple continuous exposures so that imaging sensor is exposed to low photoelectricity Both flat and high light levels are to realize HDR.Conventional complementary metal-oxide semiconductor (MOS) (CMOS) imaging sensor is due to limited trap Capacity and fixed time for exposure and be subjected to low-dynamic range.
Invention content
One embodiment of present application is related to a kind of pixel circuit, including：Photodiode, be adapted for into Penetrate light accumulation of image；Transfering transistor is coupled in the photodiode and is placed in floating in the first semiconductor layer Expanded between dynamic diffusion region with selectively will build up on the described image electric charge transfer in the photodiode to described float Dissipate area；And selection circuit, it is coupled to receive sampling enabling signal and precharge shifted signal, wherein the precharge offset Signal represents the transfering transistor row being contained therein and the difference between what is read do not go together, wherein the selection electricity Road is further coupled to the control terminal of the transfering transistor to make a choice between first and second transfer control signal To control the transfering transistor, wherein the selection circuit was coupled in the read operation phase do not gone together described in reading Between in response to precharge enable signal output it is described first transfer control signal, wherein it is described precharge enable signal in response to institute The comparison generation for being pre-charged shifted signal with exposing value signal is stated, and wherein described selection circuit is coupled in the transfer crystalline substance Signal output second transfer is enabled during the read operation of the row that body pipe is contained therein in response to the sampling to control Signal processed.
One embodiment of present application is related to a kind of imaging system, including：Pel array, it is multiple with being arranged into Multiple pixel circuits in capable and multiple row, wherein each of described pixel circuit includes：Photodiode is suitable for ringing It should be in incident light accumulation of image；Transfering transistor is coupled in the photodiode and is placed in the first semiconductor layer In floating diffusion region between selectively to will build up on the described image electric charge transfer in the photodiode to described Floating diffusion region；And selection circuit, it is coupled to receive sampling enabling signal and precharge shifted signal, wherein the preliminary filling Electric deflection signal represents the transfering transistor row being contained therein and the difference between what is read do not go together, wherein described Selection circuit is further coupled to the control terminal of the transfering transistor to be done between first and second transfer control signal Go out selection to control the transfering transistor, wherein the selection circuit is coupled in the reading do not gone together described in reading Signal output the first transfer control signal is enabled in response to precharge during operation, is rung wherein the precharge enables signal Shifted signal is pre-charged described in Ying Yu to generate, and wherein described selection circuit is coupled in institute with exposing the comparison of value signal During stating the read operation of the row that transfering transistor is contained therein signal output described the is enabled in response to the sampling Two transfer control signals；Control circuit is coupled to the pel array to control the operation of the pel array, wherein described Selection circuit is contained in the control circuit；And reading circuit, it is coupled to the pel array with from the multiple pixel Circuit reads image data.
Description of the drawings
Nonrestrictive and non-exhaustive embodiments of the invention is described with reference to schema, wherein similar reference numbers are referred to through each The similar component of kind view, unless specified otherwise.
Fig. 1 is the exploded view of an example of the stacked semiconductor devices chip of teaching according to the present invention, wherein in fact It is more in frame to be used in combination that the integrated circuit die of example imaging system includes the control circuit with row decoder and selection circuit The high dynamic range image sensor sense architecture of position spectrum assignment uses.
Fig. 2 is the circuit diagram of the example of a part for the circuit for the pixel circuit for showing teaching according to the present invention, described Pixel circuit is coupled to receive signal from row decoder so that the high dynamic range sense architecture that multidigit exposes in frame is used in combination It uses.
Fig. 3 is the circuit diagram of an example of the comparator for showing teaching according to the present invention, and the comparator may include In being coupled to receive what signal was used so that the high dynamic range sense architecture that multidigit in frame exposes is used in combination from row decoder In the circuit of pixel circuit.
Fig. 4 is the block diagram for the example imaging system for illustrating teaching according to the present invention, and the example imaging system includes tool There is the control circuit of row decoder and selection circuit, the control circuit is coupled to the high dynamic exposed using multidigit in frame The pel array of range image sensor sense architecture.
Fig. 5 is to illustrate being read, being precharged and not by preliminary filling in example imaging system for teaching according to the present invention The block diagram of the row of electricity, example imaging system include the combination high dynamic range image sensor sense architecture with the exposure factor 1 The row decoder and selection circuit used.
Fig. 6 is the block diagram for the example row decoder circuit with the exposure factor 1 for illustrating teaching according to the present invention, described Example row decoder circuit is used in combination the high dynamic range image sensor that multidigit exposes in frame and reads frame in imaging systems Structure uses.
Fig. 7 is to illustrate being read in another example of imaging system of teaching according to the present invention, be precharged and not The block diagram for the row being precharged, another example of example imaging system include the combination high dynamic range figure with the exposure factor 2 As what sensor sense architecture used includes row decoder and selection circuit.
Fig. 8 is the frame of another example for the row decoder circuit with the exposure factor 2 for illustrating teaching according to the present invention Figure, the row decoder circuit are used in combination the high dynamic range image sensor that multidigit exposes in frame and read in imaging systems Framework uses.
Corresponding reference character instruction is through the correspondence component of several views in all figures.Those skilled in the art answers Solution, the element for the sake of simple and is clear in definition graph, and it is not necessarily been drawn to scale element.For example, one in figure The size of a little elements can be exaggerated to help improve the understanding to various embodiments of the present invention relative to other elements.And And it for these the various embodiments for more understanding to aspect the present invention, is not depicted in usually useful in the embodiment of commericially feasible Or element that is necessary common but understanding well.
Specific embodiment
In the following description, numerous specific details are stated to provide the detailed understanding to the present invention.However, fields Those skilled in the art with detail it should be appreciated that without putting into practice the present invention.In other examples, many institute's weeks are not described in detail The material or method known are of the invention fuzzy to avoid making.
The reference of " one embodiment ", " embodiment ", " example " or " example " is meaned through this specification with The a particular feature, structure, or characteristic that embodiment or example are combined and describe is included at least one embodiment of the present invention. Therefore, occur through this specification in multiple places the phrase " in one embodiment ", " in embodiment ", " example " or " example " is not necessarily all referring to for identical embodiment or example.In addition, in one or more embodiments or example specific feature, Structure or characteristic is combined into any appropriate combination and/or sub-portfolio.Specific feature, structure or characteristic may be included in integrated Circuit, electronic circuit, combinational logic circuit or provide described function other appropriate components in.Additionally it should be appreciated that with Its schema provided together is for the purpose explained to one of ordinary skill in the art, and schema is painted not necessarily to scale System.
As will be discussed, the example description of teaching according to the present invention is in high dynamic range (HDR) imaging sensor Image sensor pixel circuit, it includes control circuit, with row decoder circuit to control exposure and from each pixel electricity Road reads HDR image data.As will be shown, it provides and may be programmed for height and the efficient row solution in spectrum assignment and sense architecture Code device circuit improves dynamic range performance to precharge shifted signal coding pixel to be used to mix joining technique.Various In example, pel array is placed in the chip detached with peripheral circuit, and two chips are engaged with using Pixel-level engagement Together.There are memories, are used to store each piece of exposure information in each pixel circuit or pixel circuit, the storage Device is immediately below the block of pixel circuit or pixel circuit.In various examples, across each individual pixel circuits of pel array Frame in may be programmed spectrum assignment through provide have multidigit resolution ratio, realize across pel array each pixel circuit it is optimal Operation.Compared with known HDR imaging solutions, encoded preliminary filling electric deflection can be used to believe for the example of teaching according to the present invention Number realize spectrum assignment in indivedual frames of each individual pixel circuits, this causes improved charge across pel array to integrate. Using the encoded precharge shifted signal of teaching according to the present invention such spectrum assignment and sensing technique reduce conducting wire and The number of associated metal line with eliminate read during to the needs of the combination of the multiframe of pixel circuit row or lower sampling, according to Teachings of the present invention this lead to high frame rate and high spatial resolution.
In order to illustrate Fig. 1 is a reality of the stacked semiconductor devices chip 102 and 104 of teaching according to the present invention The exploded view of example, the wherein integrated circuit die of example imaging system 100 include the control with row decoder and selection circuit Circuit is used so that the high dynamic range image sensor sense architecture of multidigit spectrum assignment in frame is used in combination.In various examples In, semiconductor device wafer 102 and 104 may include silicon or other suitable semiconductor materials.In the illustrated example, device is brilliant Piece 102 is top sensor chip, it includes with the pixel circuit 110A, 110B being placed in the first semiconductor layer 112, The pel array 106 of 110C etc..Teaching according to the present invention, device wafer 102 are stacked with device wafer 104, dress It puts chip 104 and includes corresponding support circuits 108, be placed in the second semiconductor layer 114 and engagement coupling is mixed by Pixel-level Pel array 106 is closed to support the operation of photon detection array 106.
As discussed in more detail below, teaching according to the present invention, in some instances, in the first semiconductor layer 112 Pixel circuit 110 includes the photodiode for being coupled to floating diffusion region by transfering transistor, is contained in the second semiconductor layer Correspondence support circuits 108 in 114 include the control circuit with row decoder and selection circuit, be coupled to not comprising Signal output coupling is enabled to the of transfering transistor in response to precharge during the read operation do not gone together of transfering transistor One transfer control signal, and selection circuit be coupled to during the read operation mutually gone together comprising transfering transistor in response to Sampling to transfering transistor enables signal output the second transfer control signal.In various examples, it is contained in support circuits 108 In selection circuit be coupled to receive encoded precharge shifted signal, and may include unexposed unit so that it is each indivedual Pixel, which can have, is stored in multidigit therein (for example, 4) exposure value.It is mutual that this unexposed unit can mix engagement by Pixel-level It is connected to the pixel circuit being placed in the first semiconductor layer.Unexposed unit can be implemented static RAM or its The memory of its suitable type.In addition, in various examples, unexposed unit can also be shared among the block of pixel circuit, example Such as the block of (for example) 8x8 pixel circuits.In addition, in various examples, teaching according to the present invention, because of precharging signal Precharge shifted signal is encoded into, so the number of necessary conducting wire substantially reduces, for example, being reduced to 4 from 11 conducting wires Conducting wire, the metal number of metal line are reduced.
It should be noted that for explanatory purposes, illustrating tool, there are two opened up in Fig. 1 of stacked semiconductor devices chip 102 and 104 The example image sensing system 100 shown.In other examples, it will be appreciated that teaching according to the present invention, for additional functionality, spy Sign and improved performance, image sensing system 100 may include more than two stacked semiconductor devices chips.
Fig. 2 is a circuit part for the pixel circuit 210 and associated support circuits for showing teaching according to the present invention The circuit diagram of example, associated support circuits are coupled to receive signal from row decoder so that multidigit exposure in frame is used in combination High dynamic range sense architecture uses.It should be noted that pixel circuit 210 can be the pixel circuit of the pel array 106 of Fig. 1 The example of one of 110A, 110B, 110C, and the element through similarly naming and numbering hereafter quoted is similar to institute above Description couples and works like that.It is shown in example as depicted, pixel circuit 210 is placed in the first semiconductor layer 212. Pixel circuit 210 includes the photodiode 216 being placed in the first semiconductor layer 212, adapted in response to incident light Accumulation of image.The transfering transistor 218 being placed in the first semiconductor layer 212 is coupled in photodiode 216 and placement With described in selectively will build up in photodiode 216 between floating diffusion region 220 in the first semiconductor layer 212 Image charge is transferred to floating diffusion region 220.
Continue illustrated example, reset transistor 222 is placed in the first semiconductor layer 212 and is coupled to floating diffusion Area 220 in response to reset RST signal selectively reset floating diffusion region 220.In instances, reset transistor is coupled in multiple Between position floating diffusion region RFD voltages and floating diffusion region 220.Amplifier transistor 224 is placed in the first semiconductor layer 212 And include the amplifier gate terminal for being coupled to floating diffusion region 220.In instances, amplifier transistor 224 is that source electrode follows Device coupled transistor, and with the drain terminal for being coupled to AVDD voltage and the warp for being coupled to provide amplifier transistor 224 Amplify the source terminal of output.Row selecting transistor 226 is placed in the first semiconductor layer 212 and is coupled in bit line 228 with putting Between big device transistor 224.In operation, row selecting transistor 226 is coupled in response to row selection signal RS output pixels The image data of circuit 210.
Teaching according to the present invention, selection circuit 232 are placed in the second semiconductor layer 214 and by the first semiconductor layer Between 212 and the second semiconductor layer 214 Pixel-level mixing engage 230 be coupled to the control terminal of transfering transistor 218 with It makes a choice to control transfering transistor 218 between first transfer signal PTX 242 and the second transfer control signal STX 244. Following article will be discussed in more detail, teaching according to the present invention, and selection circuit 232 can be the respective pixel for being coupled to pel array One of multiple selection circuits of circuit 210.In the example described in fig. 2, selection circuit 232 be coupled to transfer During the read operation of the different row of the row of the pel array that transistor 218 is contained therein signal is enabled in response to precharge The outputs of paddr_en 238 first transfer control signal PTX 242.Selection circuit 232 is also coupled in transfering transistor 218 During the read operation of pixel circuit in the mutually colleague for the pel array being contained therein signal is enabled in response to sampling The outputs of saddr_en 240 second transfer control signal STX 244.Therefore, teaching according to the present invention, the first transfer control letter Number PTX 242 can be used for independently being pre-charged pixel circuit 210 to control the exposure of pixel circuit 210, and use second turn It moves control signal STX 244 and reads not going together for pel array.Therefore, in the indivedual frames for realizing each individual pixel circuits 210 Spectrum assignment, this causes the improved charge across entire pel array to integrate the high dynamic to provide teaching according to the present invention Range image senses.
As shown in the example described in Fig. 2, selection circuit 232 includes：First switch S1 234 is coupled to respond Signal paddr_en 238, which is enabled, in precharge generates the first transfer control signal PTX 242；And second switch S2 236, warp Coupling generates the second transfer control signal STX 244 to enable signal saddr_en 240 in response to sampling.
Comparator circuit 248 is coupled to generate with exposing the comparison of value signal 253 in response to precharge shifted signal 250 Precharge enables signal paddr_en 238.As discussed in more detail below, in an example, it is pre-charged shifted signal 250 Be coupled to from row decoder circuit receive, and represent for precharge the current line comprising transfering transistor 218 with currently Difference between not the going together of the pel array read.In instances, exposure value signal 253 is stored in unexposed unit In EXPMEM 252.In an example, it is represented by the exposure value signal 253 being stored in unexposed unit EXPMEM 252 Exposure value is multidigit (for example, the 4) value received from auto-exposure control (AEC) circuit 254.Following article will be discussed in more detail It states, in an example, the exposure value being stored in unexposed unit EXPMEM 252 is generated for adjusting by pixel circuit 210 Image data exposure.In instances, the exposure value being stored in unexposed unit EXPMEM 252 represents exposure value signal Difference may one of exposure values.In an example, the exposure value being stored in unexposed unit EXPMEM 252 can The exposure of image data generated with the block adjusted by the pixel in the pel array comprising pixel circuit 210 is shared by the block of pixel Light, such as the 8x8 blocks of (for example) adjacent pixel.
Fig. 3 is the circuit diagram of an example of the comparator 348 for showing teaching according to the present invention, and the comparator can wrap It is used contained in being coupled to receive signal from row decoder with the high dynamic range sense architecture that multidigit in frame exposes is used in combination Pixel circuit circuit in.It should be noted that comparator 348 can be the example of one of the comparator 248 of Fig. 2, and hereafter draw Element through similarly naming and numbering, which is similar to, described above such to be coupled and works.In example as depicted Displaying, comparator 348 include multiple exclusive or (XOR) door 349A, 349B, 349C and 349D.In instances, multiple XOR gate 349A, Each of 349B, 349C and 349D are coupled to receive the correspondence position paddr_ofs of precharge shifted signal<0>350A、 paddr_ofs<1>350B、paddr_ofs<2>350C or paddr_ofs<3>The 350D and correspondence position EXPMEM for exposing value signal <0>353A、EXPMEM<1>353B、EXPMEM<2>353C or EXPMEM<3>353D.NAND gate 351 is coupled to multiple XOR gates The output of 349A, 349B, 349C and 349D, and the output of NAND gate 351 is coupled to generation precharge and enables signal paddr_ En 338 is coupled to control first switch S1 334 as illustrated.
It should be noted that the example described in Fig. 3 uses precharge shifted signal (paddr_ofs) and exposure with 4 positions Value signal (EXPMEM) illustrates.Thus, there are four XOR gates 349A, 349B, 349C and 349D.It will be appreciated that for solution Release 4 examples that purpose offer therewith illustrates, and in other examples, the number of the position of preliminary filling electric deflection and exposure value signal Mesh can be different from 4.
Fig. 4 is the block diagram for the example imaging system 400 for illustrating teaching according to the present invention, and example imaging system 400 includes Control circuit with row decoder and selection circuit is coupled to the high dynamic range images exposed using multidigit in frame The pel array 406 of sensor sense architecture.In the illustrated example, it should be understood that be contained in the pel array 406 of Fig. 4 Each of pixel circuit can be the example or Fig. 2 of pixel circuit 110A, 110B, 110C of the pel array 106 of Fig. 1 The example of pixel circuit 210, and the element through similarly naming and numbering hereafter quoted is similar to such coupling described above It closes and works.As shown in the example described in Fig. 4, teaching according to the present invention, control circuit 456 is coupled to pel array 406 to control the operation of pel array 406, is independently controlled in single frame in the pixel circuit in pel array 406 Each time for exposure.In instances, reading circuit 458 is coupled to pel array 406 with from the multiple of pel array 406 Pixel circuit reads image data.In an example, the image data read by reading circuit 458 is transferred to function logic 460.In the illustrated case, the pixel circuit of pel array 406 is placed in the first semiconductor layer 412, and control circuit 456th, reading circuit 458 and function logic 460 are placed in the second semiconductor layer 414.In instances, the first semiconductor layer 412 Chip solution is stacked and is coupled in a stacked with the second semiconductor layer 414.
In an example, reading circuit 458 may include amplifying circuit, analog/digital (ADC) conversion circuit or other.Function Logic 460 can simply store described image data or even by effect after application image (for example, cut out, rotate, eliminate it is red Eye, adjustment brightness, adjustment contrast or other) manipulate described image data.Pel array 406 can be implemented as front side-illuminated figure As sensor or backside illumination imaging sensor.As described, each pixel circuit be arranged to row in pel array 406 and To obtain the image data of personal, position or object in row, then, described image data can be used that personal, position or object is presented The image of body.
It is shown in example as depicted, control circuit 456 includes the number for being coupled to row decoder and selection circuit 431 Auto-exposure control (AEC) 454.In an example, teaching according to the present invention, AEC 454 are coupled to from reading circuit 458 reading image datas determine to be benefited in pel array 406 with the image data value based on the pixel circuit from former frame In precharge any individual pixel circuits and therefore the additional exposure time in a later frame with provide HDR imaging.Thus, according to Teachings of the present invention, AEC 454 are coupled to carry for the unexposed unit EXPMEM (for example, EXPMEM 252) in selection circuit Row decoder and selection circuit 431 are provided for corresponding exposure value, and by corresponding sample address saddr 439.
The example described in Fig. 4 illustrates the simplified example of row decoder circuit 431A, and row decoder circuit 431A can be represented It is contained in one of multiple row decoder circuits in control circuit 456.It is shown in example as depicted, row decoder electricity Road 431A includes decoder circuit 433A, is coupled to receive transmitting TX source signals 446 and sample address signal saddr 439 Signal saddr_en 440 is enabled to generate the second transfer control signal STX 444 and sample address as demonstrated.Row solution Code device circuit 431A also comprising adder/encoder circuit 435A, is also coupled to receive transmitting TX sources in an example Signal 446, and be coupled to precharge shifted signal paddr_ofs 450 be encoded and generated the first transfer control signal PTX 442.As will be described in more detail, in an example, the adder circuit of adder/encoder circuit 435A is that a+1 adds Musical instruments used in a Buddhist or Taoist mass, it includes row input and the row outputs (not shown in Fig. 4) equal to row input+1.In that example, adder circuit Row input be coupled to receive row output signal from the adder circuit of the previous row of pel array 406, and row output is through coupling It closes to generate row output signal, the row input for being coupled to the adder circuit of the next line by pel array 406 receives. In one example, adder circuit also comprising input is enabled, makes the value received in input selectively be incremented by.As retouch It is shown in the example painted, the first transfer control signal PTX 442 and the second transfer control signal STX 444, sample address signal Saddr 439 and precharge shifted signal paddr_ofs 450 are coupled to be received by corresponding selection circuit, such as (citing comes Say) selection circuit 232 shown in Fig. 2.
In the rolling shutter design example of operation, it is assumed that the row i of pel array 406 is read.Thus, the pixel of row i Transfering transistor in circuit is coupled to receive when the i that is expert at is read, transfering transistor is activated during read operation STX transfer control signals.In addition, row i+2(0-N)*MexpCan be coupled to be precharged, wherein N be greater than or equal to zero it is whole Number, and MexpIt is the exposure factor.Therefore, teaching according to the present invention, it is assumed that such as N=10 and exposure factor Mexp=1, it can be pre- It charges and receives PTX transfers control signal to provide the N+1 of the pel array 406 of additional exposure time for high dynamic range imaging Or 11 other rows are：Row i+20*Mexp, row i+21*Mexp, row i+22*Mexp..., row i+29*MexpAnd row i+210*Mexp.Change sentence For words, if the row of pel array 406 read is row i, then and when reading row i (wherein N=10, and expose the factor Mexp=1) the other rows for the pel array 406 that can be precharged be row i+1, i+2, i+4 ..., i+512 and i+1024.According to this The teaching of invention, this moment, other rows of pel array 406 are neither read nor are precharged.
In order to be better described, Fig. 5 is the pel array 506 in example imaging system for illustrating teaching according to the present invention The block diagram of the middle row for being read, being precharged and not being precharged, example imaging system, which includes, has exposure factor Mexp=1 The row decoder and selection circuit used with reference to high dynamic range image sensor sense architecture.It will be appreciated that the pel array of Fig. 5 506 can for Fig. 1 pel array 106 example or Fig. 4 pixel circuit 406 example, and hereafter quote through similarly ordering The element of name and number, which is similar to, described above such to be coupled and works.
In the example described in Figure 5, it is assumed that pel array 506 is coupled to read using rolling shutter operational design, The row saddr of wherein pel array 506 is the current line read.Thus, the transfer being contained in the pixel circuit of row saddr Transistor be coupled to transfering transistor be expert at saddr read operation during be activated when receive STX transfer control signal.
In the illustrated case, the exposure factor is Mexp=1.In addition, it is stored in being directed in unexposed unit EXPMEM The exposure intensity EM (or exposure value) of the row is binary code n, corresponds to exposure gradients：EM=bin (n).Thus, it deposits The binary code n for the exposure intensity EM being stored in unexposed unit EXPMEM is arranged to n=0.Therefore, EM is equal to 2n= 20=1.Therefore, next line, row saddr+20Or row saddr+1, use the precharge for being set to paddr_ofs=' 0000 ' Shifted signal is pre-charged, and exposure intensity EM=20=1 exposure gradients n=0.Therefore, it is contained in the pixel of row saddr+1 Transfering transistor in circuit be coupled to transfering transistor be expert at saddr read operation during be activated to be precharged In the case of receive PTX transfer control signal.
Similarly, the next line being precharged is row saddr+21Or row saddr+2, wherein binary code n=1, Corresponding to exposure intensity EM=21Or EM=2, and be pre-charged shifted signal and be set to paddr_ofs=' 0001 '.Thus, packet Transfering transistor in pixel circuit contained in row saddr+2 is coupled to be expert in transfering transistor the read operation of saddr Period receives PTX transfer control signals in the case of being activated to be precharged.
However, next line, row saddr+3 are neither read nor are precharged, this is inclined to invalid precharge using setting The precharge shifted signal of shifting signal value (such as paddr_ofs=' 1111 ') indicates.Thus, it is contained in row saddr+3's Transfering transistor in pixel circuit be expert at saddr read operation during be neither coupled to receive precharge PTX transfer control Signal processed does not read sample STX transfer control signals yet.
Instead, the next line being precharged is row saddr+22Or row saddr+4, wherein binary code n=2, Corresponding to exposure intensity EM=22Or EM=4, and be pre-charged shifted signal and be set to paddr_ofs=' 0010 '.Thus, packet Transfering transistor in pixel circuit contained in row saddr+4 is coupled to be expert in transfering transistor the read operation of saddr Period receives PTX transfer control signals in the case of being activated to be precharged.
However, next line, row saddr+5, row saddr+6 and row saddr+7, are neither read nor are precharged, this It is inclined using the precharge for these rows for being set to invalid precharge offset signal value (such as paddr_ofs=' 1111 ') Shifting signal indicates.Thus, the transfer being contained in the pixel circuit of every trade saddr+5, row saddr+6 and row saddr+7 is brilliant Body pipe be expert at saddr read operation during be neither coupled to receive precharge PTX transfers control signal nor read sample STX transfer control signals.
In the illustrated case, bottom line shown in Fig. 5 is coupled to be precharged.In instances, using two into Code n=3 setting rows saddr+2 processed3Or row saddr+8, correspond to exposure intensity EM=23Or EM=8, and preliminary filling electric deflection Signal is set to paddr_ofs=' 0011 '.Thus, the transfering transistor warp being contained in the pixel circuit of row saddr+8 Coupling with transfering transistor be expert at saddr read operation during be activated to be precharged in the case of receive PTX transfers Control signal.
Fig. 6 is to illustrate that having for teaching according to the present invention exposes factor Mexp=1 row decoder circuit 631 more in detail The block diagram of thin example, row decoder circuit 631 are used to read with the high dynamic range image sensor exposed using multidigit in frame Go out in the imaging system of framework.It will be appreciated that the row decoder circuit 631 of Fig. 6 can be the reality of the row decoder circuit 431A of Fig. 4 Example, and the element through similarly naming and number hereafter quoted such couple and works similar to described above.
It is shown in example as depicted, row decoder circuit 631 is arranged in multiple rows.Decoder is included per a line Circuit 633A to 633F, is coupled to respective adders circuit 635A to 635F, and adder circuit 635A to 635F is coupled to pair Answer encoder circuit 637A to 637F.As shown in example, each of adder circuit 635A to 635F is defeated comprising row Enter the a+1 adder circuits of Ri and row output Ro.It is every in adder circuit 635A to 635F in the example described in figure 6 One is coupled so that the value received at its corresponding line input Ri is incremented by, and exports and correspond at its corresponding line output Ro With.The row output Ro of each adder circuit 635A to 635F is coupled to the correspondence of the next line by row decoder circuit 631 The row input Ri of adder circuit 635A to 635F is received.In addition, the row output Ro of each adder circuit 635A to 635F is also It is coupled to be received by corresponding encoded device circuit 637A to the 637F mutually to go together of row decoder circuit 631.In addition, row decoder First adder circuit 635A in circuit 631 is coupled to receive the first row Ri signals 643, is existed by drift computer 641 Outside is calculated, and drift computer 641 is coupled to receive current reading row, as indicated by using current saddr 639.
In addition, following article will be shown in more detail, encoder circuit 637A to the 637F of row decision-making device circuit 631 is coupled to The corresponding precharge shifted signal paddr_ofs 650 of generation, represents corresponding line and what is currently read does not go together (as used Indicated by saddr 639) between difference, by adder circuit row output Ro represent value be 2 power in the case of row It can be precharged.It is not 2 power by the row output Ro of the adder circuit values represented, then capable not pre- if another aspect Charging, and therefore encoder circuit is coupled to the preliminary filling electric deflection letter that generation represents invalid precharge row (for example, ' 1111 ') Number paddr_ofs 650.
In the illustrated case, the current line read by the pel array for being coupled to row decoder circuit corresponds to decoding Device circuit 633B, adder circuit 635B and encoder circuit 637B.It is coupled in first adder circuit 635A from offset In the case that calculator 641 receives the first row Ri signals 643, the row output Ro values of adder circuit 635B are added by coming from first The chain of the intermediate adder circuit of adder circuit 635A adds up to Ro=0, indicates that particular row of pel array currently quilt It reads.In addition, it is coupled to the correspondence decoder electricity for receiving transfer TX source signals 646 and current sample address signal saddr639 Road 633B is coupled to generation sample control signal STX 644 and corresponding sample enables signal saddr_en 640 to read pixel The corresponding line of array.In addition, because it is coupled to pair of decoder circuit 633B, adder circuit 635B and encoder circuit 637B It should go and be read, and therefore not be precharged, so receiving the coding of the row output Ro values Ro=0 of adder circuit 635B The invalid precharge shifted signal 650 of device circuit 637B generations paddr_ofs=' 1111 ' and precharge control signal PTX The corresponding output of 642B is to indicate not to that traveling line precharge, as demonstrated.
However, as shown in Figure 6, the adder circuit 635C reception value Ri=0 of next line, and therefore, output valve Ro= 1, it is coupled to be received by encoder circuit 637C.Thus, the corresponding precharge control signal PTX of encoder circuit 637C outputs Effective precharge shifted signal 650 of 642C and paddr_ofs=' 0000 ' is to indicate into line precharge, as demonstrated.
The example described in continuation Fig. 6, the adder circuit 635D reception value Ri=1 of next line, and therefore, output valve Ro =2, it is coupled to be received by encoder circuit 637D.Thus, the corresponding precharge control signal of encoder circuit 637D outputs Effective precharge shifted signal 650 of PTX 642D and paddr_ofs=' 0001 ' are with to that traveling line precharge, such as institute's exhibition Show.
However, the adder circuit 635E reception value Ri=2 of next line, and therefore, output valve Ro=3 is coupled to It is received by encoder circuit 637E.Thus, the corresponding precharge control signal PTX 642E of encoder circuit 637E outputs and The invalid of paddr_ofs=' 1111 ' is pre-charged shifted signal 650 to indicate without being pre-charged, as demonstrated.
Continue discribed example, the adder circuit 635F in bottom line illustrated in fig. 6 is coupled to reception value Ri =2k- 1, and therefore output valve Ro=2k.Thus, the corresponding precharge control signal PTX642F of encoder circuit 637F outputs and (wherein Bin (k) represents that effective precharge shifted signal 650 of binary value k) is pre- to indicate to carry out to paddr_ofs=Bin (k) Charging, as demonstrated.For example, if adder circuit 635F receives signal Ri=7, then Ro=8, corresponding to 2 Power or 2k, wherein k=3.Therefore, teaching according to the present invention, in the illustrated case, precharge offset address paddr_ Ofs 650 is equal to Bin (k)=Bin (3), is equal to ' 0011 '.
Therefore, teaching according to the present invention ,+1 adder circuit 635A to 635F and encoder circuit 637A to 637F are used In generation precharge 650 signal of offset address in row decoder circuit 631.It will be appreciated that row decoder circuit 631 and+1 addition This design of device circuit 635A to 635F and encoder circuit 637A to 637F is independently of the number of the exposure gradients in pel array Mesh.In addition, replacing that for each exposure gradients N+1 decoder must be used, there are an adder circuit and encoder electricity Road, region independently of exposure gradients number, therefore its realize with less transistor, less metal connection simplification set Meter, and therefore use less gross area.Despite the presence of propagation delay to give birth to the chain of whole adder circuit 635A to 635F Ro values are exported, but row decoder circuit 631 can be operated with line frequency into its corresponding line, therefore this almost provides several microseconds The full row time calculate 650 values of precharge offset address paddr_ofs, the time is enough.
Fig. 7 is the block diagram of another example of teaching according to the present invention, illustrate imaging system pel array 706 it is another The row for being read, being precharged and not being precharged in one example, the imaging system, which includes, has exposure factor Mexp=2 The row decoder and selection circuit used with reference to high dynamic range image sensor sense architecture.It will be appreciated that the pel array of Fig. 5 706 can for Fig. 1 pel array 106 example or Fig. 4 pixel circuit 406 example, and hereafter quote through similarly ordering The element of name and number, which is similar to, described above such to be coupled and works.In addition, although the exposure factor is Mexp=2 rather than Mexp=1, it should be noted that in addition the example described in Fig. 7 shares many similar points with example illustrated in fig. 5.
For example, in the example described in the figure 7, it is also assumed that pel array 706 is coupled to set using rolling shutter operation Meter is read, and the row saddr of wherein pel array 706 is the current line read.Thus, it is contained in the pixel circuit of row saddr In transfering transistor be coupled to transfering transistor be expert at saddr read operation during be activated when receive STX transfer Control signal.
In the illustrated case, the row of pel array 706 being precharged is：Row saddr+2(0-N)*Mexp, wherein N tables Show the number of the possibility exposure gradients in imaging sensor, and be greater than or equal to zero integer.Therefore, in exposure factor Mexp In the case of=2, the row that can be precharged is：Row saddr+2(0)* 2, row saddr+2(1)* 2, row saddr+2(2)* 2, row saddr+2(3)* 2 ... etc., correspond to row saddr+2, row saddr+4, row saddr+8, row saddr+16 ... etc..Cause This, is later row saddr+2 by the first row being precharged in the row (saddr) read.Therefore, after the row read Next line (it is row saddr+1) be not precharged.Therefore, the precharge deviant paddr_ofs of row saddr+1 is set For invalid offset values ' 1111 '.
It can be in exposure factor MexpThe first row being pre-charged in the case of=2 is instead row saddr+2.For row saddr The binary code n of+2 exposure intensity EM being stored in unexposed unit EXPMEM is arranged to n=0.Therefore, EM is In 2n=20=1.Thus, therefore next line to be pre-charged is row saddr+20*MexpOr row saddr+2, and preliminary filling electric deflection Signal is arranged to paddr_ofs=' 0000 '.Therefore, the transfering transistor warp being contained in the pixel circuit of row saddr+2 Coupling with transfering transistor be expert at saddr read operation during be activated to be precharged in the case of receive PTX transfers Control signal.
However, next line, row saddr+3 are neither read nor are precharged, this is inclined to invalid precharge using setting The precharge shifted signal instruction of shifting signal value ' 1111 '.Thus, the transfer crystal being contained in the pixel circuit of row saddr+3 Pipe be expert at saddr read operation during be neither coupled to receive precharge PTX transfers control signal nor read sample STX Transfer control signal.
The next line that can be precharged is row saddr+21*MexpOr row saddr+4, wherein binary code n=1, it is right It should be in exposure intensity EM=21Or EM=2, and be pre-charged shifted signal and be set to paddr_ofs=' 0001 '.Thus, comprising Transfering transistor in the pixel circuit of row saddr+4 is coupled to be expert in transfering transistor read operation phase of saddr Between be activated to be precharged in the case of receive PTX transfer control signals.
However, next row, row saddr+5, row saddr+6 and row saddr+7, are neither read nor by preliminary filling Electricity, this is inclined using the precharge for these rows for being set to invalid precharge offset signal value paddr_ofs=' 1111 ' Shifting signal indicates.Thus, the transfer being contained in the pixel circuit of every trade saddr+5, row saddr+6 and row saddr+7 is brilliant Body pipe be expert at saddr read operation during be neither coupled to receive precharge PTX transfers control signal nor read sample STX transfer control signals.
The next line being precharged is row saddr+22Or row saddr+4, wherein binary code n=2, correspond to and expose Luminous intensity EM=22Or EM=4, and be pre-charged shifted signal and be set to paddr_ofs=' 0010 '.Thus, it is contained in row Transfering transistor in the pixel circuit of saddr+4 be coupled to transfering transistor be expert at saddr read operation during quilt PTX transfer control signals are received in the case of activating to be precharged.
Fig. 8 is to illustrate that having for teaching according to the present invention exposes factor Mexp=2 row decoder circuit 831 it is detailed The block diagram of example, row decoder circuit 831 can be used for reading with the high dynamic range image sensor exposed using multidigit in frame Go out in the imaging system of framework.It will be appreciated that the row decoder circuit 831 of Fig. 8 can be the another of the row decoder circuit 431A of Fig. 4 Example, and the element through similarly naming and numbering hereafter quoted is similar to and described above such couple and work.Separately Outside, although the exposure factor is Mexp=2 rather than Mexp=1, it should be noted that the example described in Fig. 8 in addition with reality illustrated in fig. 6 Example shares many similar points.
For example, in the example described in fig. 8, row decoder circuit 831 is arranged in multiple rows.Solution is included per a line Code device circuit 833A to 833F is coupled to respective adders circuit 835A to 835F, adder circuit 835A to 835F coupling To corresponding encoder circuit 837A to 837F.As shown in example, each of adder circuit 835A to 835F is to include The a+1 adder circuits of row input Ri and row output Ro.In the example described in fig. 8, in adder circuit 835A to 835F Each it is coupled so that the value that receives is incremented by its corresponding line input Ri, and export at its corresponding line output Ro places pair Ying He.The row output Ro of each adder circuit 835A to 835F is coupled to pair of the next line by row decoder circuit 831 The row input Ri of adder circuit 835A to 835F is answered to receive.In addition, the row output Ro of each adder circuit 835A to 835F It is also coupled to be received by corresponding encoded device circuit 837A to the 837F mutually to go together of row decoder circuit 831.In addition, row decoding First adder circuit 835A in device circuit 831 is coupled to receive the first row Ri signals 843, by drift computer 841 It is calculated in outside.In the illustrated example, drift computer 841 is coupled to receive current reading row, uses and works as Preceding saddr 839 is indicated.
Compared with the drift computer 641 of Fig. 6, the drift computer 841 of Fig. 8 is coupled to receive exposure factor signal Mexp845 and generation enable bus signals 847.In instances, in exposure factor MexpIn the case of=2, bus signals are enabled 847 generations ' 0101010101010 ... " can potentially be activated to carry out in every line after instruction current line saddr Precharge.Factor M is exposed whereinexpIn=3 example, ' 001001001001 ... will be generated by enabling bus signals 847 ", Indicate can be potentially activated with into line precharge every three rows after current line saddr.Factor M is exposed whereinexp=4 Example in, ' 000100010001 ... will be generated by enabling bus signals 847 ", after instruction current line saddr every four Row can be potentially activated with into line precharge, etc..
Also as demonstrated, adder circuit 835A to 835F and encoder circuit 837A to 837F is also defeated comprising corresponding enabling Enter En, be coupled to from drift computer 841 receive enable bus 847 with enable or deactivate corresponding adder circuit 835A to 835F and encoder circuit 837A to 837F.Therefore, teaching according to the present invention, in exposure factor Mexp=2 example and enabling Bus signals 847 are ' 010101010 ... " in the case of, the adder circuit 835A after the row (saddr) read is arrived 835F's and encoder circuit 837A to 837F can be activated or deactivating with into line precharge in every line.For example, and such as It is described in more detail below, for the row deactivated by enabling bus 847 comprising adder circuit 835C and encoder 837C, En =0, Ri=0, Ro=0 and paddr_ofs=' 1111 '.For comprising adder circuit 835D and encoder 837D by enabling The row that bus 847 enables, En=1, Ri=0, Ro=1 and paddr_ofs=' 0000 '.
As mentioned, encoder circuit 837A to the 837F of row decision-making device circuit 831 couples inclined to generate corresponding precharge Shifting signal paddr_ofs 850, represents corresponding line and the difference between what is currently read do not go together, and use can be by preliminary filling The row saddr 839 of electricity is indicated.For example, in an example, encoder circuit 837A to 837F address offset Δ ofs, It is the total address difference read between row (saddr) and the current line that can be precharged, and then divided by exposes factor Mexp.Then, By Δ ofs/Mexp4 codes are encoded into represent the precharge shifted signal paddr_ofs 850 for the row that can be precharged.It is special For fixed, as Δ ofs/MexpWhen being 2 power, output is by log2(Δofs/Mexp) it is converted into binary system.In other words, such as Fruit reads row saddr and by the binary logarithm of the address difference between the current line being precharged (that is, log2(Δ ofs)) divided by Expose factor MexpIt is greater than or equal to zero integer k, then precharge shifted signal 850 is set to preaddr_ofs= Bin(k).However, as Δ ofs/MexpBinary logarithm (that is, log2(Δofs/Mexp)) it is not greater than or equal to zero integer When, the output code of precharge shifted signal 850 is set to preaddr_ofs=' 1111 ', represents invalid precharge row.
In order to illustrate if it is M that evaluated row, which is saddr+2 and exposes the factor,exp=2, then Δ ofs=2, and Δ ofs/MexpQuotient be 1.0.Because log2(1.0) it is integer value k (that is, k=0), so row saddr+2 can be precharged, and pre- Charging shifted signal 850 is set to paddr_ofs=Bin (k)=' 0000 '.However, if current line is saddr, commented It is M that the row estimated, which is saddr+3 and exposes the factor,exp=2, then Δ ofs=3, and Δ ofs/MexpQuotient=1.5.Because log2 (1.5) it is not greater than or equal to zero integer value (that is, because 1.5 be not 2 power), row saddr+3 can not be precharged, And therefore precharge shifted signal 850 is set to paddr_ofs=' 1111 '.
Continue the example described in Fig. 8, the current line read is coupled to decoder circuit 833B, adder circuit The row of 835B and encoder circuit 837B.It is coupled to receive first from drift computer 841 in first adder circuit 835A In the case of row Ri signals 843, the row output Ro values of adder circuit 835B pass through in first adder circuit 835A Between the chain of adder circuit add up to Ro=0, that particular row of instruction pel array is currently read.It is in addition, coupled It is coupled to the correspondence decoder circuit 833B for receiving transfer TX source signals 846 and current sample address signal saddr 839 Generation sample control signal STX 844 and corresponding sample enable signal saddr_en 840 to read the corresponding line of pel array. In addition, because the correspondence row for being coupled to decoder circuit 833B, adder circuit 835B and encoder circuit 837B is read, and Therefore it is not being precharged, so the encoder circuit 837B for receiving the row output Ro values Ro=0 of adder circuit 835B is The invalid precharge shifted signal 850 of generation paddr_ofs=' 1111 ' and the PTX 842B of precharge control signal correspond to defeated Go out to indicate not to that traveling line precharge, as demonstrated.Also, it should be appreciated that adder circuit 835B and encoder circuit The corresponding terminal En that enables of 837B is coupled to receive ' 0 ' value from enabling bus 847 like that as demonstrated, also indicates and is about to not It is precharged, this also results in the invalid precharge shifted signal 850 of paddr_ofs=' 1111 ' and precharge control signal PTX The corresponding of 842B exports to indicate not to that traveling line precharge.
Similarly, as shown in Fig. 8, the adder circuit 835C of next line receives the enabling signal of En=0 and Ri=0, And therefore, output valve Ro=0 is coupled to be received by encoder circuit 837C, and encoder circuit 837C also receives En=0's Enable signal.Thus, encoder circuit 837C also export paddr_ofs=' 1111 ' invalid precharge shifted signal 850 and The corresponding of precharge control signal PTX 842C exports to indicate not to that traveling line precharge.
However, as summarized above, the adder circuit 835D of next line receives the enabling signal of En=1 and Ri=0, and Therefore, output valve Ro=1 is coupled to be received by encoder circuit 837D, and encoder circuit 837D also receives opening for En=1 Use signal.Thus, encoder circuit 837D also export paddr_ofs=' 0000 ' effective precharge shifted signal 850 (that is, Pass through log2(1.0) be converted into binary system) and the corresponding output of precharge control signal PTX 842D to indicate to advance to that Line precharge.
Continue discribed example, the adder circuit 835F in bottom line illustrated in fig. 8 is coupled to receive En =1 and Ri=2k-1- 1 enabling signal, and therefore, output valve Ro=2k-1, it is coupled to be received by encoder circuit 837F, Encoder circuit 837F also receives the enabling signal of En=1.Thus, encoder circuit 837F also exports paddr_ofs=Bin (k-1) effective precharge shifted signal 850 is (that is, pass through log2(k-1) it is converted into binary system) and precharge control signal PTX The corresponding output of 842F is with to that traveling line precharge.
Being described above for the example of the illustrated present invention, includes the content described in abstract of description, it is undesirable to be In detail or limit the invention to revealed precise forms.Although describe the tool of the present invention for illustrative purpose herein Body embodiment and example, but in the case of without departing substantially from the wider spirit and scope of the present invention, various equivalent modifications are possible.
In view of description in detail above, can make these modifications to the example of the present invention.It is used in the appended claims Term be not necessarily to be construed as limiting the invention to the specific embodiment disclosed in specification and claims.But institute Stating range will be indicated in the appended claims completely, the generally acknowledging principle that the claim should be explained according to the claim of foundation To explain.This specification and schema accordingly are regarded as illustrative and not restrictive.

Claims (34)

1. a kind of pixel circuit, including：
Photodiode is adapted for incident light accumulation of image；
Transfering transistor, be coupled in the photodiode between the floating diffusion region that is placed in the first semiconductor layer with Described image electric charge transfer in the photodiode selectively be will build up on to the floating diffusion region；And
Selection circuit is coupled to receive sampling enabling signal and precharge shifted signal, wherein the precharge offset letter The transfering transistor row being contained therein number is represented and the difference between what is read do not go together, wherein the selection circuit Be further coupled to the control terminal of the transfering transistor with first and second transfer control signal between make a choice with The transfering transistor is controlled,
Wherein described selection circuit is coupled to open in response to precharge during the read operation do not gone together described in reading Signal is controlled with signal output first transfer, wherein the precharge enables signal in response to the precharge shifted signal Comparison with exposing value signal generates, and
During wherein described selection circuit is coupled to the read operation of the row being contained therein in the transfering transistor Signal output the second transfer control signal is enabled in response to the sampling.
2. pixel circuit according to claim 1, wherein the pixel circuit is contained within being arranged to multiple rows and multiple One of multiple pixel circuits in the pel array of row.
3. pixel circuit according to claim 1, wherein the selection circuit includes：
First switch is coupled to enable signal generation the first transfer control signal in response to the precharge；
Second switch is coupled to enable signal generation the second transfer control signal in response to the sampling；
Comparison circuit is coupled to be pre-charged shifted signal and the exposure value signal described in comparison to generate the precharge Enable signal；And
Unexposed unit is coupled to store the exposure value signal.
4. pixel circuit according to claim 3, wherein the comparison circuit includes：
Multiple exclusive or XOR gates, wherein each of the multiple XOR gate is coupled to receive the precharge shifted signal Corresponding position and the correspondence position of the exposure value signal；And
NAND gate is coupled to the output of the multiple XOR gate, wherein the output of the NAND gate be coupled to generate it is described pre- Charging enables signal.
5. pixel circuit according to claim 4, further comprises automatic exposure control circuit, it is coupled to serve as reasons The exposure value signal generation different possible exposure values of the unexposed unit storage.
6. pixel circuit according to claim 1, further comprises row decoder circuit, it is coupled in response to sample This address signal generates the sampling and enables signal and the precharge enabling signal, wherein sample address signal expression will It is subjected to the current line of the read operation.
7. pixel circuit according to claim 6, wherein the row decoder circuit includes：
Decoder circuit is coupled to receive transmitting source signal and the sample address signal, wherein the decoder circuit It is coupled in response to the whether described transfering transistor of the current line for being subjected to the read operation is contained therein The row output sampling enables signal and the second transfer control signal；
Adder circuit has row input and row output, wherein the adder circuit is coupled so that the row input is passed Increase and exported with generating the row, wherein previous adder circuit of the row input coupling of the adder circuit to previous row Row output, and wherein described row output coupling to the further addition device circuit of next line row input；And
Encoder circuit is coupled to generate the preliminary filling electric deflection letter in response to the row output of the adder circuit Number and the first control signal.
8. pixel circuit according to claim 7, further comprises drift computer, it is coupled to receive the sample This address signal is coupled to be received by the row input of the first adder circuit in the first row to generate the first row value.
9. pixel circuit according to claim 8, wherein the encoder circuit is coupled to generate the precharge partially Shifting signal, the difference between representing the row that the transfering transistor is contained therein and not going together described in reading Different, the value represented by the row output of the adder circuit is 2 power, and wherein described encoder circuit is coupled to give birth to It is not the situation of 2 power in the described value that the row output by the adder circuit represents into precharge shifted signal It is lower to represent invalid precharge row value.
10. pixel circuit according to claim 8, wherein the drift computer be further coupled to receive exposure because Subsignal, wherein the drift computer is further coupled to enable signal in response to the exposure factor signal generation.
11. pixel circuit according to claim 10, wherein adder circuit are further coupled to from the offset meter It calculates device and receives the enabling signal, wherein the adder circuit is coupled so that the row input is conditionally incremented by with response It is transmitted in whether the enabling signal or the adder circuit are coupled to input the row in response to the enabling signal The row output is generated to row output.
12. pixel circuit according to claim 11, wherein the encoder circuit is coupled to generate the precharge Shifted signal, the row being contained therein in the transfering transistor and the difference between not going together described in reading Different sum divided by be to represent that the transfering transistor is contained in the case of 2 power by the value that the exposure factor signal represents The sum of the row therein and the difference between not going together described in reading divided by by the exposure factor table The binary logarithm for the described value shown, and wherein described encoder circuit is coupled to generate the precharge shifted signal, The row that is contained therein in the transfering transistor and the difference between not going together described in reading it is described total Number divided by be not to represent invalid precharge row value in the case of 2 power by the described value that the exposure factor signal represents.
13. pixel circuit according to claim 11, wherein the encoder circuit is further coupled to described in reception Signal is enabled, is not opened in encoder circuit described in the enabling signal designation wherein the encoder circuit is coupled to generation The precharge shifted signal of precharge row value in vain is represented in the case of.
14. pixel circuit according to claim 1, wherein the first control signal is preliminary filling electrotransfer control signal, And wherein second control signal is sample transfer control signal.
15. pixel circuit according to claim 1, wherein the photodiode, the transfering transistor and described floating Dynamic diffusion region is placed in the first semiconductor layer, and wherein described selection circuit is placed in the second semiconductor layer and is coupled to Pass through the terminal of transfering transistor described in the mixing Engagement Control between first and second described semiconductor layer.
16. pixel circuit according to claim 15, further comprises：
Reset transistor is placed in first semiconductor layer and is coupled to the floating diffusion region selectively to reset The floating diffusion region；
Amplifier transistor is placed in first semiconductor layer and with the amplifier for being coupled to the floating diffusion region Grid；And
Row selecting transistor, be positioned to be coupled in first semiconductor layer bit line and the amplifier transistor it Between.
17. pixel circuit according to claim 15, wherein first and second described semiconductor layer chip side in a stacked Case is stacked and is coupled.
18. a kind of imaging system, including：
Pel array has the multiple pixel circuits being arranged into multiple rows and multiple row, wherein in the pixel circuit Each includes：
Photodiode is adapted for incident light accumulation of image；
Transfering transistor, be coupled in the photodiode between the floating diffusion region that is placed in the first semiconductor layer with Described image electric charge transfer in the photodiode selectively be will build up on to the floating diffusion region；And
Selection circuit is coupled to receive sampling enabling signal and precharge shifted signal, wherein the precharge offset letter The transfering transistor row being contained therein number is represented and the difference between what is read do not go together, wherein the selection circuit Be further coupled to the control terminal of the transfering transistor with first and second transfer control signal between make a choice with The transfering transistor is controlled,
Wherein described selection circuit is coupled to open in response to precharge during the read operation do not gone together described in reading Signal is controlled with signal output first transfer, wherein the precharge enables signal in response to the precharge shifted signal It is generated with exposing the comparison of value signal, and
During wherein described selection circuit is coupled to the read operation of the row being contained therein in the transfering transistor Signal output the second transfer control signal is enabled in response to the sampling；
Control circuit is coupled to the pel array to control the operation of the pel array, wherein the selection circuit packet Contained in the control circuit；And
Reading circuit is coupled to the pel array to read image data from the multiple pixel circuit.
19. imaging system according to claim 18, further comprises function logic, it is coupled to the reading circuit To store the described image data read from the multiple pixel circuit.
20. imaging system according to claim 18, wherein the selection circuit includes：
First switch is coupled to enable signal generation the first transfer control signal in response to the precharge；
Second switch is coupled to enable signal generation the second transfer control signal in response to the sampling；
Comparison circuit is coupled to be pre-charged shifted signal and the exposure value signal described in comparison to generate the precharge Enable signal；And
Unexposed unit is coupled to store the exposure value signal.
21. imaging system according to claim 20, wherein the comparison circuit includes：
Multiple exclusive or XOR gates, wherein each of the multiple XOR gate is coupled to receive the precharge shifted signal Corresponding position and the correspondence position of the exposure value signal；And
NAND gate is coupled to the output of the multiple XOR gate, wherein the output of the NAND gate be coupled to generate it is described pre- Charging enables signal.
22. imaging system according to claim 20, wherein the control circuit further comprises auto-exposure control electricity Road is coupled to the possible exposure value of difference that generation can be stored by the unexposed unit.
23. imaging system according to claim 18, wherein the control circuit further comprises row decoder circuit, It is coupled to enable signal in response to the sample address signal generation sampling and the precharge enables signal, wherein the sample The current line that the expression of this address signal will be subjected to the read operation.
24. imaging system according to claim 23, wherein the row decoder circuit includes：
Decoder circuit is coupled to receive emitting voltage signal and the sample address signal, wherein the decoder is electric Whether it is that the transfering transistor is contained therein that road is coupled in response to will be subjected to the current line of the read operation The row output it is described sampling enable signal and it is described second transfer control signal；
Adder circuit has row input and row output, wherein the adder circuit is coupled so that the row input is passed Increase and exported with generating the row, wherein previous adder circuit of the row input coupling of the adder circuit to previous row Row output, and wherein described row output coupling to the further addition device circuit of next line row input；And
Encoder circuit is coupled to generate the preliminary filling electric deflection letter in response to the row output of the adder circuit Number and the first control signal.
25. imaging system according to claim 24, wherein the control circuit further comprises drift computer, warp Coupling generates the first row value to receive the sample address signal, is coupled to by the first adder circuit in the first row Row input receive.
26. imaging system according to claim 25, wherein the encoder circuit is coupled to generate the precharge Shifted signal, in the case where the binary logarithm of value represented by the output of the row of the adder circuit is 2 power The difference between representing the row that the transfering transistor is contained therein and not going together described in reading, and wherein The encoder circuit is coupled to generation precharge shifted signal, is represented being exported by the row of the adder circuit The binary logarithm of described value be not to represent invalid precharge row value in the case of 2 power.
27. imaging system according to claim 25, wherein the drift computer is further coupled to receive exposure Factor signal, wherein the drift computer is further coupled to enable signal in response to the exposure factor signal generation.
28. imaging system according to claim 27, wherein adder circuit are further coupled to from the offset meter It calculates device and receives the enabling signal, wherein the adder circuit is coupled so that the row input is conditionally incremented by with response It is transmitted in whether the enabling signal or the adder circuit are coupled to input the row in response to the enabling signal The row output is generated to row output.
29. imaging system according to claim 28, wherein the encoder circuit is coupled to generate the precharge Shifted signal, the row being contained therein in the transfering transistor and the difference between not going together described in reading Different sum divided by be to represent that the transfering transistor is contained in the case of 2 power by the value that the exposure factor signal represents The sum of the row therein and the difference between not going together described in reading divided by by the exposure factor table The binary logarithm for the described value shown, and wherein described encoder circuit is coupled to generate the precharge shifted signal, The row that is contained therein in the transfering transistor and the difference between not going together described in reading it is described total Number divided by be not to represent invalid precharge row value in the case of 2 power by the described value that the exposure factor signal represents.
30. imaging system according to claim 28, wherein the encoder circuit is further coupled to described in reception Signal is enabled, is not opened in encoder circuit described in the enabling signal designation wherein the encoder circuit is coupled to generation The precharge shifted signal of precharge row value in vain is represented in the case of.
31. imaging system according to claim 18, wherein the first control signal is preliminary filling electrotransfer control signal, And wherein second control signal is sample transfer control signal.
32. imaging system according to claim 28, wherein the photodiode, the transfering transistor and described floating Dynamic diffusion region is placed in the first semiconductor layer, and wherein described selection circuit is placed in the second semiconductor layer and is coupled to Pass through the terminal of transfering transistor described in the mixing Engagement Control between first and second described semiconductor layer.
33. imaging system according to claim 32, wherein each of described pixel circuit further includes：
Reset transistor is placed in first semiconductor layer and is coupled to the floating diffusion region selectively to reset The floating diffusion region；
Amplifier transistor is placed in first semiconductor layer and with the amplifier for being coupled to the floating diffusion region Grid；And
Row selecting transistor, be positioned to be coupled in first semiconductor layer bit line and the amplifier transistor it Between.
34. imaging system according to claim 32, wherein first and second described semiconductor layer chip side in a stacked Case is stacked and is coupled.
CN201711360109.6A 2016-12-20 2017-12-15 Pixel circuit and imaging system Active CN108206919B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/384,866 2016-12-20
US15/384,866 US9888185B1 (en) 2016-12-20 2016-12-20 Row decoder for high dynamic range image sensor using in-frame multi-bit exposure control

Publications (2)

Publication Number Publication Date
CN108206919A true CN108206919A (en) 2018-06-26
CN108206919B CN108206919B (en) 2020-05-01

Family

ID=61027373

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711360109.6A Active CN108206919B (en) 2016-12-20 2017-12-15 Pixel circuit and imaging system

Country Status (3)

Country Link
US (1) US9888185B1 (en)
CN (1) CN108206919B (en)
TW (1) TWI665917B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110827748A (en) * 2019-11-08 2020-02-21 深圳市德普微电子有限公司 Pre-charging circuit of LED display screen driving chip
CN111565047A (en) * 2019-02-13 2020-08-21 豪威科技股份有限公司 Comparator output circuit of single slope analog-to-digital converter

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3462731B1 (en) * 2017-09-29 2021-11-10 Canon Kabushiki Kaisha Imaging device, imaging system, and moving body
CN111083403B (en) * 2019-12-11 2021-07-06 中国电子科技集团公司第四十四研究所 On-chip multiplexing type pixel control circuit
CN114449187B (en) * 2020-11-06 2023-10-17 广州印芯半导体技术有限公司 Image sensor and image sensing method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1864240A (en) * 2003-08-07 2006-11-15 微米技术有限公司 Imager photo diode capacitor structure with reduced process variation sensitivity
US7397509B2 (en) * 2004-08-27 2008-07-08 Micron Technology, Inc. High dynamic range imager with a rolling shutter
CN102833495A (en) * 2012-08-16 2012-12-19 格科微电子（上海）有限公司 Highly-dynamic image sensor driving method
CN102881703A (en) * 2012-09-29 2013-01-16 上海中科高等研究院 Image sensor and preparation method thereof
CN104660925A (en) * 2013-11-21 2015-05-27 全视科技有限公司 High Dynamic Range Image Sensor Read Out Architecture
CN104733480A (en) * 2013-12-19 2015-06-24 全视科技有限公司 Image sensor pixel for use in high dynamic range image sensor

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW393854B (en) * 1998-08-21 2000-06-11 Elecvision Inc Pixel device for image sensor and the image sensing method of the same
US7190397B2 (en) 2002-08-16 2007-03-13 Micron Technology, Inc. CMOS imager decoder structure
KR100562489B1 (en) * 2002-11-11 2006-03-21 삼성전자주식회사 CMOS image sensor having row decoder capable of shutter timing control
US7858917B2 (en) * 2003-05-02 2010-12-28 Massachusetts Institute Of Technology Digital photon-counting geiger-mode avalanche photodiode solid-state monolithic intensity imaging focal-plane with scalable readout circuitry
US20080239111A1 (en) * 2007-03-26 2008-10-02 Micron Technology, Inc. Method and appratus for dark current compensation of imaging sensors
JP4978795B2 (en) * 2007-09-28 2012-07-18 ソニー株式会社 Solid-state imaging device, drive control method, and imaging device
EP2587794B1 (en) * 2008-04-07 2022-05-04 Cmosis NV Pixel and pixel array with global shutter
US8093541B2 (en) 2008-06-05 2012-01-10 Aptina Imaging Corporation Anti-blooming protection of pixels in a pixel array for multiple scaling modes
CN102646386B (en) * 2011-05-13 2014-08-06 京东方科技集团股份有限公司 Pixel unit circuit, pixel array, panel and panel driving method
US8896743B2 (en) 2011-06-08 2014-11-25 Omnivision Technologies, Inc. Enclosure for image capture systems with focusing capabilities
JP6112306B2 (en) * 2011-11-25 2017-04-12 パナソニックＩｐマネジメント株式会社 Solid-state imaging device and imaging device including the same
US8742311B2 (en) * 2012-02-27 2014-06-03 Omnivision Technologies, Inc. Enhanced pixel cell architecture for an image sensor having a direct output from a buried channel source follower transistor to a bit line
KR102245973B1 (en) * 2014-02-17 2021-04-29 삼성전자주식회사 Correlated double sampling circuit and image sensor including the same
CN104134427B (en) * 2014-08-06 2016-08-24 友达光电股份有限公司 Image element circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1864240A (en) * 2003-08-07 2006-11-15 微米技术有限公司 Imager photo diode capacitor structure with reduced process variation sensitivity
US7397509B2 (en) * 2004-08-27 2008-07-08 Micron Technology, Inc. High dynamic range imager with a rolling shutter
CN102833495A (en) * 2012-08-16 2012-12-19 格科微电子（上海）有限公司 Highly-dynamic image sensor driving method
CN102881703A (en) * 2012-09-29 2013-01-16 上海中科高等研究院 Image sensor and preparation method thereof
CN104660925A (en) * 2013-11-21 2015-05-27 全视科技有限公司 High Dynamic Range Image Sensor Read Out Architecture
CN104733480A (en) * 2013-12-19 2015-06-24 全视科技有限公司 Image sensor pixel for use in high dynamic range image sensor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111565047A (en) * 2019-02-13 2020-08-21 豪威科技股份有限公司 Comparator output circuit of single slope analog-to-digital converter
CN111565047B (en) * 2019-02-13 2021-08-31 豪威科技股份有限公司 Comparator output circuit of single slope analog-to-digital converter
CN110827748A (en) * 2019-11-08 2020-02-21 深圳市德普微电子有限公司 Pre-charging circuit of LED display screen driving chip

Also Published As

Publication number Publication date
US9888185B1 (en) 2018-02-06
TWI665917B (en) 2019-07-11
CN108206919B (en) 2020-05-01
TW201841495A (en) 2018-11-16

Similar Documents

Publication Publication Date Title
CN108206919A (en) Pixel circuit and imaging system
US11728355B2 (en) Imaging device and electronic device
US20230297822A1 (en) Imaging device, imaging module, electronic device, and imaging system
CN108270979B (en) High dynamic range pixel circuit and the picture system for using high dynamic range pixel circuit
JP7202297B2 (en) Imaging device and electronic equipment
Mishra et al. Image acquisition and techniques to perform image acquisition
KR20200032202A (en) Stacked light sensor assembly with pixel level interconnects
CN102460700B (en) Color filters for sub-diffraction limit sensors
CN102257810B (en) Image sensor with controllable transfer gate voltages
US20160014353A1 (en) Unit pixel of image sensor, image sensor, and computing system having the same
KR20140024707A (en) Image sensor and electronic device including the same
CN104488259A (en) Wide dynamic range using monochromatic sensor
US8420996B2 (en) Intensity estimation using binary sensor array with spatially varying thresholds
KR102081040B1 (en) Photodetector
CN104917942B (en) Image capture apparatus and image capture system
CN206835238U (en) Imaging sensor and imaging system
CN108234907A (en) Without image high dynamic range image sensor sense architecture is obscured using multidigit spectrum assignment in frame
TW201223273A (en) Image processing apparatus, image processing method, and image processing program
CN105935296B (en) A kind of pixel circuit, digital X-ray detection device and its detection method
US20170251135A1 (en) Imaging device and imaging method
CN106129072B (en) Stacked chips share pixel structure
CN107278329A (en) Pixel sensor cell and image capturing device
US9843756B2 (en) Imaging devices, arrays of pixels receiving photocharges in bulk of select transistor, and methods
CN115988303A (en) Image sensor circuit and image acquisition method
US6947077B1 (en) Fast and accurate adjustment of gain and exposure time for image sensors

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant