CN108198585B - Time sequence signal storage testing device and method based on data compression technology - Google Patents
Time sequence signal storage testing device and method based on data compression technology Download PDFInfo
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- CN108198585B CN108198585B CN201810026072.1A CN201810026072A CN108198585B CN 108198585 B CN108198585 B CN 108198585B CN 201810026072 A CN201810026072 A CN 201810026072A CN 108198585 B CN108198585 B CN 108198585B
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- 238000012360 testing method Methods 0.000 title claims abstract description 37
- 238000013144 data compression Methods 0.000 title claims abstract description 32
- 238000005516 engineering process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 title claims abstract description 14
- 230000000087 stabilizing effect Effects 0.000 claims description 15
- 238000005070 sampling Methods 0.000 claims description 13
- 238000001514 detection method Methods 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 claims description 3
- 230000009286 beneficial effect Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000013500 data storage Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 238000005474 detonation Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2273—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2275—Writing or programming circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
- G11C11/225—Auxiliary circuits
- G11C11/2293—Timing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/40—Response verification devices using compression techniques
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention belongs to the technical field of embedded storage test and data compression, and particularly discloses a time sequence signal storage test device and a method based on a data compression technology.
Description
Technical Field
The invention belongs to the technical field of embedded storage testing and data compression, and particularly discloses a time sequence signal storage testing device and method based on a data compression technology.
Background
During the firing of a projectile from a target, the missile-borne control system typically needs to send a series of actuation signals to effect the associated actions, such as: engine ignition signals, explosion bolt detonation signals, timing control signals, counter periodic signals and the like. In order to check whether the missile-borne control system gives corresponding signals at a specified time point, a missile-borne time sequence signal storage testing device is generally adopted to record the level characteristics of the time actuation signals, and after the hit target is recovered, the data in the reading device can be used as a basis for evaluating whether the missile-borne control works normally.
The existing missile-borne time series signal storage testing device generally samples the tested signal at a sampling rate which is 5-10 times that of the tested signal, then sequentially stores each sampling result into a memory, and reads the data in the memory after the target is bumped. Because the signal is not compressed in the data storage process, if the flight time of the bullet is too long or the frequency of the measured signal is high, the amount of data to be stored will be large, and a NAND FLASH mass storage is usually needed to store the collected data. However, the NAND FLASH memory may have a bad block randomly, and if the memory block storing the valid data segment stored in the memory is damaged during reading the data, a part of valid data may be lost, which may cause erroneous judgment on the test result.
Disclosure of Invention
The invention aims to solve the technical problem of providing a time sequence signal storage testing device and a method based on a data compression technology, which can effectively improve the reliability of the storage testing device and reduce the power consumption of the device.
The technical scheme for solving the technical problems is as follows:
a time series signal storage testing device based on data compression technology, comprising:
the photoelectric isolator is used for converting an input multichannel time series signal into a standard level digital signal;
the CPLD device is connected with the photoelectric isolator and is used for reading the high and low levels of the standard level digital signal and encoding the read high and low levels according to a data compression algorithm;
the ferroelectric memory is connected with the CPLD device and used for storing the encoded data;
and the data read-back module is connected with the CPLD device and used for transmitting the stored data to the upper computer, and the upper computer recovers and restores the time sequence signal and displays the time sequence signal.
The beneficial effects of the invention are as follows: aiming at the defects of the existing testing device, a data compression algorithm for time series signals is provided, and a time series signal storage testing device is designed based on the algorithm. The device can meet the requirement on the storage capacity by adopting the ferroelectric memory as a storage medium due to the adoption of a data compression algorithm, and the ferroelectric memory has the characteristics of high-speed reading and writing, ultralow power consumption, infinite writing and the like, does not generate bad blocks, and can effectively improve the reliability of the storage testing device and reduce the power consumption of the device.
On the basis of the technical scheme, the invention can be improved as follows.
Further, the data read-back module includes a voltage stabilizing chip U8, and a USB interface chip U12 and a USB interface P5 connected to the voltage stabilizing chip U8.
The beneficial effects of adopting the further scheme are as follows: can be hot plugged and pulled, and is convenient to use.
Further, the ferroelectric memory model is FM22L16.
The beneficial effects of adopting the further scheme are as follows: the test device has the characteristics of high-speed reading and writing, ultra-low power consumption, infinite writing and the like.
Further, the USB interface chip U12 adopts a FT245BM chip, and the voltage stabilizing chip U8 adopts an AIC117; the pin 2 of the USB interface P5 is connected with the pin 7 of the USB interface chip U12 through a resistor R11, and the resistor R11 is connected with the pin 5 of the USB interface chip U12 through a resistor R12; the pin 4 of the USB interface P5 is connected with the input end of the voltage stabilizing chip U8 through an inductor and is simultaneously connected with the pin 26 and the pin 13 of the USB interface chip U12; the output end of the voltage stabilizing chip U8 is connected with a pin 30 of the USB interface chip U12; the pin 1 of the USB interface P5 is grounded and is connected with the pin 4 of the USB interface P5 through a capacitor C16; pin 3 of USB interface P5 connects pin 8 of USB interface chip U12 through resistor R10.
The beneficial effects of adopting the further scheme are as follows: the FT245BM chip is a second-generation USB interface chip which is introduced by the FTDI company, and compared with other USB chips, a user does not need to consider the design of firmware and the writing of a driving program, so that the development period of USB peripheral products can be greatly shortened.
Further, the optoisolator employs a TLP521 optocoupler.
In addition, the invention also provides a time series signal storage testing method based on the data compression technology, which is based on the storage testing device and comprises the following steps:
(1) The photoelectric isolator converts the input multichannel time series signal into a standard level digital signal;
(2) The CPLD device reads the high and low levels of the standard level digital signal and encodes the read high and low levels according to a data compression algorithm;
(3) The ferroelectric memory stores the encoded data;
(4) And the data read-back module transmits the stored data to the upper computer, and the upper computer restores and displays the time sequence signal.
Further, the specific method of the step (2) is as follows:
when the CPLD receives the zero time trigger signal, sampling the time sequence signals of all channels;
the CPLD carries out edge jump detection on the time sequence signals of each channel at the sampling frequency of 10KHz, and writes the time corresponding to the jump time and the logic value of the signals into the ferroelectric memory; wherein the time of the transition instant is relative to the time of zero.
The beneficial effects of adopting the further scheme are as follows: by such a data compression method, the overhead of the storage capacity can be effectively reduced.
Further, the memory cells with addresses of 0x0000 and 0x0001 in the ferroelectric memory store total time, wherein 0x0000 is low in time, 0x0001 is high in time, and the rest sequentially occupy 3 memory cells each time a signal jumps.
Drawings
FIG. 1 is a block diagram of the apparatus of the present invention;
FIG. 2 is a diagram of the electrical channels of the interface of the data read-back module of the present invention;
FIG. 3 is a schematic diagram of data storage based on the data compression technique of the present invention.
Detailed Description
The principles and features of the present invention are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.
Aiming at the defects of the existing testing device, a data compression algorithm for time series signals is provided, and a time series signal storage testing device is designed based on the algorithm. The device can meet the requirement on the storage capacity by adopting the ferroelectric memory as a storage medium due to the adoption of a data compression algorithm, and the ferroelectric memory has the characteristics of high-speed reading and writing, ultralow power consumption, infinite writing and the like, does not generate bad blocks, and can effectively improve the reliability of the storage testing device and reduce the power consumption of the device.
As shown in fig. 1, the present invention discloses a time-series signal storage testing device based on a data compression technology, which comprises:
the photoelectric isolator is used for converting an input multichannel time series signal into a standard level digital signal;
the CPLD device is connected with the photoelectric isolator and is used for reading the high and low levels of the standard level digital signal and encoding the read high and low levels according to a data compression algorithm;
the ferroelectric memory is connected with the CPLD device and used for storing the encoded data; the ferroelectric memory is used as a memory module for storing the testing device, so that the testing device has the characteristics of high-speed reading and writing, ultra-low power consumption, infinite writing and the like.
And the data read-back module is connected with the CPLD device and used for transmitting the stored data to the upper computer, and the upper computer recovers and restores the time sequence signal and displays the time sequence signal.
The device adopts the scheme of CPLD+ferroelectric memory to design a time sequence signal storage testing device, and has the advantages of low power consumption, small volume, high reliability, long storage time and the like.
The time sequence signal is a series of actuating signals sent by the controller, the invention isolates the signals through optical coupling, converts the sequence signals into unified standard level digital quantity signals, the converted digital quantity signals can be directly connected with IO pins of the CPLD, and the signals can be sampled by utilizing IO ports without sampling the signals through an AD conversion chip, so that the storage width of the one-channel time sequence signal is 1bit.
The invention designs a data read-back module and upper computer read-back software, the data read-back module reads back the data stored in the testing device to the upper computer after the test is finished, and the upper computer can recover the original signal by analyzing the time of jump time and the logic value of the signal. In fig. 1, through an opto-isolator, the present invention selects a TLP521 optocoupler to convert a time-series signal into a standard level digital signal, and the converted digital signals are connected with an IO port of a CPLD. After the CPLD receives the zero time trigger signal, sampling of each channel signal is started, and data is stored in the ferroelectric memory according to the data storage mode provided by the invention. And after the test is finished, the data in the ferroelectric memory is read back to the upper computer through the data read-back module, and the upper computer recovers the signals and displays the signals.
FIG. 2 is a diagram of the electrical channels of the interface of the data read-back module of the device of the present invention. The data read-back module comprises a voltage stabilizing chip U8, and a USB interface chip U12 and a USB interface P5 which are connected with the voltage stabilizing chip U8. The USB interface chip U12 adopts a FT245BM chip, and the voltage stabilizing chip U8 adopts an AIC117; the pin 2 of the USB interface P5 is connected with the pin 7 of the USB interface chip U12 through a resistor R11, and the resistor R11 is connected with the pin 5 of the USB interface chip U12 through a resistor R12; the pin 4 of the USB interface P5 is connected with the input end of the voltage stabilizing chip U8 through an inductor and is simultaneously connected with the pin 26 and the pin 13 of the USB interface chip U12; the output end of the voltage stabilizing chip U8 is connected with a pin 30 of the USB interface chip U12; the pin 1 of the USB interface P5 is grounded and is connected with the pin 4 of the USB interface P5 through a capacitor C16; pin 3 of USB interface P5 connects pin 8 of USB interface chip U12 through resistor R10.
The read-back module is a bridge for data interaction between the PC and the acquisition and storage module, the PC can downwards send instructions through the module, and the acquisition and storage module executes corresponding operations according to the instructions or uploads data in the memory to the PC. The invention designs the read-back electric channel based on the FT245BM chip, the FT245BM chip is a second generation USB interface chip which is pushed out by the FTDI company, and compared with other USB chips, a user does not need to consider the design of firmware and the writing of a driving program, thereby greatly shortening the development period of USB peripheral products. After the upper computer reads back the data, decompression and restoration processing are carried out on the data according to the data compression rule.
The invention provides a time sequence signal storage testing method based on a data compression technology, which is based on the storage testing device and comprises the following steps:
(1) The photoelectric isolator converts the input multichannel time series signal into a standard level digital signal;
(2) The CPLD device reads the high and low levels of the standard level digital signal and encodes the read high and low levels according to a data compression algorithm; the specific process is as follows:
when the CPLD receives the zero time trigger signal, sampling the time sequence signals of all channels;
the CPLD carries out edge jump detection on the time sequence signals of each channel at the sampling frequency of 10KHz, and writes the time corresponding to the jump time and the logic value of the signals into the ferroelectric memory; wherein the time of the jump instant is the time relative to the zero instant;
(3) The ferroelectric memory stores the encoded data;
(4) And the data read-back module transmits the stored data to the upper computer, and the upper computer restores and displays the time sequence signal.
By such a data compression method, the storage capacity can be effectively saved.
As shown in fig. 3, the present invention will be described with respect to a 16-channel time-series signal, which is a coding scheme of data in a ferroelectric memory. The ferroelectric memory type selected by the invention is FM22L16, and the memory storage capacity is 256K multiplied by 16bit. When the CPLD receives the zero time trigger signal, the CPLD starts to work, and the storage units with addresses of 0x0000 and 0x0001 in the memory are used for storing the total time, wherein 0x0000 is the low order of time, 0x0001 is the high order of time, and according to the sampling frequency, 1 is added to the total time every 0.1ms, so that the total storable time is 42948 seconds. When any channel signal in the 16-channel signals jumps, the CPLD immediately stores the corresponding jump time and the value of the jump time into the ferroelectric memory: wherein the time of the jump time is relative to the time of the zero time, and the two storage units are used for storing; whereas the value of each digital quantity channel occupies 1bit, the value of 16 channels can be stored with one memory unit. Thus, each time there are signal jumps, 3 memory cells are occupied, and the chip ferroelectric memory can store 78000 jumps in total. If the existing method is used, the data is not compressed, and a storage capacity of 6.8GB is required to store the same amount of time. As can be seen by comparison, the data compression storage algorithm provided by the invention can save a large amount of storage space.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (6)
1. A time-series signal storage testing device based on a data compression technology, comprising:
the photoelectric isolator is used for converting an input multichannel time series signal into a standard level digital signal;
the CPLD device is connected with the photoelectric isolator; the CPLD device is used for reading the high and low levels of the standard level digital signal, and encoding the read high and low levels according to a data compression algorithm, and specifically comprises: when the CPLD receives the zero time trigger signal, sampling the time sequence signals of all channels; the CPLD carries out edge jump detection on the time sequence signals of each channel at the sampling frequency of 10KHz, and writes the time corresponding to the jump time and the logic value of the signals into the ferroelectric memory; wherein the time of the jump instant is the time relative to the zero instant; the memory cells with addresses of 0x0000 and 0x0001 in the ferroelectric memory store total time, wherein 0x0000 is low in time, 0x0001 is high in time, and the rest of the memory cells sequentially occupy 3 memory cells when each signal jumps;
the ferroelectric memory is connected with the CPLD device and used for storing the encoded data;
and the data read-back module is connected with the CPLD device and used for transmitting the stored data to the upper computer, and the upper computer recovers and restores the time sequence signal and displays the time sequence signal.
2. The device for testing time-series signal storage based on data compression technology according to claim 1, wherein the data read-back module comprises a voltage stabilizing chip U8, and a USB interface chip U12 and a USB interface P5 connected to the voltage stabilizing chip U8.
3. The time-series signal storage testing device based on the data compression technology according to claim 2, wherein the USB interface chip U12 adopts an FT245BM chip, and the voltage stabilizing chip U8 adopts an AIC117; the pin 2 of the USB interface P5 is connected with the pin 7 of the USB interface chip U12 through a resistor R11, and the resistor R11 is connected with the pin 5 of the USB interface chip U12 through a resistor R12; the pin 4 of the USB interface P5 is connected with the input end of the voltage stabilizing chip U8 through an inductor and is simultaneously connected with the pin 26 and the pin 13 of the USB interface chip U12; the output end of the voltage stabilizing chip U8 is connected with a pin 30 of the USB interface chip U12; the pin 1 of the USB interface P5 is grounded and is connected with the pin 4 of the USB interface P5 through a capacitor C16; pin 3 of USB interface P5 connects pin 8 of USB interface chip U12 through resistor R10.
4. The data compression technology based time series signal storage testing device of claim 1, wherein the ferroelectric memory model is FM22L16.
5. The device for testing time-series signal storage based on data compression technology according to claim 1, wherein the optoisolator is a TLP521 optocoupler.
6. A time series signal storage testing method based on a data compression technique, characterized in that it is based on a storage testing device according to any one of claims 1 to 5, comprising the steps of:
(1) The photoelectric isolator converts the input multichannel time series signal into a standard level digital signal;
(2) The CPLD device reads the high and low levels of the standard level digital signal and encodes the read high and low levels according to a data compression algorithm;
(3) The ferroelectric memory stores the encoded data;
(4) The data read-back module transmits the stored data to the upper computer, and the upper computer restores and displays the time sequence signal;
the specific method of the step (2) is as follows:
when the CPLD receives the zero time trigger signal, sampling the time sequence signals of all channels;
the CPLD carries out edge jump detection on the time sequence signals of each channel at the sampling frequency of 10KHz, and writes the time corresponding to the jump time and the logic value of the signals into the ferroelectric memory; wherein the time of the jump instant is the time relative to the zero instant;
the memory cells with addresses of 0x0000 and 0x0001 in the ferroelectric memory store total time, wherein 0x0000 is low in time, 0x0001 is high in time, and the rest of the memory cells sequentially occupy 3 memory cells each time a signal jumps.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109684243A (en) * | 2019-02-21 | 2019-04-26 | 叶勇 | A kind of General Data Acquisition and signal processing system and its processing method |
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| JPH08314466A (en) * | 1996-06-14 | 1996-11-29 | Yamaha Corp | Compressing method of waveform data and digital data for musical sound control |
| CN101807214A (en) * | 2010-03-22 | 2010-08-18 | 湖南亿能电子科技有限公司 | High-speed signal acquisition, storage and playback device based on FPGA |
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