CN108182955B - Low-delay write priority decoding circuit - Google Patents

Low-delay write priority decoding circuit Download PDF

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CN108182955B
CN108182955B CN201810083424.7A CN201810083424A CN108182955B CN 108182955 B CN108182955 B CN 108182955B CN 201810083424 A CN201810083424 A CN 201810083424A CN 108182955 B CN108182955 B CN 108182955B
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word line
write word
input signal
line input
write
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CN108182955A (en
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李振涛
宋芳芳
刘尧
陈书明
郭阳
张秋萍
吕灵慧
宋婷婷
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National University of Defense Technology
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits

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Abstract

In order to eliminate write collision with more than 2 write ports, the invention provides a low-delay write priority decoding circuit. The decoding circuit has more than 2 write word line input signals and more than 2 write word line output signals with priority; all write word line input signals and write word line output signals are all high active; and giving the priority order of write word line input signals from high to low, wherein each write word line input signal corresponds to one write port, when more than 2 write word line input signals are simultaneously 1, only the write port corresponding to the write word line input signal with the highest priority executes write operation to the current row register, and the other write word line input signals with low priority are all shielded. The invention realizes the sequencing of the write operation according to the given write priority sequence, and the output of the decoder is only 1 at most, thereby eliminating the write conflict. Meanwhile, the decoding circuit has the advantages of low delay and area saving.

Description

Low-delay write priority decoding circuit
Technical Field
The invention belongs to the field of digital circuit design, and particularly relates to a method for realizing a multi-port register file writing decoding circuit.
Background
The decoding is to convert the binary code into specific One-Hot signal, and the decoding circuit can translate various states of the input binary code into corresponding output signals according to the original meaning. A logic circuit that converts an input binary code into a specific high (low) level signal for output is called a decoder.
The register file is a high-speed storage Unit inside a Central Processing Unit (CPU), is a special Static Random Access Memory (SRAM), and has the advantages of a large number of ports, high speed, small area, and the like. The register file is a core component of a CPU core data path, and provides source operands for functional components such as arithmetic logic and the like and stores operation results. The write decoding circuit is a key circuit of the register file and is used for compiling write addresses to generate write word line signals for controlling the writing of corresponding write data into the memory cells.
When a register file has write conflict, namely a plurality of write addresses write the same storage unit address, write competition occurs, and the write result has an uncertain state, so that a write priority ordering mechanism needs to be added to ensure that only a write word line translated by a write port with the highest priority is valid when write conflict occurs, and data on the write port is controlled to be written into the storage unit. The write priority logic is added in the decoding circuit, so that the logic level of the decoder is inevitably increased, and the decoding delay is increased, therefore, the design of low-delay priority decoding is an important technology of multi-port register file design.
Disclosure of Invention
For a register file with more than 2 write ports, each write word line signal corresponds to one write port, and when the write word line signal is 1, the write port corresponding to the write word line signal is indicated to execute a write operation to the current row register; when more than 2 write word line signals are all 1, it indicates that there are multiple write ports to write the register of the current row at this time, and a write conflict occurs, so that the value of the register of the current row enters an indeterminate state.
Aiming at a register file with 2 write ports, the invention provides a low-delay write priority decoding circuit in order to eliminate write conflict. The decoding circuit has 2 write word line input signals, which are w0 and w1 respectively; the decoding circuit has 2 write word line output signals, which are w0_ wl and w1_ wl respectively; all write word line input signals and write word line output signals are active high, the priority order of the write word line input signals is w0> w1 from high to low, each write word line input signal corresponds to one write port, when 2 write word line input signals are simultaneously 1, only the write port corresponding to the write word line input signal with the highest priority performs write operation to the current row register, and other write word line input signals with low priority are all shielded.
1) The write word line input signal w0 passes through the first buffer to generate a write word line output signal w0_ wl, which has a logic level of 2 levels of w0_ wl.
2) The write word line input signal w0 generates a signal w0_ bar through a first inverter; the signal w0_ bar and the write word line input signal w1 are connected to the input end of the first two-input nand gate, and output through the output end of the first two-input nand gate, and then pass through the second inverter to generate a write word line output signal w1_ wl.
When the write word line input signal w0 is 1, the write word line input signal w1 is masked off its corresponding output to always be 0; when the write word line input signal w0 is 0 and the write word line input signal w1 is 1, the write port corresponding to the write word line input signal w1 can perform a write operation to the current row register to output a write word line output signal w1_ wl; the write word line output signal w1_ wl has a logic level of 3 levels.
Aiming at a register file with 3 write ports, the invention provides a low-delay write priority decoding circuit in order to eliminate write conflict. The decoding circuit has 3 write word line input signals, which are w0, w1 and w2 respectively; the decoding circuit has 3 write word line output signals, which are w0_ wl, w1_ wl, and w2_ wl respectively; all write word line input signals and write word line output signals are high-effective, the priority order of the write word line input signals is w0> w1> w2 from high to low, each write word line input signal corresponds to one write port, when 2 or 3 write word line input signals are simultaneously 1, only the write port corresponding to the write word line input signal with the highest priority performs write operation to the current row register, and other write word line input signals with low priority are all shielded.
1) The write word line input signal w0 passes through the first buffer to generate a write word line output signal w0_ wl, which has a logic level of 2 levels of w0_ wl.
2) The write word line input signal w0 generates a signal w0_ bar through a first inverter, the signal w0_ bar and the write word line input signal w1 are connected to the input end of a first two-input NAND gate, and the write word line input signal w1_ wl is output through the output end of the first two-input NAND gate and then is generated into a write word line output signal w1_ wl through a second inverter;
when the write word line input signal w0 is 1, the write word line input signal w1 is masked off its corresponding output to always be 0; when the write word line input signal w0 is 0 and the write word line input signal w1 is 1, the write port corresponding to the write word line input signal w1 can perform a write operation to the current row register to output a write word line output signal w1_ wl; the write word line output signal w1_ wl has a logic level of 3 levels.
3) The write word line input signal w0 and the write word line input signal w1 generate a signal w01_ bar through a first two-input NOR gate; the signal w01_ bar and the write word line input signal w2 are connected to the input end of the second two-input nand gate, and the write word line output signal w2_ wl is generated through the third inverter after being output by the output end of the second two-input nand gate;
when the write word line input signal w0 or the write word line input signal w1 is 1, the write word line input signal w2 is masked and its corresponding output is always 0; when the write word line input signal w0 and the write word line input signal w1 are both 0, the write port corresponding to the write word line input signal w2 can perform a write operation to the current row register to output a write word line output signal w2_ wl, and the logic level of the write word line output signal w2_ wl is 3 levels.
Aiming at a register file with 4 write ports, the invention provides a low-delay write priority decoding circuit in order to eliminate write conflict. The decoding circuit has 4 write word line input signals which are w0, w1, w2 and w3 respectively; the decoding circuit has 4 write word line output signals, which are w0_ wl, w1_ wl, w2_ wl, and w3_ wl respectively; all write word line input signals and write word line output signals are high-effective, the priority order of the write word line input signals is w0> w1> w2> w3 from high to low, each write word line input signal corresponds to one write port, when 2, 3 or 4 write word line input signals are simultaneously 1, only the write port corresponding to the write word line input signal with the highest priority performs write operation to the current row register, and other write word line input signals with low priority are all shielded.
1) The write word line input signal w0 passes through the first buffer to generate a write word line output signal w0_ wl, which has a logic level of 2 levels of w0_ wl.
2) The write word line input signal w0 generates a signal w0_ bar through a first inverter, the signal w0_ bar and the write word line input signal w1 are connected to the input end of a first two-input NAND gate, and the write word line input signal w1_ wl is output through the output end of the first two-input NAND gate and then is generated into a write word line output signal w1_ wl through a second inverter;
when the write word line input signal w0 is 1, the write word line input signal w1 is masked off its corresponding output to always be 0; when the write word line input signal w0 is 0 and the write word line input signal w1 is 1, the write port corresponding to the write word line input signal w1 can perform a write operation to the current row register to output a write word line output signal w1_ wl, and the logic level of the write word line output signal w1_ wl is 3 levels.
3) The write word line input signal w0 and the write word line input signal w1 generate a signal w01_ bar through a first two-input NOR gate; the signal w01_ bar and the write word line input signal w2 are connected to the input end of the second two-input nand gate, and the write word line output signal w2_ wl is generated through the third inverter after being output by the output end of the second two-input nand gate;
when the write word line input signal w0 or the write word line input signal w1 is 1, the write word line input signal w2 is masked and its corresponding output is always 0; when the write word line input signal w0 and the write word line input signal w1 are both 0, the write port corresponding to the write word line input signal w2 can perform a write operation to the current row register to output a write word line output signal w2_ wl, and the logic level of the write word line output signal w2_ wl is 3 levels.
4) The write word line input signal w0, the write word line input signal w1 and the write word line input signal w2 are connected to the input end of the first three-input NOR gate, and the output signals are the signals w012_ bar; the signal w012_ bar and the write word line input signal w3 are connected to the third two-input nand gate, and the write word line output signal w3_ wl is generated through the fourth inverter after being output by the output end of the third two-input nand gate;
when one of the write word line input signal w0, the write word line input signal w1, and the write word line input signal w2 is 1, the write word line input signal w3 is masked off its corresponding output to always be 0; when the write word line input signal w0, the write word line input signal w1 and the write word line input signal w2 are all 0, the write port corresponding to the write word line input signal w3 is capable of performing a write operation to the current row register to output a write word line output signal w3_ wl, and the logic level of the write word line output signal w3_ wl is 3 levels.
Aiming at a register file with 5 write ports, the invention provides a low-delay write priority decoding circuit in order to eliminate write conflict. The decoding circuit has 5 write word line input signals which are w0, w1, w2, w3 and w4 respectively; the decoding circuit has 5 write word line output signals, which are w0_ wl, w1_ wl, w2_ wl, w3_ wl, and w4_ wl respectively; all write word line input signals and write word line output signals are high-effective, the priority order of the write word line input signals is w0> w1> w2> w3> w4 from high to low, each write word line input signal corresponds to one write port, when 2, 3, 4 or 5 write word line input signals are simultaneously 1, only the write port corresponding to the write word line input signal with the highest priority performs write operation to the current row register, and other write word line input signals with low priority are all shielded.
1) The write word line input signal w0 passes through the first buffer to generate a write word line output signal w0_ wl, which has a logic level of 2 levels of w0_ wl.
2) The write word line input signal w0 generates a signal w0_ bar through a first inverter, the signal w0_ bar and the write word line input signal w1 are connected to the input end of a first two-input NAND gate, and the write word line input signal w1_ wl is output through the output end of the first two-input NAND gate and then is generated into a write word line output signal w1_ wl through a second inverter;
when the write word line input signal w0 is 1, the write word line input signal w1 is masked off its corresponding output to always be 0; when the write word line input signal w0 is 0 and the write word line input signal w1 is 1, the write port corresponding to the write word line input signal w1 can perform a write operation to the current row register to output a write word line output signal w1_ wl, and the logic level of the write word line output signal w1_ wl is 3 levels.
3) The write word line input signal w0 and the write word line input signal w1 generate a signal w01_ bar through a first two-input NOR gate, the signal w01_ bar and the write word line input signal w2 are connected to the input end of the second two-input NAND gate, and the write word line output signal w2_ wl is generated through a third inverter after being output through the output end of the second two-input NAND gate;
when the write word line input signal w0 or the write word line input signal w1 is 1, the write word line input signal w2 is masked and its corresponding output is always 0; when the write word line input signal w0 and the write word line input signal w1 are both 0, the write port corresponding to the write word line input signal w2 can perform a write operation to the current row register to output a write word line output signal w2_ wl, and the logic level of the write word line output signal w2_ wl is 3 levels.
4) The write word line input signal w0, the write word line input signal w1 and the write word line input signal w2 are connected to the input end of the first three-input NOR gate, and the output signals are the signals w012_ bar; the signal w012_ bar and the write word line input signal w3 are connected to the third two-input nand gate, and the write word line output signal w3_ wl is generated through the fourth inverter after being output by the output end of the third two-input nand gate;
when one of the write word line input signal w0, the write word line input signal w1, and the write word line input signal w2 is 1, the write word line input signal w3 is masked off its corresponding output to always be 0; when the write word line input signal w0, the write word line input signal w1 and the write word line input signal w2 are all 0, the write port corresponding to the write word line input signal w3 is capable of performing a write operation to the current row register to output a write word line output signal w3_ wl, and the logic level of the write word line output signal w3_ wl is 3 levels.
5) The write word line input signal w3 generates a signal w3_ bar through a fifth inverter, the signals w012_ bar, w3_ bar and the write word line input signal w4 are connected to the input end of the first three-input nand gate, and the output end of the first three-input nand gate generates a write word line output signal w4_ wl through a sixth inverter;
when one of the write word line input signal w0, the write word line input signal w1, the write word line input signal w2 and the write word line input signal w3 is 1, the write word line input signal w4 is shielded and the corresponding output is always 0; when the write word line input signal w0, the write word line input signal w1, the write word line input signal w2 and the write word line input signal w3 are all 0, the write port corresponding to the write word line input signal w4 can perform a write operation to the current row register to output a write word line output signal w4_ wl, and the logic stage number of the write word line output signal w4_ wl is 3 stages.
Aiming at a register file with 6 write ports, the invention provides a low-delay write priority decoding circuit in order to eliminate write conflict. The decoding circuit has 6 write word line input signals which are w0, w1, w2, w3, w4 and w 5; the decoding circuit has 6 write word line output signals which are w0_ wl, w1_ wl, w2_ wl, w3_ wl, w4_ wl and w5_ wl respectively; all write word line input signals and write word line output signals are active high, the priority order of the write word line input signals is w0> w1> w2> w3> w4> w5 from high to low, each write word line input signal corresponds to one write port, when 2, 3, 4, 5 or 6 write word line input signals are simultaneously 1, only the write port corresponding to the write word line input signal with the highest priority performs write operation to the current row register, and other write word line input signals with low priority are all shielded.
1) The write word line input signal w0 passes through the first buffer to generate a write word line output signal w0_ wl, which has a logic level of 2 levels of w0_ wl.
2) The write word line input signal w0 generates a signal w0_ bar through a first inverter, the signal w0_ bar and the write word line input signal w1 are connected to the input end of a first two-input NAND gate, and the write word line input signal w1_ wl is output through the output end of the first two-input NAND gate and then is generated into a write word line output signal w1_ wl through a second inverter;
when the write word line input signal w0 is 1, the write word line input signal w1 is masked off its corresponding output to always be 0; when the write word line input signal w0 is 0 and the write word line input signal w1 is 1, the write port corresponding to the write word line input signal w1 can perform a write operation to the current row register to output a write word line output signal w1_ wl, and the logic level of the write word line output signal w1_ wl is 3 levels.
3) The write word line input signal w0 and the write word line input signal w1 generate a signal w01_ bar through a first two-input NOR gate, the signal w01_ bar and the write word line input signal w2 are connected to the input end of the second two-input NAND gate, and the write word line output signal w2_ wl is generated through a third inverter after being output through the output end of the second two-input NAND gate;
when the write word line input signal w0 or the write word line input signal w1 is 1, the write word line input signal w2 is masked and its corresponding output is always 0; when the write word line input signal w0 and the write word line input signal w1 are both 0, the write port corresponding to the write word line input signal w2 can perform a write operation to the current row register to output a write word line output signal w2_ wl, and the logic level of the write word line output signal w2_ wl is 3 levels.
4) The write word line input signal w0, the write word line input signal w1 and the write word line input signal w2 are connected to the input end of the first three-input NOR gate, and the output signals are the signals w012_ bar; the signal w012_ bar and the write word line input signal w3 are connected to the third two-input nand gate, and the write word line output signal w3_ wl is generated through the fourth inverter after being output by the output end of the third two-input nand gate;
when one of the write word line input signal w0, the write word line input signal w1, and the write word line input signal w2 is 1, the write word line input signal w3 is masked off its corresponding output to always be 0; when the write word line input signal w0, the write word line input signal w1 and the write word line input signal w2 are all 0, the write port corresponding to the write word line input signal w3 is capable of performing a write operation to the current row register to output a write word line output signal w3_ wl, and the logic level of the write word line output signal w3_ wl is 3 levels.
5) The write word line input signal w3 generates a signal w3_ bar through a fifth inverter, the signals w012_ bar, w3_ bar and the write word line input signal w4 are connected to the input end of the first three-input nand gate, and the output end of the first three-input nand gate generates a write word line output signal w4_ wl through a sixth inverter;
when one of the write word line input signal w0, the write word line input signal w1, the write word line input signal w2 and the write word line input signal w3 is 1, the write word line input signal w4 is shielded and the corresponding output is always 0; when the write word line input signal w0, the write word line input signal w1, the write word line input signal w2 and the write word line input signal w3 are all 0, the write port corresponding to the write word line input signal w4 can perform a write operation to the current row register to output a write word line output signal w4_ wl, and the logic stage number of the write word line output signal w4_ wl is 3 stages.
6) The write word line input signal w3 and the write word line input signal w4 are connected to the second two-input NOR gate, and the output is the signal w34_ bar; the signal w012_ bar, the signal w34_ bar and the write word line input signal w5 are connected to the input terminal of the second three-input nand gate, and the output of the second three-input nand gate generates the write word line output signal w5_ wl through the seventh inverter;
when one of the write word line input signal w0, the write word line input signal w1, the write word line input signal w2, the write word line input signal w3 and the write word line input signal w4 is 1, the write word line input signal w5 is shielded and the corresponding output is always 0; when the write word line input signal w0, the write word line input signal w1, the write word line input signal w2, the write word line input signal w3 and the write word line input signal w4 are all 0, the write port corresponding to the write word line input signal w5 can perform a write operation to the current row register to output a write word line output signal w5_ wl, and the logic stage of the write word line output signal w5_ wl is 3 stages.
The low-delay write priority decoding circuit provided by the invention realizes the sequencing of write operation according to the given write priority sequence, and the output of the decoder is only 1 at most, thereby eliminating write conflict. Meanwhile, the longest logic stage number of the decoder is 3 stages, and only 16 logic gates are used in common for a register file with 6 write ports, so that the decoder has the advantages of low delay and area saving.
The low-delay write priority decoding circuit provided by the invention can be suitable for the design of a decoder circuit with the number of write ports less than 6 through logic cutting.
Drawings
Fig. 1 is a block diagram of a decoding circuit with low delay priority (having 6 write ports).
Detailed Description
Fig. 1 is a block diagram of a low latency write priority decoder circuit according to the present invention, the decoder circuit has 6 write word line input signals, and the 6 write word line input signals are w0, w1, w2, w3, w4, and w 5. The decoding circuit has 6 write word line output signals w0_ wl, w1_ wl, w2_ wl, w3_ wl, w4_ wl, and w5_ wl, and all the input and output signals are high active.
1) The write word line input signal w0 passes through a first buffer to generate a write word line output signal w0_ wl.
2) The write word line input signal w0 generates a signal w0_ bar, a signal w0_ bar and a write word line input signal w1 through a first inverter, and the write word line input signal w1 is connected to the input end of the first two-input nand gate, and is output through the output end of the first two-input nand gate and then passes through a second inverter to generate a write word line output signal w1_ wl.
3) The write word line input signal w0 and the write word line input signal w1 pass through the first two-input nor gate to generate a signal w01_ bar, the signal w01_ bar and the write word line input signal w2 are connected to the input end of the second two-input nand gate, and pass through the third inverter after being output by the output end of the second two-input nand gate to generate a write word line output signal w2_ wl.
4) The write word line input signal w0, the write word line input signal w1 and the write word line input signal w2 are connected to the input end of the first three-input NOR gate, and the output signals are the signals w012_ bar; the w012_ bar and write word line input signal w3 are connected to the third two-input nand gate, and output through the output terminal of the third two-input nand gate, and then pass through the fourth inverter to generate a write word line output signal w3_ wl.
5) The write word line input signal w3 generates a signal w3_ bar through a fifth inverter, the signals w012_ bar, w3_ bar and the write word line input signal w4 are connected to the input terminal of the first three-input NAND gate, and the output terminal of the first three-input NAND gate generates a write word line output signal w4_ wl through a sixth inverter
6) The write word line input signal w3 and the write word line input signal w4 are connected to the second two-input NOR gate, and the output of the second two-input NOR gate is the signal w34_ bar; the w012_ bar, w34_ bar and write word line input signal w5 are connected to the input of the second three-input nand gate, and the output of the second three-input nand gate generates the write word line output signal w5_ wl through the seventh inverter.
The priority order of the write word line input signals is w0> w1> w2> w3> w4> w5 from high to low, and each write word line input signal corresponds to one write port; when 2, 3, 4 or 5 write word line input signals are simultaneously 1, only the write port corresponding to the write word line input signal with the highest priority performs the write operation to the current row register, and the other write word line input signals with the low priority are all shielded.
The write word line input signal w0 has the highest priority, i.e., the write port corresponding to the write word line input signal w0 has the highest priority.
When the write word line input signal w0 is asserted (i.e., when w0 is 1), the write word line input signal w0 goes high through the first buffer output w0_ wl, and the other output signals are all low.
When w0 is inactive (i.e. w0 is 0), w1 is active (i.e. w1 is 1), the write word line input signal w0 generates a signal w0_ bar through the first inverter, the inverted signal w0_ bar of w0 is high, the signal w0_ bar and the write word line input signal w1 are connected to the input terminal of the first two-input nand gate, the output signal w1_ wl is output through the output terminal of the first two-input nand gate and then passes through the second inverter, the write word line output signal w1_ wl is high, and the other output signals are low.
When w0 and w1 are both inactive (both 0) and w2 is active (both 1), the write word line input signal w0 and the write word line input signal w1 generate a signal w01_ bar through a first two-input nor gate, and the signal w01_ bar is high; the w01_ bar and write word line input signal w2 are connected to the input of the second two-input nand gate, and output through the output of the second two-input nand gate, and then pass through the third inverter to generate a write word line output signal w2_ wl, where w2_ wl is high and the other output signals are low.
When w0, w1 and w2 are inactive and w3 is active, the write word line input signal w0, the write word line input signal w1 and the write word line input signal w2 are connected to the input end of the first three-input nor gate, the output signal is w012_ bar, the signal w012_ bar is high level, the signal w012_ bar and the write word line input signal w3 are connected to the third two-input nand gate, and the write word line output signal w3_ wl is generated through the fourth inverter after being output from the output end of the third two-input nand gate, the w3_ wl is high level, and other output signals are all low level.
When w0, w1, w2, w3 are inactive and w4 are active, the write word line input signal w3 generates a signal w3_ bar through a fifth inverter, and the signal w3_ bar is high; w012_ bar is also high; the w012_ bar, w3_ bar and write word line input signal w4 are connected to the input of the first three-input nand gate, the output of which passes through the sixth inverter to generate a write word line output signal w4_ wl, w4_ wl is high, and the other output signals are all low.
When the w0, w1, w2, w3 and w4 signals are all inactive and the w5 signal is active, the write word line input signal w3 and the write word line input signal w4 are connected to the second two-input nor gate, the output thereof is the signal w34_ bar, and the signal w34_ bar is at high level; the w012_ bar, w34_ bar and write word line input signal w5 are connected to the input of the second three-input nand gate, the output of which passes through the seventh inverter to generate a write word line output signal w5_ wl, w5_ wl is high, and the other output signals are all low.
The invention uses the least units and logic levels to realize the function of priority decoding, solves the problem of writing conflict when a plurality of writing lines are effective, ensures that the output of a word line with low priority is 0 necessarily when the high priority is effective by each NOR gate, and ensures that the output signal of only one writing line with priority is at high level at any time.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and not only the register file of 6-write port, but also includes all multi-port register files with different capacity specifications, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to those skilled in the art may occur to persons skilled in the art without departing from the spirit and scope of the present invention.

Claims (5)

1. A low latency write priority decoding circuit, characterized by: the decoding circuit has 2 write word line input signals, which are w0 and w1 respectively; the decoding circuit has 2 write word line output signals, which are w0_ wl and w1_ wl respectively; all write word line input signals and write word line output signals are high-effective, the priority order of the write word line input signals is w0> w1 from high to low, each write word line input signal corresponds to one write port, when 2 write word line input signals are simultaneously 1, only the write port corresponding to the write word line input signal with the highest priority executes write operation to the current row register, and other write word line input signals with low priority are all shielded;
1) the write word line input signal w0 generates a write word line output signal w0_ wl through the first buffer, and the logic level of the write word line output signal w0_ wl is 2 levels;
2) the write word line input signal w0 generates a signal w0_ bar through a first inverter; the signal w0_ bar and the write word line input signal w1 are connected to the input end of the first two-input NAND gate, and output by the output end of the first two-input NAND gate and then pass through the second inverter to generate a write word line output signal w1_ wl;
when the write word line input signal w0 is 1, the write word line input signal w1 is masked and its corresponding output is always 0; when the write word line input signal w0 is 0 and the write word line input signal w1 is 1, the write port corresponding to the write word line input signal w1 can perform a write operation to the current row register to output a write word line output signal w1_ wl; the write word line output signal w1_ wl has a logic level of 3 levels.
2. A low latency write priority decoding circuit, characterized by: the decoding circuit has 3 write word line input signals, which are w0, w1 and w2 respectively; the decoding circuit has 3 write word line output signals, which are w0_ wl, w1_ wl, and w2_ wl respectively; all write word line input signals and write word line output signals are all high active; the priority order of the write word line input signals is w0> w1> w2 from high to low, and each write word line input signal corresponds to one write port; when 2 or 3 write word line input signals are simultaneously 1, only the write port corresponding to the write word line input signal with the highest priority executes write operation to the current row register, and the other write word line input signals with low priority are all shielded;
1) the write word line input signal w0 generates a write word line output signal w0_ wl through the first buffer, and the logic level of the write word line output signal w0_ wl is 2 levels;
2) the write word line input signal w0 generates a signal w0_ bar through a first inverter, the signal w0_ bar and the write word line input signal w1 are connected to the input end of a first two-input NAND gate, and the write word line input signal w1_ wl is output through the output end of the first two-input NAND gate and then is generated into a write word line output signal w1_ wl through a second inverter;
when the write word line input signal w0 is 1, the write word line input signal w1 is masked and its corresponding output is always 0; when the write word line input signal w0 is 0 and the write word line input signal w1 is 1, the write port corresponding to the write word line input signal w1 can perform a write operation to the current row register to output a write word line output signal w1_ wl; the logic level of the write word line output signal w1_ wl is 3 levels;
3) the write word line input signal w0 and the write word line input signal w1 generate a signal w01_ bar through a first two-input NOR gate; the signal w01_ bar and the write word line input signal w2 are connected to the input end of the second two-input nand gate, and the write word line output signal w2_ wl is generated through the third inverter after being output by the output end of the second two-input nand gate;
when the write word line input signal w0 or the write word line input signal w1 is 1, the write word line input signal w2 is masked and its corresponding output is always 0; when the write word line input signal w0 and the write word line input signal w1 are both 0, the write port corresponding to the write word line input signal w2 can perform a write operation to the current row register to output a write word line output signal w2_ wl, and the logic level of the write word line output signal w2_ wl is 3 levels.
3. A low latency write priority decoding circuit, characterized by: the decoding circuit has 4 write word line input signals which are w0, w1, w2 and w3 respectively; the decoding circuit has 4 write word line output signals, which are w0_ wl, w1_ wl, w2_ wl, and w3_ wl respectively; all the write word line input signals and the write word line output signals are high-effective, the priority order of the write word line input signals is w0> w1> w2> w3 from high to low, and each write word line input signal corresponds to one write port; when 2, 3 or 4 write word line input signals are simultaneously 1, only the write port corresponding to the write word line input signal with the highest priority executes write operation to the current row register, and the other write word line input signals with low priority are all shielded;
1) the write word line input signal w0 generates a write word line output signal w0_ wl through the first buffer, and the logic level of the write word line output signal w0_ wl is 2 levels;
2) the write word line input signal w0 generates a signal w0_ bar through a first inverter, the signal w0_ bar and the write word line input signal w1 are connected to the input end of a first two-input NAND gate, and the write word line input signal w1_ wl is output through the output end of the first two-input NAND gate and then is generated into a write word line output signal w1_ wl through a second inverter;
when the write word line input signal w0 is 1, the write word line input signal w1 is masked and its corresponding output is always 0; when the write word line input signal w0 is 0 and the write word line input signal w1 is 1, the write port corresponding to the write word line input signal w1 can perform a write operation to the current row register to output a write word line output signal w1_ wl, and the logic level of the write word line output signal w1_ wl is 3 levels;
3) the write word line input signal w0 and the write word line input signal w1 generate a signal w01_ bar through a first two-input NOR gate; the signal w01_ bar and the write word line input signal w2 are connected to the input end of the second two-input nand gate, and the write word line output signal w2_ wl is generated through the third inverter after being output by the output end of the second two-input nand gate;
when the write word line input signal w0 or the write word line input signal w1 is 1, the write word line input signal w2 is masked and its corresponding output is always 0; when the write word line input signal w0 and the write word line input signal w1 are both 0, the write port corresponding to the write word line input signal w2 can perform a write operation to the current row register to output a write word line output signal w2_ wl, and the logic level of the write word line output signal w2_ wl is 3 levels;
4) the write word line input signal w0, the write word line input signal w1 and the write word line input signal w2 are connected to the input end of the first three-input NOR gate, and the output signals are the signals w012_ bar; the signal w012_ bar and the write word line input signal w3 are connected to the third two-input nand gate, and the write word line output signal w3_ wl is generated through the fourth inverter after being output by the output end of the third two-input nand gate;
when one of the write word line input signal w0, the write word line input signal w1, and the write word line input signal w2 is 1, the write word line input signal w3 is masked and its corresponding output is always 0; when the write word line input signal w0, the write word line input signal w1 and the write word line input signal w2 are all 0, the write port corresponding to the write word line input signal w3 is capable of performing a write operation to the current row register to output a write word line output signal w3_ wl, and the logic level of the write word line output signal w3_ wl is 3 levels.
4. A low latency write priority decoding circuit, characterized by: the decoding circuit has 5 write word line input signals which are w0, w1, w2, w3 and w4 respectively; the decoding circuit has 5 write word line output signals, which are w0_ wl, w1_ wl, w2_ wl, w3_ wl, and w4_ wl respectively; all write word line input signals and write word line output signals are all high active; the priority order of the write word line input signals is w0> w1> w2> w3> w4 from high to low, and each write word line input signal corresponds to one write port; when 2, 3, 4 or 5 write word line input signals are simultaneously 1, only the write port corresponding to the write word line input signal with the highest priority executes write operation to the current row register, and the other write word line input signals with low priority are all shielded;
1) the write word line input signal w0 generates a write word line output signal w0_ wl through the first buffer, and the logic level of the write word line output signal w0_ wl is 2 levels;
2) the write word line input signal w0 generates a signal w0_ bar through a first inverter, the signal w0_ bar and the write word line input signal w1 are connected to the input end of a first two-input NAND gate, and the write word line input signal w1_ wl is output through the output end of the first two-input NAND gate and then is generated into a write word line output signal w1_ wl through a second inverter;
when the write word line input signal w0 is 1, the write word line input signal w1 is masked and its corresponding output is always 0; when the write word line input signal w0 is 0 and the write word line input signal w1 is 1, the write port corresponding to the write word line input signal w1 can perform a write operation to the current row register to output a write word line output signal w1_ wl, and the logic level of the write word line output signal w1_ wl is 3 levels;
3) the write word line input signal w0 and the write word line input signal w1 generate a signal w01_ bar through a first two-input NOR gate, the signal w01_ bar and the write word line input signal w2 are connected to the input end of the second two-input NAND gate, and the write word line output signal w2_ wl is generated through a third inverter after being output through the output end of the second two-input NAND gate;
when the write word line input signal w0 or the write word line input signal w1 is 1, the write word line input signal w2 is masked and its corresponding output is always 0; when the write word line input signal w0 and the write word line input signal w1 are both 0, the write port corresponding to the write word line input signal w2 can perform a write operation to the current row register to output a write word line output signal w2_ wl, and the logic level of the write word line output signal w2_ wl is 3 levels;
4) the write word line input signal w0, the write word line input signal w1 and the write word line input signal w2 are connected to the input end of the first three-input NOR gate, and the output signals are the signals w012_ bar; the signal w012_ bar and the write word line input signal w3 are connected to the third two-input nand gate, and the write word line output signal w3_ wl is generated through the fourth inverter after being output by the output end of the third two-input nand gate;
when one of the write word line input signal w0, the write word line input signal w1, and the write word line input signal w2 is 1, the write word line input signal w3 is masked and its corresponding output is always 0; when the write word line input signal w0, the write word line input signal w1 and the write word line input signal w2 are all 0, the write port corresponding to the write word line input signal w3 can perform a write operation to the current row register to output a write word line output signal w3_ wl, and the logic level of the write word line output signal w3_ wl is 3 levels;
5) the write word line input signal w3 generates a signal w3_ bar through a fifth inverter, the signals w012_ bar, w3_ bar and the write word line input signal w4 are connected to the input end of the first three-input nand gate, and the output end of the first three-input nand gate generates a write word line output signal w4_ wl through a sixth inverter;
when one of the write word line input signal w0, the write word line input signal w1, the write word line input signal w2 and the write word line input signal w3 is 1, the write word line input signal w4 is masked, and the corresponding output is always 0; when the write word line input signal w0, the write word line input signal w1, the write word line input signal w2 and the write word line input signal w3 are all 0, the write port corresponding to the write word line input signal w4 can perform a write operation to the current row register to output a write word line output signal w4_ wl, and the logic stage number of the write word line output signal w4_ wl is 3 stages.
5. A low latency write priority decoding circuit, characterized by: the decoding circuit has 6 write word line input signals which are w0, w1, w2, w3, w4 and w 5; the decoding circuit has 6 write word line output signals which are w0_ wl, w1_ wl, w2_ wl, w3_ wl, w4_ wl and w5_ wl respectively; all write word line input signals and write word line output signals are high-effective, the priority order of the write word line input signals is w0> w1> w2> w3> w4> w5 from high to low, and each write word line input signal corresponds to one write port; when 2, 3, 4, 5 or 6 write word line input signals are simultaneously 1, only the write port corresponding to the write word line input signal with the highest priority executes write operation to the current row register, and the other write word line input signals with low priority are all shielded;
1) the write word line input signal w0 generates a write word line output signal w0_ wl through the first buffer, and the logic level of the write word line output signal w0_ wl is 2 levels;
2) the write word line input signal w0 generates a signal w0_ bar through a first inverter, the signal w0_ bar and the write word line input signal w1 are connected to the input end of a first two-input NAND gate, and the write word line input signal w1_ wl is output through the output end of the first two-input NAND gate and then is generated into a write word line output signal w1_ wl through a second inverter;
when the write word line input signal w0 is 1, the write word line input signal w1 is masked and its corresponding output is always 0; when the write word line input signal w0 is 0 and the write word line input signal w1 is 1, the write port corresponding to the write word line input signal w1 can perform a write operation to the current row register to output a write word line output signal w1_ wl, and the logic level of the write word line output signal w1_ wl is 3 levels;
3) the write word line input signal w0 and the write word line input signal w1 generate a signal w01_ bar through a first two-input NOR gate, the signal w01_ bar and the write word line input signal w2 are connected to the input end of the second two-input NAND gate, and the write word line output signal w2_ wl is generated through a third inverter after being output through the output end of the second two-input NAND gate;
when the write word line input signal w0 or the write word line input signal w1 is 1, the write word line input signal w2 is masked and its corresponding output is always 0; when the write word line input signal w0 and the write word line input signal w1 are both 0, the write port corresponding to the write word line input signal w2 can perform a write operation to the current row register to output a write word line output signal w2_ wl, and the logic level of the write word line output signal w2_ wl is 3 levels;
4) the write word line input signal w0, the write word line input signal w1 and the write word line input signal w2 are connected to the input end of the first three-input NOR gate, and the output signals are the signals w012_ bar; the signal w012_ bar and the write word line input signal w3 are connected to the third two-input nand gate, and the write word line output signal w3_ wl is generated through the fourth inverter after being output by the output end of the third two-input nand gate;
when one of the write word line input signal w0, the write word line input signal w1, and the write word line input signal w2 is 1, the write word line input signal w3 is masked and its corresponding output is always 0; when the write word line input signal w0, the write word line input signal w1 and the write word line input signal w2 are all 0, the write port corresponding to the write word line input signal w3 can perform a write operation to the current row register to output a write word line output signal w3_ wl, and the logic level of the write word line output signal w3_ wl is 3 levels;
5) the write word line input signal w3 generates a signal w3_ bar through a fifth inverter, the signals w012_ bar, w3_ bar and the write word line input signal w4 are connected to the input end of the first three-input nand gate, and the output end of the first three-input nand gate generates a write word line output signal w4_ wl through a sixth inverter;
when one of the write word line input signal w0, the write word line input signal w1, the write word line input signal w2 and the write word line input signal w3 is 1, the write word line input signal w4 is masked, and the corresponding output is always 0; when the write word line input signal w0, the write word line input signal w1, the write word line input signal w2 and the write word line input signal w3 are all 0, the write port corresponding to the write word line input signal w4 can perform a write operation to the current row register to output a write word line output signal w4_ wl, and the logic stage number of the write word line output signal w4_ wl is 3 stages;
6) the write word line input signal w3 and the write word line input signal w4 are connected to the second two-input NOR gate, and the output is the signal w34_ bar; the signal w012_ bar, the signal w34_ bar and the write word line input signal w5 are connected to the input terminal of the second three-input nand gate, and the output of the second three-input nand gate generates the write word line output signal w5_ wl through the seventh inverter;
when one of the write word line input signal w0, the write word line input signal w1, the write word line input signal w2, the write word line input signal w3 and the write word line input signal w4 is 1, the write word line input signal w5 is masked, and the corresponding output is always 0; when the write word line input signal w0, the write word line input signal w1, the write word line input signal w2, the write word line input signal w3 and the write word line input signal w4 are all 0, the write port corresponding to the write word line input signal w5 can perform a write operation to the current row register to output a write word line output signal w5_ wl, and the logic stage of the write word line output signal w5_ wl is 3 stages.
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