CN108172578A - A kind of DRAM cell and its manufacturing method for reducing design area - Google Patents
A kind of DRAM cell and its manufacturing method for reducing design area Download PDFInfo
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- CN108172578A CN108172578A CN201711434312.3A CN201711434312A CN108172578A CN 108172578 A CN108172578 A CN 108172578A CN 201711434312 A CN201711434312 A CN 201711434312A CN 108172578 A CN108172578 A CN 108172578A
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- panel
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- bit line
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
Abstract
The present invention provides a kind of DRAM cells and its manufacturing method for reducing design area, applied to semiconductor storage manufacturing field, wherein, each DRAM cell includes a transistor, a capacitor, and the Transfer pipe between bit line and the capacitor is connected in the gate electrode of the transistor under the control of word line voltage；It is prepared per a pair of DRAM cell by following steps：In the panel that horizontal direction expansion is formed on semiconductor substrate；The gate electrode of a transistor is formed in the panel both sides；A precalculated position forms the bit line connector being electrically connected with bit line generation above the panel；The capacitor is formed in the side of the gate electrode, the capacitor is electrically connected with Transfer pipe generation；Advantageous effect：Reduce the design area of DRAM cell by way of shared panel and bit line connector.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of DRAM cells for reducing design area
And its manufacturing method.
Background technology
In general, dynamic RAM is made of a plurality of DRAM cells.It is at this point, a plurality of
One transistor (CTR) of each freedom of DRAM cell formed with capacitor.Capacitor can store charge,
Transistor (CTR) forms the Transfer pipe (TCH) that a basis is attached to the voltage of gate electrode and connects bit line and capacitor.
Meanwhile with the high aggregation of dynamic RAM, about the dynamic RAM list for reducing design area
The research of first (DRAM Cell) is carried out.Particularly ensuring a degree of cell transistor Transfer pipe length
In the case of, it reduces during the technology of design area energetically carries out.
Vertical-type filler with cell transistor is that these reduce one of technology of cell transistor design area.It gathers around
The cell transistor for having vertical-type filler can be under limited design area, and the transmission that can also embody required length is led to
Road.
But because each dynamic RAM needs one in this cell transistor for possessing vertical-type filler
A filler, so there are bottlenecks in the design area for reducing dynamic RAM.
Invention content
In view of the above-mentioned problems, the present invention provides a kind of manufacturers for the DRAM cell for reducing design area
Method, applied to semiconductor storage manufacturing field, wherein, each DRAM cell include a transistor,
One capacitor, the transmission that the gate electrode of the transistor is connected under the control of word line voltage between bit line and the capacitor are led to
Road；It is prepared per a pair of DRAM cell by following steps：
Step S1, in the panel that horizontal direction expansion is formed on semiconductor substrate；
Step S2 forms the gate electrode of a transistor in the panel both sides；
Step S3, a precalculated position forms the bit line connector being electrically connected with bit line generation above the panel；
Step S4 forms the capacitor in the side of the gate electrode, and the capacitor is generated with the Transfer pipe
Electrical connection.
Wherein, the method that the panel is formed in the step S1 includes the following steps：
Step S11 deposits one first oxide layer and one first insulating layer successively in the semiconductor substrate surface；
Step S12 deposits one first mask layer in first surface of insulating layer, patterns first mask layer, in
One precalculated position formation process window；
Step S13, by first mask layer to first insulating layer, first oxide layer and the semiconductor
Substrate performs etching, and stays in a predetermined depth in the semiconductor substrate, forms splitter box；
Step S14 removes first mask layer, and one second mask layer, pattern are formed in first surface of insulating layer
Change second mask layer, in a precalculated position formation process window；
Step S15, by second mask layer to first insulating layer, first oxide layer and the semiconductor
Substrate performs etching, and stays in a predetermined depth in the semiconductor substrate, forms the panel；
Wherein, the method that gate electrode is formed in the step S2 includes the following steps：
Step S21 removes second mask layer, and ion note is carried out to the semiconductor substrate and the panel surface
Enter, form the Transfer pipe；
Step S22 forms one second oxide layer and one first conducting shell in the semiconductor substrate and the panel surface；
Step S23 performs etching first conducting shell, forms the gate electrode；
Wherein, the method for forming the bit line connector includes the following steps：
Step S31 forms a third oxide layer in the surface gate electrode, the second oxidation layer surface；
Step S32 planarizes the third oxide layer, stays in first surface of insulating layer；
Step S33 removes first insulating layer and first oxide layer, forms a groove structure；
Step S34, in the 4th oxide layer of groove structure disposed on sidewalls 1；
Step S35, in one second conducting shell of the 4th oxide layer surface deposition；
Step S36 planarizes second conducting shell, stays in the third oxidation layer surface, forms the bit line and connect
Interface；
Wherein, the method that capacitor is formed in the step S4 includes the following steps：
Step S41 forms a second insulating layer, a third in the bitline plug surface and third oxidation layer surface
Mask layer patterns the third mask layer, in a precalculated position formation process window；
Step S42 performs etching the second insulating layer by the third mask layer, perforation second insulation
Layer, the third oxide layer and second oxide layer, stop to the semiconductor substrate surface；
Step S43 deposits one second conducting shell above the semiconductor base；
Step S44 planarizes second conducting shell, until exposing the second insulating layer, forms capacitor connector；
Step S45 forms the capacitor above the capacitor connector.
Wherein, the Transfer pipe is higher than the semiconductor substrate.
Wherein, described gate electrode at least part is silicified.
Wherein, described gate electrode at least part is made of tungsten or titanium.
Wherein, the Transfer pipe includes the ingredient of vertical direction and the ingredient of horizontal direction.
A kind of DRAM cell for reducing design area, including：
One silicon base is formed with a panel in the silicon base；
One splitter box is set to inside the silicon base；
One bit line connector is set to above the panel, is connected with a bit line；
Transfer pipe is covered in the silicon substrate surface and the panel both sides；
Gate electrode is set on the Transfer pipe of the silicon base and the panel angle；
Capacitor is set to above the silicon base, is connected by capacitor connector with the Transfer pipe.
Advantageous effect：The present invention can effectively reduce the design area of DRAM cell.
Description of the drawings
The structure diagram of Fig. 1 embodiment of the present invention；
Fig. 2 is the sectional view of Figure 1A-A '；
The equivalent circuit diagram of Fig. 3 DRAM cells of the present invention；
Fig. 4 flow charts of the present invention；
Structure diagram in each step of Fig. 5 a~5i present invention.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art obtained under the premise of creative work is not made it is all its
His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The invention will be further described in the following with reference to the drawings and specific embodiments, but not as limiting to the invention.
In a preferred embodiment, as shown in Figure 4, it is proposed that a kind of dynamic RAM for reducing design area
The manufacturing method of unit, applied to semiconductor storage manufacturing field, wherein, each DRAM cell packet
A transistor (CTR), a capacitor (STG) are included, the gate electrode (EGT) of the transistor is led under the control of wordline (WL) voltage
Logical Transfer pipe (TCH) between bit line (BL) and the capacitor；Per a pair of DRAM cell by with
It is prepared by lower step：
Step S1, in the panel 150 that horizontal direction expansion is formed on semiconductor substrate；
Step S2 forms the gate electrode 240 of a transistor in 150 both sides of panel；
Step S3, a precalculated position is formed above the panel 150 connect with the bit line of bit line generation electrical connection
Mouthful；
Step S4 forms the capacitor 430 in the side of the gate electrode, and the capacitor 430 and the transmission are logical
Road 230 generates electrical connection.
Above-mentioned technical proposal can effectively reduce the design area of DRAM cell.
In a preferred embodiment, as depicted in figs. 1 and 2, a pair of of DRAM cell (MCD<1>,MCD
<2>) in a center of symmetry with panel 150.
In above-mentioned technical proposal, panel 150 has certain height, and to dampening relative to the horizontal plane of semiconductor substrate
Flat first direction is expanded, i.e. left and right directions in Fig. 1.Meanwhile form wordline (WL on the two sides of panel 150<1>) and wordline
(WL<2>)。
In a preferred embodiment, bit line (BL) extends towards horizontal second direction, i.e. upper and lower in Fig. 1
To.The boundary layer separations (BLC) of bit line are positioned at the crosspoint of panel 150 and bit line.
In above-mentioned technical proposal, a binding site of transistor passes through boundary layer separations in DRAM cell
It sets up to form bit line connector 350 (BFLG), electrical contact is generated with bit line；Another binding site passes through capacitor boundary layer separations
Set up to form capacitor connector 420, with capacitor 430 generation be electrically connected.
With reference to Fig. 1, Fig. 2 and Fig. 3, DRAM cell respectively includes a transistor and a capacitor.
The binding site of transistor is connected by same bit line connector with bit line, another binding site of transistor with
One end of capacitor is connected, and the other end of capacitor can apply capacitance voltage.
In above-mentioned technical proposal, the voltage of transistor wordline can ensure the unimpeded of Transfer pipe.
In a preferred embodiment, the vertical direction of each Transfer pipe is distributed in the one side of panel, i.e., a pair of dynamic
The vertical direction of the Transfer pipe of state random-access memory unit is opposite two-by-two on the basis of panel.
In a preferred embodiment, a pair of of DRAM cell shares panel 150 and bit line connector
350。
In a preferred embodiment, without using photoresist as mask when forming wordline 1 and wordline 2.
In above-mentioned technical proposal, the wordline 1 and wordline 2 of active regions (ARACT) form the gate electrode of transistor,
In a preferred embodiment, the method that panel 150 is formed in the step S1 includes the following steps：
Step S11 as shown in Figure 5 a, one first oxide layer 110 and one is deposited in the semiconductor substrate surface successively
One insulating layer 130；
Step S12 in 130 surface deposition of the first insulating layer, one first mask layer, patterns first mask layer,
In a precalculated position formation process window；
Step S13, by first mask layer to first insulating layer 130, first oxide layer 110 and described
Semiconductor substrate performs etching, and stays in a predetermined depth in the semiconductor substrate, forms splitter box 140 as shown in Figure 5 b
(TRH)；
Step S14 removes first mask layer, and one second mask layer, figure are formed in 130 surface of the first insulating layer
Second mask layer described in case, in a precalculated position formation process window；
Step S15, by second mask layer to first insulating layer 130, first oxide layer 110 and described
Semiconductor substrate performs etching, and stays in a predetermined depth in the semiconductor substrate, forms panel 150 as shown in Figure 5 c；
In above-mentioned technical proposal, the first insulating layer 130 can use nitride film (SiN)
In a preferred embodiment, the method that gate electrode is formed in the step S2 includes the following steps：
Step S21 removes second mask layer, and ion is carried out in the semiconductor substrate and 150 surface of the panel
Injection, forms Transfer pipe 230 as fig 5d；
Step S22 forms one second oxide layer 210 and one first in the semiconductor substrate and 150 surface of the panel
Conducting shell 220；
Step S23 performs etching first conducting shell 220, forms gate electrode 240 as depicted in fig. 5e；
In a preferred embodiment, the method for forming bit line connector 350 includes the following steps：
Step S31 forms a third oxide layer 310 in the surface gate electrode, 210 surface of the second oxide layer；
Step S32 planarizes the third oxide layer 210, stays in 130 surface of the first insulating layer；
Step S33 removes first insulating layer 130 and first oxide layer 110, forms a groove structure；
Step S34 in the 4th oxide layer 330 of groove structure disposed on sidewalls 1, forms structure as shown in figure 5f；
Step S35, in 330 surface deposition of the 4th oxide layer, one second conducting shell 340；
Step S36 planarizes second conducting shell 340, stays in 310 surface of third oxide layer, is formed as schemed
Bit line connector 350 shown in 5g；
In a preferred embodiment, the method that capacitor 430 is formed in the step S4 includes the following steps：
Step S41 forms a second insulating layer in 350 surface of bit line connector and third oxidation layer surface
410th, a third mask layer patterns the third mask layer, in a precalculated position formation process window；
Step S42 performs etching the second insulating layer 410 by the third mask layer, and perforation described second is absolutely
Edge layer 410, the third oxide layer 310 and second oxide layer 210, stop to the semiconductor substrate surface；
Step S43 deposits a third conducting shell 420 above the semiconductor base；
Step S44 planarizes the third conducting shell 420, until exposing the second insulating layer 410, is formed such as Fig. 5 h institutes
The capacitor connector 420 shown；
Step S45 forms capacitor 430 as shown in figure 5i above the capacitor connector 420.
Wherein, the Transfer pipe 230 is higher than the semiconductor substrate.
Wherein, described 240 at least part of gate electrode is silicified.
Wherein, described 240 at least part of gate electrode is made of tungsten or titanium.
A kind of DRAM cell for reducing design area, can be manufactured by any of the above-described method, including：
One silicon base is formed with a panel 150 in the silicon base；
One splitter box 140, is set to inside the silicon base；
One bit line connector 350 is set to 150 top of panel, is connected with a bit line；
Transfer pipe 230 is covered in 150 both sides of the silicon substrate surface and the panel；
Gate electrode 240 is set on the Transfer pipe 230 of the silicon base and 150 angle of panel；
Capacitor 430 is set to above the silicon base, passes through capacitor connector 420 and 230 phase of Transfer pipe
Even.
In above-mentioned technical proposal, by way of shared panel 150 and bit line connector 350, reach reduction dynamic random
The purpose of the design area of memory cell.
The foregoing is merely preferred embodiments of the present invention, not thereby limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all include within the scope of the present invention.
Claims (10)
1. a kind of manufacturing method for the DRAM cell for reducing design area, manufactures applied to semiconductor storage
Field, which is characterized in that each DRAM cell includes a transistor, a capacitor, the transistor
The Transfer pipe between bit line and the capacitor is connected in gate electrode under the control of word line voltage；Per a pair of dynamic random
Memory cell is prepared by following steps：
Step S1, in the panel that horizontal direction expansion is formed on semiconductor substrate；
Step S2 forms the gate electrode of a transistor in the panel both sides；
Step S3, a precalculated position forms the bit line connector being electrically connected with bit line generation above the panel；
Step S4 forms the capacitor in the side of the gate electrode, and the capacitor is electrically connected with Transfer pipe generation
It connects.
2. according to the method described in claim 1, it is characterized in that, formed in the step S1 panel method include with
Lower step：
Step S11 deposits one first oxide layer and one first insulating layer successively in the semiconductor substrate surface；
Step S12 deposits one first mask layer in first surface of insulating layer, patterns first mask layer, pre- in one
Formation process window is put in positioning；
Step S13, by first mask layer to first insulating layer, first oxide layer and the semiconductor substrate
It performs etching, stays in a predetermined depth in the semiconductor substrate, form splitter box；
Step S14 removes first mask layer, forms one second mask layer in first surface of insulating layer, patterns institute
The second mask layer is stated, in a precalculated position formation process window；
Step S15, by second mask layer to first insulating layer, first oxide layer and the semiconductor substrate
It performs etching, stays in a predetermined depth in the semiconductor substrate, form the panel.
3. according to the method described in claim 2, it is characterized in that, the method for gate electrode is formed in the step S2 including following
Step：
Step S21 removes second mask layer, and ion implanting, shape are carried out to the semiconductor substrate and the panel surface
Into the Transfer pipe；
Step S22 forms one second oxide layer and one first conducting shell in the semiconductor substrate and the panel surface；
Step S23 performs etching first conducting shell, forms the gate electrode.
4. according to the method described in claim 3, it is characterized in that, the method for forming the bit line connector includes following step
Suddenly：
Step S31 forms a third oxide layer in the surface gate electrode, the second oxidation layer surface；
Step S32 planarizes the third oxide layer, stays in first surface of insulating layer；
Step S33 removes first insulating layer and first oxide layer, forms a groove structure；
Step S34, in the 4th oxide layer of groove structure disposed on sidewalls 1；
Step S35, in one second conducting shell of the 4th oxide layer surface deposition；
Step S36 planarizes second conducting shell, stays in the third oxidation layer surface, forms the bit line connector.
5. according to the method described in claim 4, it is characterized in that, the method for capacitor is formed in the step S4 including following
Step：
Step S41 connects discharge surface in the bit line and third oxidation layer surface forms a second insulating layer, a third is covered
Film layer patterns the third mask layer, in a precalculated position formation process window；
Step S42 performs etching the second insulating layer by the third mask layer, penetrates through the second insulating layer, institute
Third oxide layer and second oxide layer are stated, is stopped to the semiconductor substrate surface；
Step S43 deposits one second conducting shell above the semiconductor base；
Step S44 planarizes second conducting shell, until exposing the second insulating layer, forms capacitor connector；
Step S45 forms the capacitor above the capacitor connector.
6. according to the method described in claim 3, it is characterized in that, the Transfer pipe is higher than the semiconductor substrate.
7. according to the method described in claim 1, it is characterized in that, gate electrode at least part is silicified.
8. according to the method described in claim 1, it is characterized in that, gate electrode at least part is made of tungsten or titanium.
9. according to the method described in claim 1, it is characterized in that, the Transfer pipe includes the ingredient and level of vertical direction
The ingredient in direction.
10. a kind of DRAM cell for reducing design area, which is characterized in that including：
One silicon base is formed with a panel in the silicon base；
One splitter box is set to inside the silicon base；
One bit line connector is set to above the panel, is connected with a bit line；
Transfer pipe is covered in the silicon substrate surface and the panel both sides；
Gate electrode is set on the Transfer pipe of the silicon base and the panel angle；
Capacitor is set to above the silicon base, is connected by capacitor connector with the Transfer pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711434312.3A CN108172578A (en) | 2017-12-26 | 2017-12-26 | A kind of DRAM cell and its manufacturing method for reducing design area |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711434312.3A CN108172578A (en) | 2017-12-26 | 2017-12-26 | A kind of DRAM cell and its manufacturing method for reducing design area |
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| Publication Number | Publication Date |
|---|---|
| CN108172578A true CN108172578A (en) | 2018-06-15 |
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ID=62521372
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711434312.3A Pending CN108172578A (en) | 2017-12-26 | 2017-12-26 | A kind of DRAM cell and its manufacturing method for reducing design area |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02135777A (en) * | 1988-11-17 | 1990-05-24 | Sony Corp | Semiconductor memory |
| US20020008269A1 (en) * | 1999-04-30 | 2002-01-24 | Chiara Corvasce | Structure of a stacked memory cell, in particular a ferroelectric cell |
| CN1702869A (en) * | 2004-05-25 | 2005-11-30 | 株式会社日立制作所 | Semiconductor memory device |
| US20060211231A1 (en) * | 2005-03-15 | 2006-09-21 | Elpida Memory, Inc. | Memory device and manufacturing method thereof |
| US20090085088A1 (en) * | 2007-09-28 | 2009-04-02 | Elpida Memory, Inc. | Semiconductor device and method of forming the same as well as data processing system including the semiconductor device |
| US20110121374A1 (en) * | 2009-11-24 | 2011-05-26 | Elpida Memory, Inc. | Semiconductor device and method for manufacturing the same |
| US20130023095A1 (en) * | 2011-07-20 | 2013-01-24 | Elpida Memory, Inc. | Method of manufacturing device |
| KR20140086647A (en) * | 2012-12-28 | 2014-07-08 | 에스케이하이닉스 주식회사 | Semiconductor device with metal pad and method for fabricating the same |
-
2017
- 2017-12-26 CN CN201711434312.3A patent/CN108172578A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02135777A (en) * | 1988-11-17 | 1990-05-24 | Sony Corp | Semiconductor memory |
| US20020008269A1 (en) * | 1999-04-30 | 2002-01-24 | Chiara Corvasce | Structure of a stacked memory cell, in particular a ferroelectric cell |
| CN1702869A (en) * | 2004-05-25 | 2005-11-30 | 株式会社日立制作所 | Semiconductor memory device |
| US20060211231A1 (en) * | 2005-03-15 | 2006-09-21 | Elpida Memory, Inc. | Memory device and manufacturing method thereof |
| US20090085088A1 (en) * | 2007-09-28 | 2009-04-02 | Elpida Memory, Inc. | Semiconductor device and method of forming the same as well as data processing system including the semiconductor device |
| US20110121374A1 (en) * | 2009-11-24 | 2011-05-26 | Elpida Memory, Inc. | Semiconductor device and method for manufacturing the same |
| US20130023095A1 (en) * | 2011-07-20 | 2013-01-24 | Elpida Memory, Inc. | Method of manufacturing device |
| KR20140086647A (en) * | 2012-12-28 | 2014-07-08 | 에스케이하이닉스 주식회사 | Semiconductor device with metal pad and method for fabricating the same |
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| CB02 | Change of applicant information |
Address after: Room 1228, 12th floor A, Block B, 2855 Lane 1-72, Zhaoxiang Town, Qingpu District, Shanghai 201700 Applicant after: Dongxin Semiconductor Co., Ltd. Address before: 201200 Pudong New Area, Shanghai, China (Shanghai) free trade trial area, 1 1 203/03, Guo Shou Jing Road. Applicant before: East core Semiconductor Co Ltd |
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Application publication date: 20180615 |
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