CN108170622A - A kind of multiple CPLD chip address automatic configuration systems and method - Google Patents
A kind of multiple CPLD chip address automatic configuration systems and method Download PDFInfo
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- CN108170622A CN108170622A CN201711465531.8A CN201711465531A CN108170622A CN 108170622 A CN108170622 A CN 108170622A CN 201711465531 A CN201711465531 A CN 201711465531A CN 108170622 A CN108170622 A CN 108170622A
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- cpld
- cpld chips
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- chips
- automatic configuration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
Abstract
The present invention relates to a kind of multiple CPLD chip address automatic configuration systems and method, the system to include：Central processing unit, for sending smbus control signals to specified CPLD chips；CPLD chips for signal being controlled to send channel break-make control signal to specific bypass modules according to smbus, are additionally operable to generate the slave device address slaveAddr of the CPLD chips according to pin codes, so that central processing unit reads and writes different CPLD chips；Bypass modules, for signal being controlled to control the channel break-make between each function element according to channel break-make；Pin code definition modules are connected between central processing unit and each CPLD chips, for being directed to different CPLD chips imparting pin codes and sending it to CPLD chips.The central processing unit of the present invention can access CPLD chips according to the different slave device address of CPLD chips in expansion card.
Description
Technical field
Field is automatically configured the present invention relates to CPLD chip address more particularly to a kind of multiple CPLD chip address are matched automatically
Put system and method.
Background technology
Bypass exactly can allow two networks not pass through net by specific triggering state (power on, power off or crash)
The system of network safety equipment, and be directly physically connected, so after having bypass, after Network Security Device failure, also
The network mutual conduction being connected in this equipment can be allowed, certain this when of this network equipment also would not be again to network
In package process.Bypass is usually triggered or is controlled by power supply, GPIO and watchdog.
In the prior art or patent, existing program can realize controls of the CPU to bypass.It is that CPU passes through wherein to have one kind
Smbus (System Management Bus, smbus bus) accesses CPLD (Complex Programmable Logic
Devic, Complex Programmable Logic Devices) in related register, and then control bypass GPIO (General Purpose
Input Output, referred to as universal input/output, GPIO or bus extender) pin, achieve the purpose that control bypass.
Technology used in this technical solution belongs to known technology.
For this technical solution mentioned above, it is possible that being used in a development board to more in actual product
A expansion card, and each expansion card is controlled the situation of bypass by respective CPLD.In this case, will encounter with
Some lower problems：
First, CPU need the slave device address slaveAddr using CPLD by smbus access CPLD, if each expand
CPLD programs on exhibition card then will appear address conflict phenomenon using same slaveAddr；
Second, if the program of CPLD on each expansion card is using respective slaveAddr, and can increase to CPLD
Software maintenance, burning difficulty, be unfavorable for volume production significantly.
Therefore, it is necessary to a kind of multiple CPLD chip address automatic configuration systems and method that can be solved the above problems.
Invention content
According to an aspect of the present invention, a kind of multiple CPLD chip address automatic configuration systems are provided, including：Centre
Device is managed, for sending smbus control signals to specified CPLD chips；CPLD chips, for controlling signal to specific according to smbus
Bypass modules send channel break-make control signal, are additionally operable to generate the slave device address of the CPLD chips according to pin codes
SlaveAddr, so that central processing unit reads and writes different CPLD chips；The bypass modules being set on each function element,
For signal being controlled to control the channel break-make between each function element according to channel break-make；Pin code definition modules, in being connected to
Between central processor and each CPLD chips, for being directed to different CPLD chips imparting pin codes and the pin codes being sent to CPLD
Chip.
Central processing unit is connect with multiple CPLD chips, and CPLD chips are connect with multiple bypass modules.
Central controller is connect by smbus buses with multiple CPLD chips.
Pin codes definition module is the host slot with pin lines, for being connect with the pin feet on CPLD chips.
The low and high level that host slot with pin lines passes through pin lines during the mating connection of host slot and CPLD chips
The pin codes of CPLD chips are defined, CPLD chips generate slave device address slaveAddr according to pin codes.
Multiple pin feet are set on CPLD chips.
When setting 4 pin feet on CPLD chips, host slot number is 16.
According to another aspect of the present invention, a kind of multiple CPLD chip address method of automatic configuration are provided, including following
Step：Pin codes definition module assigns different low and high level pin codes for different CPLD chips, and CPLD chips identify this
After pin codes, the slave device address slaveAddr of the CPLD chips is generated, so that central processing unit reads and writes CPLD chips；Centre
It manages device and sends smbus control signals to multiple CPLD chips；CPLD chips control signal to multiple bypass modules according to smbus
Send channel break-make control signal；The bypass modules being set on each function element control signal control according to channel break-make
Channel break-make between each function element.
Multiple CPLD chip address method of automatic configuration of the present invention, further include：Host slot with pin lines passes through master
The low and high level of pin lines defines the pin codes of CPLD chips during the mating connection of plate slot and CPLD chips.
Compared with prior art, the present invention it has the following advantages：
1. the CPLD chip firmwares of the present invention can generate current slot CPLD cores according to the different pin codes on different slots
The slave device address slaveAddr of piece, to reach the different purposes of CPLD slave devices address slaveAddr on different slots.
2. the central processing unit of the present invention can come to visit according to CPLD chips slave device address slaveAddr in different expansion cards
It asks the CPLD chips on the expansion card, and controls its bypass.
3. CPLD chips only need a program in expansion card, you can are used in all expansion board.
4. in hardware design, the respective low and high level of pin0~pin3 on each host slot need to only be configured, without
Need user's manual jumper, it is not required that worry the fashionable address conflict issues of more clampings.
During 5.CPLD chip volume productions, it is only necessary to the same CPLD firmwares of burning.
Description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this field
Technical staff will become clear.Attached drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Setting.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings：
Fig. 1 is multiple CPLD chip address automatic configuration system block diagrams of the present invention；
Fig. 2 is multiple CPLD chip address method of automatic configuration flow diagrams of the present invention.
Specific embodiment
The exemplary embodiment of the disclosure is more fully described below with reference to accompanying drawings.Although the disclosure is shown in attached drawing
Exemplary embodiment, it being understood, however, that may be realized in various forms the disclosure without should be by embodiments set forth here
It is set.On the contrary, these embodiments are provided to facilitate a more thoroughly understanding of the present invention, and can be by the scope of the present disclosure
Completely it is communicated to those skilled in the art.
Those skilled in the art of the present technique are appreciated that unless expressly stated, singulative " one " used herein, " one
It is a ", " described " and "the" may also comprise plural form.It is to be further understood that is used in the specification of the present invention arranges
Diction " comprising " refers to there are the feature, integer, step, operation, element and/or component, but it is not excluded that presence or addition
Other one or more features, integer, step, operation, element, component and/or their group.
Those skilled in the art of the present technique are appreciated that unless otherwise defined all terms used herein are (including technology art
Language and scientific terminology), there is the meaning identical with the general understanding of the those of ordinary skill in fields of the present invention.Should also
Understand, those terms such as defined in the general dictionary, it should be understood that have in the context of the prior art
The consistent meaning of meaning, and unless by specific definitions, otherwise will not be explained with the meaning of idealization or too formal.
Fig. 1 is multiple CPLD chip address automatic configuration system block diagrams of the present invention, as shown in Figure 1, provided by the invention
Multiple CPLD chip address automatic configuration systems, including：Central processing unit, for sending smbus controls to specified CPLD chips
Signal；CPLD chips for signal being controlled to send channel break-make control signal to specific bypass modules according to smbus, are also used
In the slave device address slaveAddr that the CPLD chips are generated according to pin codes, so that central processing unit reads and writes different CPLD cores
Piece；The bypass modules being set on each function element, for signal being controlled to control each function element according to channel break-make
Between channel break-make；Pin code definition modules are connected between central processing unit and each CPLD chips, different for being directed to
CPLD chips assign pin codes and the pin codes are sent to CPLD chips.Central processing unit is connect with multiple CPLD chips, CPLD
Chip is connect with multiple bypass modules.Central controller is connect by smbus buses with multiple CPLD chips.Pin codes define
Module is the host slot with pin lines, for being connect with the pin feet on CPLD chips.Host slot with pin lines passes through
The low and high level of pin lines defines the pin codes of CPLD chips, CPLD chip roots during the mating connection of host slot and CPLD chips
Slave device address slaveAddr is generated according to pin codes.Multiple pin feet are set on CPLD chips, when setting 4 on CPLD chips
During pin feet, host slot number can be 16.The present invention CPLD chip firmwares can according to the different pin codes on different slots,
The slave device address slaveAddr of current slot CPLD chips is generated, to reach CPLD slave devices address on different slots
The different purposes of slaveAddr.
Wherein, CPLD chips are given birth to according to pin codes by the mapping relations between pin codes and slave device address slaveAddr
Into the slave device address slaveAddr of the CPLD chips, which can be table, formula etc..
Specifically, when setting 4 pins on CPLD chips, multiple CPLD chip address automatic configuration systems of the invention
Operation principle it is as follows：4 pin lines on each host slot are set, are inserted mainboard is inserted into including the expansion card of CPLD chips
Slot, the low and high level of 4 pin lines of CPLD chips identification host slot, i.e. pin codes are true according to the low and high level of 4 pin lines
Determine the slave device address slaveAddr of CPLD chips.
CPLD chips generate its slave device address by pin codes so that when the CPLD chips in multiple host slots are phase
During with model, the CPLD chip slave devices address on each slot is different from, and central processing unit of the invention can be according to difference
Slave device address slaveAddr access different expansion card CPLD chips, and control its bypass, so as to avoid CPLD chips
Address conflict issues；Meanwhile the CPLD chips in expansion card are without to avoid address conflict from distinguishing burning program, thus,
During CPLD chip volume productions, it is only necessary to the same CPLD firmwares of burning.
Illustratively, it is automatic to multiple CPLD chip address of the present invention by hardware design and two aspects of Software for Design
Configuration system carries out description below.
From hardware design, multiple CPLD chip address automatic configuration systems of the invention based on CPLD chips,
Mainly include " CPLD chip slave devices address wire " and " CPLD chip controls bypassGPIO ".Therefore, it in hardware design, only needs
The respective low and high level of pin0~pin3 on the good each host slot of configuration, without user's manual jumper, it is not required that
Worry the fashionable address conflict issues of more clampings.
" CPLD chip slave devices address wire " is the 4 pin feet drawn from CPLD chips, is docked with host slot.This 4
The low and high level of pin feet is provided by host slot, shares 16 kinds of various combinations, each corresponding respective slot of combination.It is this to do
Method is similar to 4 bit in binary system, and value range is 0~15, if pin0~pin3 corresponds respectively to bit0~bit3,
The low and high level of that pin0~pin3 just corresponds to 1/0 value of bit0~bit3 respectively.Underneath with bit0~bit3 value-
Pin codes come represent the different low and high levels of pin0~pin3 combine.So the value range of pin codes 0~15 can be used for table
Show the slot 0~15 belonging to CPLD chips.
" CPLD chip controls bypass GPIO " belongs to known technology, by writing CPLD chip programs, and by bypass
GPIO transfers to CPLD programs to control.
From Software for Design, multiple CPLD chip address automatic configuration systems of the invention include " CPLD programs " and
" CPU programs ".Wherein, " CPU programs " is divided into " program under bios " and " program under linux ", and principle is the same, herein
It is stated with CPU programs.
" CPLD programs " mainly realizes two parts function：A part controls for communicating with CPU according to the instruction of CPU
bypass；Another part is used to identify the affiliated slots of CPLD, and then configure the " CPLD corresponding to the slot according to pin codes
Chip slave device address "-slaveAddr.
It is the smbus agreements of standard that " CPLD programs " communicates with " CPU programs ", this partly belongs to known technology, no longer in detail
It states.
" CPLD programs " is converted into pin codes, CPLD chip roots according to the low and high level of pin0~pin3 of affiliated slot
According to included address and its mapping relations of pin codes of host slot and slaveAddr are installed and are configured " CPLD slave devices
Location "-CPU accesses the slave device address needed for CPLD chips.
" CPU programs " accesses and is configured the register of CPLD chips according to the smbus agreements of standard, so as to reach control
The purpose of bypass." CPU programs " accesses to CPLD chips according to the slaveAddr of different slots.SlaveAddr's
Value is not single to have fixed mapping relations with pin codes, this is also on the different slots that " CPU programs " and " CPLD programs " agree upon
CPLD slave devices address.
In short, pin0~the pin3 different to different slot configurations, so that it is determined that going out respective pin codes；CPLD chips
Program generates slave device address-slaveAddr according to the pin codes for the slot being currently accessed；CPU programs according to slaveAddr come
CPLD chips are accessed and are configured, so as to reach the desired effect of control bypass.
Fig. 2 is multiple CPLD chip address method of automatic configuration flow diagrams of the present invention, as shown in Fig. 2, of the invention
The multiple CPLD chip address method of automatic configuration provided, include the following steps：Pin codes definition module is directed to different CPLD cores
Piece assigns different low and high level pin codes, after CPLD chips identify the pin codes, generates the slave device address of the CPLD chips
SlaveAddr, so that central processing unit reads and writes CPLD chips；Central processing unit sends smbus control letters to multiple CPLD chips
Number；CPLD chips control signal to send channel break-make control signal to multiple bypass modules according to smbus；It is set to each work(
Bypass modules on energy device control signal to control the channel break-make between each function element according to channel break-make.
Specifically, pin codes definition module be the host slot with pin lines, host slot and expansion card with pin lines
Pin feet connection on middle CPLD chips.Therefore, multiple CPLD chip address method of automatic configuration provided by the invention, including with
Lower step：Pin codes definition module assigns different pin foot low and high levels, CPLD chips for different expansion card CPLD chips
Current slot CPLD chip slave devices address SlaveAddr is generated after identifying the pin foot low and high levels, so that central processing unit is read
Take CPLD chips；Central processing unit is sent according to smbus agreements, and using SlaveAddr as slave device address to CPLD chips
Control signal；CPLD chips control signal to send the control of channel break-make respectively to specific or multiple bypass modules according to smbus
Signal；The bypass modules on each function element are set to according between each function element of channel break-make control signal control
Channel break-make.
The apparatus embodiments described above are merely exemplary, wherein the unit illustrated as separating component can
To be or may not be physically separate, the component shown as unit may or may not be physics list
Member, you can be located at a place or can also be distributed in multiple network element.It can be selected according to the actual needs
In some or all of module realize the purpose of this embodiment scheme.Those of ordinary skill in the art are not paying creativeness
Labour in the case of, you can to understand and implement.
Through the above description of the embodiments, those skilled in the art can be understood that each embodiment can
It is realized by the mode of software plus required general hardware platform, naturally it is also possible to pass through hardware.Based on such understanding, on
Technical solution is stated substantially in other words to embody the part that the prior art contributes in the form of software product, it should
Computer software product can store in a computer-readable storage medium, such as ROM/RAM, magnetic disc, CD, including several fingers
It enables and (can be personal computer, server or the network equipment etc.) so that computer equipment is used to perform each implementation
Method described in certain parts of example or embodiment.
In addition, it will be appreciated by those of skill in the art that although some embodiments in this include institute in other embodiments
Including certain features rather than other feature, but the combination of the feature of different embodiment means in the scope of the present invention
Within and form different embodiments.For example, in the following claims, embodiment claimed it is arbitrary it
One mode can use in any combination.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention is described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that：It still may be used
To modify to the technical solution recorded in foregoing embodiments or carry out equivalent replacement to which part technical characteristic；
And these modification or replace, various embodiments of the present invention technical solution that it does not separate the essence of the corresponding technical solution spirit and
Range.
Claims (10)
1. a kind of multiple CPLD chip address automatic configuration systems, which is characterized in that including：
Central processing unit, for sending smbus control signals to specified CPLD chips；
CPLD chips for signal being controlled to send channel break-make control signal to specific bypass modules according to smbus, are additionally operable to
The slave device address slaveAddr of the CPLD chips is generated according to pin codes, so that central processing unit reads and writes different CPLD cores
Piece；
The bypass modules being set on each function element, for signal being controlled to control each function element according to channel break-make
Between channel break-make；
Pin code definition modules are connected between central processing unit and each CPLD chips, are assigned for being directed to different CPLD chips
The pin codes are simultaneously sent to CPLD chips by pin codes.
2. multiple CPLD chip address automatic configuration systems according to claim 1, which is characterized in that central processing unit with
Multiple CPLD chips connections, CPLD chips are connect with multiple bypass modules.
3. multiple CPLD chip address automatic configuration systems according to claim 2, which is characterized in that central controller leads to
Smbus buses are crossed to connect with multiple CPLD chips.
4. multiple CPLD chip address automatic configuration systems according to claim 3, which is characterized in that pin codes define mould
Block is the host slot with pin lines, for being connect with the pin feet on CPLD chips.
5. multiple CPLD chip address automatic configuration systems according to claim 4, which is characterized in that with pin lines
Host slot defines the pin of CPLD chips by the low and high level of pin lines during the mating connection of host slot and CPLD chips
Code, CPLD chips generate slave device address slaveAddr according to pin codes.
6. multiple CPLD chip address automatic configuration systems according to claim 5, which is characterized in that set on CPLD chips
Put multiple pin feet.
7. multiple CPLD chip address automatic configuration systems according to claim 6, which is characterized in that when on CPLD chips
When setting 4 pin feet, host slot number is 16.
8. a kind of multiple CPLD chip address method of automatic configuration, which is characterized in that include the following steps：
Pin codes definition module assigns different low and high level pin codes for different CPLD chips, and CPLD chips identify this
After pin codes, the slave device address slaveAddr of the CPLD chips is generated, so that central processing unit reads and writes CPLD chips；
Central processing unit sends smbus control signals to multiple CPLD chips；
CPLD chips control signal to send channel break-make control signal to multiple bypass modules according to smbus；
The bypass modules on each function element are set to according between each function element of channel break-make control signal control
Channel break-make.
9. multiple CPLD chip address method of automatic configuration according to claim 8, which is characterized in that pin codes define mould
Block is the host slot with pin lines, and the host slot with pin lines is connect with the pin feet on CPLD chips.
10. multiple CPLD chip address method of automatic configuration according to claim 9, which is characterized in that further include：It carries
The host slot of pin lines defines CPLD cores by the low and high level of pin lines during the mating connection of host slot and CPLD chips
The pin codes of piece.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711465531.8A CN108170622A (en) | 2017-12-28 | 2017-12-28 | A kind of multiple CPLD chip address automatic configuration systems and method |
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| CN201711465531.8A CN108170622A (en) | 2017-12-28 | 2017-12-28 | A kind of multiple CPLD chip address automatic configuration systems and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109583032A (en) * | 2018-11-01 | 2019-04-05 | 郑州云海信息技术有限公司 | A kind of backboard end VPP address configuration circuit and its design method |
| CN111352877A (en) * | 2018-12-20 | 2020-06-30 | 技嘉科技股份有限公司 | System management bus device management system and method thereof |
| CN114328314A (en) * | 2021-12-31 | 2022-04-12 | 华勤通讯香港有限公司 | Address automatic acquisition method, device, terminal equipment and storage medium |
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| CN114328314A (en) * | 2021-12-31 | 2022-04-12 | 华勤通讯香港有限公司 | Address automatic acquisition method, device, terminal equipment and storage medium |
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