CN108170257A - A kind of Dynamic voltage scaling system and method for adjustment - Google Patents
A kind of Dynamic voltage scaling system and method for adjustment Download PDFInfo
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- CN108170257A CN108170257A CN201810234268.XA CN201810234268A CN108170257A CN 108170257 A CN108170257 A CN 108170257A CN 201810234268 A CN201810234268 A CN 201810234268A CN 108170257 A CN108170257 A CN 108170257A
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- 238000004364 calculation method Methods 0.000 claims abstract description 9
- 238000004458 analytical method Methods 0.000 claims description 36
- 230000003362 replicative effect Effects 0.000 claims description 5
- 238000001514 detection method Methods 0.000 abstract description 9
- 238000005516 engineering process Methods 0.000 description 9
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
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Abstract
Present invention is disclosed a kind of Dynamic voltage scaling system and methods of adjustment, the system comprises master controller, power management chip and at least one operation chips, after operation chip has been more than predetermined threshold value for detection calculations result error rate, operation mistake information is sent to master controller；Master controller is used to adjust the supply voltage of operation chip to power management chip according to operation mistake delivering power supply adjustment order.The present invention controls chip power-consumption under frequency fixing situation by reducing voltage, can efficiently, farthest reduce chip power supply voltage, and by hardware detection, is substantially shorter that voltage detecting, adjustment time are short, improves chip and the power-efficient of system.
Description
Technical field
The present invention relates to a kind of Dynamic voltage scaling technologies, and voltage is reduced by dynamic to control work(more particularly, to one kind
The Dynamic voltage scaling system and method for adjustment of consumption.
Background technology
With the development of integrated circuit technique, the scale of chip is increasing, and power consumption has become in IC design more
Carry out the problem of more important.Dynamic voltage frequency adjusts (Dynamic Voltage Freque ncy Scaling, abbreviation DVFS)
Technology is a kind of dynamic voltage frequency regulation technology being widely adopted at present in semiconductor applications, and DVFS technologies are specifically dynamic
State adjusts the running frequency and voltage of chip, so as to reach energy-efficient purpose.The technology is more and more applied to height at present
Performance calculates (HPC) system, as multi-core central processing unit (CPU), tensor processor (TPU), virtual coin are dug in ore deposit chip.
There are mainly two types of the solutions of existing chip dynamic regulation of voltage frequency, first, software is handled, but at software
Reason needs many clock cycle that could complete data analysis and adjustment, and mostly based on the free time for judging CPU, such as patent Shen
Please publication No. be that a kind of patent name is disclosed in CN103345296A as " dynamic voltage frequency adjustment trigger device and method "
Technology, cardinal principle is：At the end of timing cycle, by timer to idleness calculator and DVFS interrupt generators into
Row triggering；The processor idleness in timing cycle terminated by idleness calculator based on the triggering calculating；By in DVFS
Disconnected generator determines whether the processor idleness in the timing cycle terminated exceeds current processor power consumption based on the triggering
Either if lower limit beyond the upper limit or lower limit of current processor power consumption level, sends out interrupt signal to the upper limit of rank.Two
It is to adjust the operating voltage of chip or frequency using Digital Logic time margin, as patent application publication number is
The technology that a kind of patent name is " dynamic voltage frequency adjusting method and system " is disclosed in CN103426453A, it is main
Principle is：The operating voltage of monitoring memory in real time calculates the working frequency and frequency correspondence for determining that memory is current desired
Target voltage, the minimum voltage preset value size of target voltage, current voltage and memory is respectively compared, according to target electricity
Pressure, determines read operation preset clearance value desired value, makes memory in target voltage, and the read operation of memory is set aside some time gap
Enough.So as on the basis of ensuring that memory read operation is accurate, the operating voltage of memory is adjusted to be less than preset
Minimum operating voltage, to reduce the operating power consumption of memory.
However above two scheme there is detection to a certain extent when realizing and adjustment time is longer, and implements
The problem of relatively complicated.
Existing large size digit chip, such as CPU, TPU, DSP (Digital Signal Processing, at digital signal
Reason) and GPU (Graphics Processing Unit, graphics processor) in, the relationship of power consumption and voltage, frequency is for example following
Shown in formula：
P=aCFV2；
Wherein, P is workload (power), and a is constant, and C is load capacitance, and F is frequency, and V is chip digital part electricity
Source voltage, power consumption and voltage are quadratic relationships as can be seen from the above equation, therefore reduce the Income Maximum of voltage versus power consumption control.
Invention content
The defects of it is an object of the invention to overcome the prior art, providing a kind of can efficiently reduce voltage and can shorten adjustment
The Dynamic voltage scaling system and method for adjustment of time.
To achieve the above object, the following technical solutions are proposed by the present invention：A kind of Dynamic voltage scaling system, including：Master control
Device processed, power management chip and at least one operation chip, wherein,
At least one operation chip is communicated to connect with master controller, for detecting its operation mistake rate, and described
After error rate has been more than predetermined threshold value, operation mistake information is sent to the master controller；
The master controller is communicated to connect with power management chip, for collecting the operation that the operation chip reports
Error message, and according to operation mistake delivering power supply adjustment order to power management chip；
The power management chip is connected with operation chip, for receiving the adjustment order of the power supply of the master controller
And provide corresponding supply voltage to the operation chip.
Preferably, the operation chip is multiple, and multiple operation chips are in series or parallel operation.
Preferably, the operation chip includes a duplication arithmetic core and a statistics judging unit, wherein,
The duplication arithmetic core calculates corresponding operation result for receiving preset operand, by algorithm and exports
To the Statistic analysis unit；
The Statistic analysis unit is used to judge whether the operation result is correct, and count the arithmetic fault in setting time
Accidentally number according to the operation mistake number and performs operation mistake rate described in the ratio calculation of operation total degree, and described
After error rate has been more than predetermined threshold value, operation mistake information is sent to the master controller.
Preferably, preset in the Statistic analysis unit for detect replicate arithmetic core output operation result whether
A correct reference results, Statistic analysis unit are used to received operation result and the reference results being compared,
If the two is consistent, judge that the operation result is correct, if it is inconsistent, judging operation result mistake.
Preferably, a predetermined threshold value is also preset in the Statistic analysis unit, Statistic analysis unit is used to calculate
The operation mistake rate gone out is compared with the predetermined threshold value, will fortune if error rate has been more than the predetermined threshold value
Miscalculate false information and be sent to master controller.
Preferably, the master controller receives the error message that multiple operation chips report, and at least associative operation simultaneously
The supply voltage value of chip operation, power consumption, operational capability judge whether to send out power supply adjustment order to power management chip, come
Control the supply voltage of power management chip adjustment operation chip.
Preferably, the operation chip further includes an at least arithmetic core, the structure of the arithmetic core and the duplication
The structure of arithmetic core is same or similar.
Preferably, the operation chip is communicated by bus with master controller connect.
Preferably, the power MOSFET tube for controlling power supply, the power supply are equipped in or beyond the power management chip
Managing chip controls MOSFET pipes to provide supply voltage to operation chip.
Preferably, HIP630x chips or TL494 chips at least can be used in the power management chip.
Preferably, the embeded processor of FPGA or integrated ARM cores at least can be used in the master controller.
The invention also provides another technical solutions：A kind of Dynamic voltage scaling method, including：
S1 detects its operation mistake rate, and after the error rate has been more than predetermined threshold value by an at least operation chip,
Operation mistake information is sent to master controller；
S2, the operation mistake information reported by the master controller collection operation chip, and according to the fortune
Miscalculate false information and send out power supply adjustment order to power management chip；
S3, the power supply adjustment that the master controller is received by the power management chip are ordered and to the operation core
Piece provides corresponding supply voltage.
Preferably, the S1 includes：
S11 receives preset operand by duplication arithmetic core, by algorithm calculate corresponding operation result export to
Statistic analysis unit；
S12, whether operation result is correct as described in Statistic analysis unit judges, and counts the operation mistake in setting time
Number according to the operation mistake number and performs operation mistake rate described in the ratio calculation of operation total degree, and in the mistake
After accidentally rate has been more than predetermined threshold value, operation mistake information is sent to master controller.
Preferably, in S12, whether the operation result as described in Statistic analysis unit judges correctly specifically includes：It is described
Statistic analysis unit by received operation result with its built in reference results be compared, if the two is consistent, sentence
The operation result that breaks is correct, if it is inconsistent, judging operation result mistake
Preferably, it is described after the error rate has been more than predetermined threshold value in S12, operation mistake information is sent to
Master controller specifically includes：Statistic analysis unit is used for the operation mistake rate calculated and built-in predetermined threshold value phase
Compare, if error rate has been more than the predetermined threshold value, operation mistake information is sent to master controller.
The beneficial effects of the invention are as follows：
1st, one kind is proposed under frequency fixing situation, and a kind of dynamic electric voltage of chip power-consumption is controlled by reducing voltage
Adjustment system and method for adjustment can efficiently, farthest reduce the supply voltage of chip digital part.
2nd, by hardware detection, it is short to be substantially shorter voltage detecting, adjustment time, improves operation chip and high-performance calculation
The power-efficient of system.
3rd, the application advantage in more computing chip systems of series-fed and parallel operation becomes apparent.
Description of the drawings
Fig. 1 is the structure diagram of the Dynamic voltage scaling system of series-fed of the present invention；
Fig. 2 is the structure diagram of the Dynamic voltage scaling system of parallel operation of the present invention；
Fig. 3 is the structure diagram of operation chip interior of the present invention；
Fig. 4 is the flow diagram of the method for the present invention；
Fig. 5 is the flow diagram of present invention method.
Specific embodiment
Below in conjunction with the attached drawing of the present invention, clear, complete description is carried out to the technical solution of the embodiment of the present invention.
A kind of disclosed Dynamic voltage scaling system and method for adjustment, it is fixed in frequency, pass through
Voltage is farthest reduced, so as to achieve the effect that preferably to reduce chip operation energy consumption.
With reference to shown in Fig. 1 and Fig. 2, a kind of revealed Dynamic voltage scaling system of the embodiment of the present invention is one high property
Energy computing system (HPC systems), including：Master controller, power management chip and at least one operation chip, wherein, operation
Chip is the core of this HPC systems, for carrying out data calculating, such as tensor (Tensor) operation, cryptographic calculation
(Encryption Operation) etc..With reference to shown in Fig. 3, operation chip is generally one and includes built-in at least one operation
The chip of core (i.e. arithmetic logical unit), arithmetic core for it is multiple when, such as it is tens of, even hundreds of when, these operations
The structure and function of chip is identical or similar.
Unlike the structure of existing operation chip, addition one in operation chip of the embodiment of the present invention replicates fortune
Core (Replica Computing Core) and a statistics judging unit are calculated, wherein, replicate structure and the operation of arithmetic core
The structure of existing above-mentioned arithmetic core is the same or similar in chip, and in the situation for not performing detection function of the present invention
Under, it can perform the function identical with existing above-mentioned arithmetic core.In the embodiment of the present invention, replicate arithmetic core and be mainly used for connecing
Preset operand is received to the algorithm unit of itself, such as above-mentioned tensor algorithm or Encryption Algorithm, such as operand is encrypted
After algorithm, correspondingly, algorithm unit, which can export a fixed operation result, gives Statistic analysis unit.
In the present embodiment, preset in Statistic analysis unit for detect replicate arithmetic core output operation result whether
A correct reference results, Statistic analysis unit be mainly used for by it is received duplication arithmetic core output operation result with
Reference results in its own are compared, if the two is consistent, illustrate that the operation result for replicating arithmetic core is correct, if
It is inconsistent, then illustrate operation result mistake, no matter the operation result correctness that Statistic analysis unit judges go out, replicates operation core
After Statistic analysis unit judges go out result, the algorithm for continuing next operand calculates the heart.And Statistic analysis unit exists
While judging operation result mistake, it can count and replicate operation mistake number of the arithmetic core in setting time, it such as can be with
It is counted by a timer conter.
Further, Statistic analysis unit is in the operation mistake number for counting duplication arithmetic core in setting time
Afterwards, it is additionally operable to perform the ratio of operation total degree according to the operation mistake number and in the setting time to calculate operation core
The operation mistake rate of piece, the operation total degree such as performed within the 1s times set is 10,000 time, the operation counted in the 1s
Errors number is 5 times, then the operation mistake rate calculated is then 0.0005.
In the present embodiment, a predetermined threshold value is also preset in Statistic analysis unit, which can configure, Statistic analysis
Unit compares the above-mentioned operation mistake rate calculated with the predetermined threshold value, if error rate has been more than the pre-determined threshold
Value, then be sent to master controller by operation mistake information.Wherein, operation chip is communicated to connect by bus and master controller.
In the present embodiment, it can be in series with reference to shown in Fig. 1 and Fig. 2, between operation chip or side by side, can be respectively used to
More computing chip systems of series-fed and parallel operation.During series connection, such as 20 operation chip-in series, each operation chip institute
The supply voltage needed is 1V, then total supply voltage needed for 20 series connection operation chips is then 20V；When in parallel, such as 20 fortune
Chip parallel connection is calculated, the supply voltage needed for each operation chip is 1V, then total power supply electricity needed for 20 operation chips in parallel
Pressure is then 1V.
In addition, the present invention carries out operational performance by the duplication arithmetic core in operation chip and Statistic analysis unit
Detection, duplication arithmetic core and Statistic analysis unit here, compared to the processing of existing software, can pass through hardware by hardware timeout
Detection, can shorten detection, adjustment time.
Master controller passes through the digital interfaces such as bus and operation chip phase two-way communication link.In the present embodiment, main control
Device is mainly used for collecting the operation mistake information that operation chip reports, and adjust and order according to the operation mistake delivering power supply
To power management chip.Specifically, during multiple operation chips, master controller is simultaneously or almost simultaneously received on multiple operation chips
The error message of report, according to these information, and supply voltage value (the i.e. P=in power consumption formula of associative operation chip real work
aCFV2In parameter V value), power consumption (i.e. P=aCFV in power consumption formula2In parameter P value), operational capability etc. it is a variety of because
Element judges whether to send out power supply adjustment order to power management chip, to control the confession of power management chip adjustment operation chip
Piezoelectric voltage.
By taking the parallel system being made of 100 operation chips as an example.Master controller receives an operation chip and reports mistake
Rate is more than threshold value, and it is setting that master controller, which can inquire firmware (firmware here refers to the driver preserved inside main controller),
Power consumption is preferentially or calculating power preferential principle does corresponding judgement.If calculating, power is preferential, and master controller can send out the electricity that voltage is turned up
Source adjustment order, for the supply voltage of operation chip to be turned up, makes this operation chip error rate be reduced to below threshold value.If
Firmware setting power consumption is preferential, and master controller, which can further compare raising supply voltage, makes the operation chip be restored to normal work institute
Increase the percentage of power consumption and this operation chip accounts for the calculation power percentage of the entire HPC systems of the application.If this operation core
Piece is shared calculate power percentage less than improve supply voltage make this operation chip be restored to normal work increased power consumption hundred
Divide ratio, master controller will not then send out the power supply adjustment order that voltage is turned up, conversely, then sending out the power supply adjustment life of height-regulating voltage
It enables.
During implementation, master controller can be FPGA (Field-Programmable Gate Array, field programmable gate
Array), the embeded processor of integrated ARM cores etc..
Power management (Voltage Regulator Module, abbreviation VRM) chip and master controller and operation chip are equal
Connection is communicated, one side is used to receive the power supply adjustment order of master controller, is generated according to power supply adjustment order corresponding
Supply voltage gives operation chip power supply；The opposing party's operation chip sends operation mistake information to master controller.Specifically, power supply pipe
(or external) has power MOSFET (the Metal-Oxide-Semiconductor Field- for controlling power supply in reason chip
Effect Tran sistor, Chinese full name Metal-Oxide Semiconductor field-effect transistor) pipe, power management chip control
MOSFET pipes provide supply voltage to operation chip, and the supply voltage value main controller control specifically provided.During implementation, electricity
Such as HIP630x chips, TL494 chips can be used in source control chip.
Based on above-mentioned Dynamic voltage scaling system, as shown in figure 4, the embodiment of the present invention further discloses a kind of dynamic electric voltage tune
Adjusting method, including：
S1 detects its operation mistake rate, and after error rate has been more than predetermined threshold value by an at least operation chip, will transport
Miscalculate false information and be sent to master controller.
Specifically, with reference to shown in Fig. 5, the arithmetic core that replicates in operation chip receives preset operand to the calculation of itself
Method unit, algorithm unit can export a fixed operation result and give Statistic analysis unit.Statistic analysis unit is received
Duplication arithmetic core output operation result be compared with the reference results in its own, if the two is consistent, illustrate
The operation result for replicating arithmetic core is correct, if it is inconsistent, illustrating operation result mistake；Statistic analysis unit is being judged
While operation result mistake, the operation mistake number for replicating arithmetic core in setting time can be counted, according to the arithmetic fault
It misses number and the ratio of operation total degree is performed in the setting time to calculate the operation mistake rate of operation chip, Statistic analysis
Unit compares the above-mentioned operation mistake rate calculated with the predetermined threshold value, if error rate has been more than the pre-determined threshold
Value, then be sent to master controller by operation mistake information.
S2, the operation mistake information reported by master controller collection operation chip, and according to the operation mistake delivering
Power supply adjustment order is to power management chip.
Specifically, specifically, during multiple operation chips, master controller is simultaneously or almost simultaneously received on multiple operation chips
The error message of report, according to these information, and supply voltage value, power consumption, operational capability of associative operation chip real work etc.
Many factors judge whether to send out power supply adjustment order to power management chip, power management chip to be controlled to adjust operation core
The supply voltage of piece.
S3 receives the power supply adjustment order of master controller by power management chip and provides corresponding power supply to operation chip
Voltage.
Specifically, there is the power MOSFET (Metal-Oxide- for controlling power supply in power management chip
Semiconductor Field-Effect Transistor, Chinese full name Metal-Oxide Semiconductor field-effect transistor)
Pipe, power management chip control MOSFET pipes give operation chip to provide supply voltage, and the supply voltage value acceptor specifically provided
Controller controls.
On the basis of the present invention is by being based on operation chip to error rate judgement, carried out with reference to other information described above
Dynamic voltage scaling can reduce the supply voltage of operation chip to the greatest extent, so as to farthest reduce whole system
Operating power consumption, reached power consumption control result more better than existing computation-free time and time margin and shortened detection and tune
The whole time.
The technology contents and technical characteristic of the present invention have revealed that as above, however those skilled in the art still may base
Make various replacements and modification without departing substantially from spirit of the present invention, therefore, the scope of the present invention in teachings of the present invention and announcement
The revealed content of embodiment should be not limited to, and various replacements and modification without departing substantially from the present invention should be included, and is this patent Shen
Please claim covered.
Claims (11)
1. a kind of Dynamic voltage scaling system, which is characterized in that including：Master controller, power management chip and at least one fortune
Chip is calculated, wherein,
At least one operation chip is communicated to connect with master controller, for detecting its operation mistake rate, and in the mistake
After rate has been more than predetermined threshold value, operation mistake information is sent to the master controller；
The master controller is communicated to connect with power management chip, for collecting the operation mistake that the operation chip reports
Information, and according to operation mistake delivering power supply adjustment order to power management chip；
The power management chip is connected with operation chip, for receive the power supply of the master controller adjustment order and to
The operation chip provides corresponding supply voltage.
2. Dynamic voltage scaling system according to claim 1, which is characterized in that the operation chip is multiple to be multiple
The operation chip is in series or parallel operation.
3. Dynamic voltage scaling system according to claim 1, which is characterized in that the operation chip includes one and replicates fortune
Core and a statistics judging unit are calculated, wherein,
For receiving preset operand, calculate corresponding operation result by algorithm exports the duplication arithmetic core to institute
State Statistic analysis unit；
The Statistic analysis unit counts the operation mistake in setting time for judging whether the operation result is correct
Number according to the operation mistake number and performs operation mistake rate described in the ratio calculation of operation total degree, and in the mistake
After rate has been more than predetermined threshold value, operation mistake information is sent to the master controller.
4. Dynamic voltage scaling system according to claim 3, which is characterized in that preset in the Statistic analysis unit
For detecting the whether correct reference results of operation result for replicating arithmetic core output, Statistic analysis unit is used to be connect
The operation result received is compared with the reference results, if the two is consistent, judges that the operation result is correct, if
It is inconsistent, then judge operation result mistake.
5. Dynamic voltage scaling system according to claim 3, which is characterized in that also preset in the Statistic analysis unit
There is a predetermined threshold value, the operation mistake rate that Statistic analysis unit is used to calculate is compared with the predetermined threshold value
Compared with if error rate has been more than the predetermined threshold value, operation mistake information is sent to master controller.
6. Dynamic voltage scaling system according to claim 1, which is characterized in that the master controller receives multiple simultaneously
The error message that operation chip reports, and at least supply voltage value of associative operation chip operation, power consumption, operational capability judge
Whether power supply adjustment order is sent out to power management chip, to control the supply voltage of power management chip adjustment operation chip.
7. Dynamic voltage scaling system according to claim 3, which is characterized in that the operation chip further includes at least one
Arithmetic core, the structure of the arithmetic core and the structure for replicating arithmetic core are same or similar.
8. a kind of Dynamic voltage scaling method based on Dynamic voltage scaling system described in 3~7 any one of the claims,
It is characterised in that it includes：
S1 detects its operation mistake rate, and after the error rate has been more than predetermined threshold value, will transport by an at least operation chip
Miscalculate false information and be sent to master controller；
S2, the operation mistake information reported by the master controller collection operation chip, and according to the arithmetic fault
False information sends out power supply adjustment order to power management chip；
S3 is received the power supply adjustment order of the master controller by the power management chip and is carried to the operation chip
For corresponding supply voltage.
9. Dynamic voltage scaling method according to claim 8, which is characterized in that the S1 includes：
S11 receives preset operand by duplication arithmetic core, calculates corresponding operation result by algorithm and export to statistics
Judging unit；
S12, whether operation result is correct as described in Statistic analysis unit judges, and counts the operation mistake in setting time
Number according to the operation mistake number and performs operation mistake rate described in the ratio calculation of operation total degree, and in the mistake
After rate has been more than predetermined threshold value, operation mistake information is sent to master controller.
10. Dynamic voltage scaling method according to claim 9, which is characterized in that described by Statistic analysis list in S12
Member judges whether the operation result correctly specifically includes：The Statistic analysis unit will be in received operation result and its
The reference results put are compared, if the two is consistent, judge that the operation result is correct, if it is inconsistent, judging fortune
Calculate result mistake.
11. Dynamic voltage scaling method according to claim 9, which is characterized in that described in the error rate in S12
It has been more than after predetermined threshold value, operation mistake information is sent to master controller and is specifically included：Statistic analysis unit by will based on
The operation mistake rate calculated is compared with built-in predetermined threshold value, if error rate has been more than the predetermined threshold value,
Operation mistake information is sent to master controller.
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| CN110286729A (en) * | 2019-05-21 | 2019-09-27 | 晶晨半导体(上海)股份有限公司 | A method of the power supply Vtune parameter for grafting reactants processor |
| CN110502358A (en) * | 2019-08-16 | 2019-11-26 | 紫光展锐(重庆)科技有限公司 | Operation method and device |
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| CN112558507A (en) * | 2019-09-25 | 2021-03-26 | 北京比特大陆科技有限公司 | Frequency adaptation method and apparatus, data processing device, medium, and product |
| CN115250172A (en) * | 2022-09-22 | 2022-10-28 | 千纳微电子技术(南通)有限公司 | Side channel protection method and system under dynamic frequency switching |
| CN116107646A (en) * | 2022-12-23 | 2023-05-12 | 无锡摩芯半导体有限公司 | Method for starting serial chips |
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| WO2024040887A1 (en) * | 2022-08-25 | 2024-02-29 | 深圳比特微电子科技有限公司 | Power supply voltage control method and device, blockchain server, and storage medium |
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