CN108156748A - Signal wire when printed circuit board double-sided mounts is fanned out to method and printed circuit board - Google Patents
Signal wire when printed circuit board double-sided mounts is fanned out to method and printed circuit board Download PDFInfo
- Publication number
- CN108156748A CN108156748A CN201711476766.7A CN201711476766A CN108156748A CN 108156748 A CN108156748 A CN 108156748A CN 201711476766 A CN201711476766 A CN 201711476766A CN 108156748 A CN108156748 A CN 108156748A
- Authority
- CN
- China
- Prior art keywords
- circuit board
- printed circuit
- fanned out
- blind hole
- signal wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/093—Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10189—Non-printed connector
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
Abstract
A kind of signal wire when the present invention provides printed circuit board double-sided attachment is fanned out to method and printed circuit board, the method includes：In the topsheet surface and bottom surface of printed circuit board, one or more blind holes are set respectively；One or more signal wires of two components to be mounted of the topsheet surface for being mounted on the printed circuit board respectively and bottom surface are fanned out to by each blind hole；The size of wiring space is configured when the quantity and position of the blind hole mount the component to be mounted in the topsheet surface or bottom surface according to the printed circuit board；The topsheet surface or bottom surface of the printed circuit board are equipped with the one or more vias for being fanned out to the signal wire not being fanned out in the component to be mounted by the blind hole.The mode that the present invention is combined using blind hole and through-hole solves the smooth of signal wire when PCB tables, two layers of bottom same position install QSFP DD connectors simultaneously and is fanned out to, and ensure that preferable signal integrity.
Description
Technical field
The present invention relates to electronic circuit fields, and more particularly to mounting technology field, specially a kind of printed circuit board is double
Signal wire when face paste fills is fanned out to method and printed circuit board.
Background technology
In next-generation 400G network switch product, highdensity QSFP-DD connectors can be used as I/O ports.
QSFP (Quad Small Form-factor Pluggable) refers to four-way SFP interfaces (QSFP).The pluggable of 4 channels connects
Port transmission rate has reached 40Gbps.Speed and density are superior to 4 channel C X4 interfaces.Small pluggable QSFP connectors can expire
The sufficient multiple supply agreements of MSA, can significantly simplify the design work of client, including host connector signal integrity, module
Squirrel-cage EMI protection and heat dissipation and light pipe signal solution.Passive and active copper cable component length is up to 20 meters.Circle
Shape optical cable can improve cable management in the application.Four 10G high speed dedicated channels are integrated in one pluggable mutually to link
In system, the port density for being four times in SFP is obtained.
In order to improve the I/O port densities in unit space, can be used in high-end product identical on PCB tops, two surface of bottom
Position is the same as the design method of fashionable dress QSFP-DD connectors.But such design requirement is to the letter of highdensity QSFP-DD connectors
The integrality of number line being fanned out on PCB and 56Gbps high speed signals brings difficult and challenge.
Invention content
In order to solve the technical issues of above-mentioned and other are potential, the embodiment provides a kind of printed circuits
Signal wire during the two-sided attachment of plate is fanned out to method, and the signal wire during printed circuit board double-sided attachment is fanned out to method and includes：In
The topsheet surface and bottom surface of printed circuit board set one or more blind holes respectively；It is fanned out to by each blind hole and pasted respectively
One or more signal wires of two components to be mounted of topsheet surface and bottom surface loaded on the printed circuit board.
In one embodiment of the invention, the quantity of the blind hole and position are according to the topsheet surface of the printed circuit board
Or the size of wiring space is configured when the component to be mounted is mounted in bottom surface.
In one embodiment of the invention, the topsheet surface or bottom surface of the printed circuit board are equipped with to be waited to paste by described
One or more vias that the signal wire not being fanned out in dress component by the blind hole is fanned out to.
In one embodiment of the invention, the component to be mounted is connector.
In one embodiment of the invention, the connector is QSFP-DD connectors.
The embodiment of the present invention also provides a kind of printed circuit board, the topsheet surface and bottom surface of the printed circuit board
One or more blind holes are set respectively；Be fanned out to by each blind hole be mounted on respectively the printed circuit board topsheet surface and
One or more signal wires of two components to be mounted of bottom surface.
In one embodiment of the invention, the quantity of the blind hole and position are according to the topsheet surface of the printed circuit board
Or the size of wiring space is configured when the component to be mounted is mounted in bottom surface.
In one embodiment of the invention, the topsheet surface or bottom surface of the printed circuit board are equipped with to be waited to paste by described
One or more vias that the signal wire not being fanned out in dress component by the blind hole is fanned out to.
In one embodiment of the invention, the component to be mounted is connector.
In one embodiment of the invention, the connector is QSFP-DD connectors.
As described above, the signal wire during printed circuit board double-sided attachment of the present invention is fanned out to method and printed circuit board and has
Following advantageous effect：
The present invention sets one or more blind holes respectively in the topsheet surface and bottom surface of printed circuit board, passes through each institute
State one that blind hole is fanned out to two components to be mounted of the topsheet surface for being mounted on the printed circuit board respectively and bottom surface
Or multiple signal wires, it is not fanned out to by the signal wire that blind hole is fanned out to by one or more vias in the component to be mounted, profit
The mode being combined with blind hole and through-hole under the normal level of PCB manufacturing process, is solved in PCB tables, two layers of bottom identical bits
Signal wire is smoothly fanned out to, and ensure that preferable signal integrity when putting while installing QSFP-DD connectors.
Description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for
For those of ordinary skill in the art, without creative efforts, other are can also be obtained according to these attached drawings
Attached drawing.
Signal wire when Fig. 1 is shown as the printed circuit board double-sided attachment of the present invention is fanned out to the flow diagram of method.
Signal wire when Fig. 2 is shown as the printed circuit board double-sided attachment of the present invention is fanned out to the preferred flow signal of method
Figure.
Fig. 3 is shown as the setting exemplary plot of via and blind hole on the top layer of the printed circuit board of the present invention.
Fig. 4 is shown as the setting exemplary plot of via and blind hole on the bottom of the printed circuit board of the present invention.
Component label instructions
100 printed circuit boards
110 vias
120 blind holes
S110~S130 steps
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.It should be noted that in the absence of conflict, following embodiment and implementation
Feature in example can be combined with each other.
It please refers to Fig.1 to Fig.4.It should be clear that structure, ratio, size depicted in this specification institute accompanying drawings etc., only to
Coordinate the revealed content of specification, so that those skilled in the art understands and reads, being not limited to the present invention can be real
The qualifications applied, therefore do not have technical essential meaning, the tune of the modification of any structure, the change of proportionate relationship or size
It is whole, in the case where not influencing the effect of present invention can be generated and the purpose that can reach, should all still fall in disclosed skill
Art content is obtained in the range of covering.Meanwhile in this specification it is cited as " on ", " under ", "left", "right", " centre " and
The term of " one " etc. is merely convenient to understanding rather than to limit the enforceable range of the present invention for narration, relativeness
It is altered or modified, in the case where changing technology contents without essence, when being also considered as the enforceable scope of the present invention.
The purpose of the present embodiment is that signal wire when providing a kind of printed circuit board double-sided attachment is fanned out to method and printing
Circuit board can not mount QSFP-DD connectors simultaneously for solving PCB tops, two surface same position of bottom in the prior art
Problem.
Signal wire during the printed circuit board double-sided attachment of the present invention described in detail below is fanned out to method and printed circuit
The principle and embodiment of plate makes those skilled in the art not need to the printed circuit board that creative work is appreciated that the present invention
Signal wire during two-sided attachment is fanned out to method and printed circuit board.
As shown in Figure 1, signal wire when present embodiments providing a kind of printed circuit board double-sided attachment is fanned out to method, it is described
Signal wire when printed circuit board double-sided mounts is fanned out to method and includes：
Step S110 sets one or more blind holes respectively in the topsheet surface and bottom surface of printed circuit board；
Step S120 is fanned out to by each blind hole and is mounted on the topsheet surface of the printed circuit board and bottom table respectively
One or more signal wires of two components to be mounted in face.
In this present embodiment, as shown in Fig. 2, the signal wire when printed circuit board double-sided mounts is fanned out to method and includes：
Step S130, the topsheet surface or bottom surface of the printed circuit board be equipped with by the component to be mounted not by described blind
One or more vias that the signal wire that hole is fanned out to is fanned out to.
Signal wire when being mounted below to the present embodiment printed circuit board double-sided is fanned out to step S110 in method to step
S130 is described in detail.
Step S110 as shown in Figure 3 and Figure 4, one is set in the topsheet surface and bottom surface of printed circuit board 100 respectively
A or multiple blind holes 120.
One layer therein in (PCB) top layer of printed circuit board 100 or bottom of blind hole 120 (Blind Via) is seen, separately
That outer layer can't see, that is to say, that blind hole 120 is bored from surface, but does not drill through all layers.Such as in 4 layers of PCB,
As long as blind hole 120 may be from 1 layer to 2 layer or from 4 layers to 3 layer, 120 advantage of blind hole is 1 layer, and 2 layers of conducting do not interfere with 3
Layer, 4 layers of cabling).But blind hole 120 generally requires laser drilling machine and drills.Blind hole 120 be applied to superficial layer and one or
The connection of multiple internal layers is exactly simply that 120 surface of blind hole can only see one side, and another side is in printed circuit board 100
(PCB) it is inner.It is typically employed in four layers or four layers or more of pcb board.
Step S120, be fanned out to by each blind hole 120 be mounted on respectively the printed circuit board 100 topsheet surface and
One or more signal wires of two components to be mounted of bottom surface.
In this present embodiment, the component to be mounted is connector；Preferably, in this present embodiment, the connector is
QSFP-DD connectors.
Since one or more signal wires of the QSFP-DD connectors of the topsheet surface of the printed circuit board 100 pass through
Blind hole 120 is fanned out to, and one or more signal wires of the QSFP-DD connectors of the bottom surface of the printed circuit board 100 also lead to
It crosses blind hole 120 to be fanned out to, the blind hole 120 of the topsheet surface of the printed circuit board 100 and the bottom table of the printed circuit board 100
120 phase of blind hole in face is independent of each other, so the top layer and bottom same position in PCB can install QSFP-DD connectors simultaneously,
Each blind hole 120 can be when the top layer and bottom same position of PCB can install QSFP-DD connectors simultaneously by signal wire
It is smoothly fanned out to, and ensure that preferable signal integrity.
Wherein, in this present embodiment, the quantity of the blind hole 120 and position are according to the top layer of the printed circuit board 100
The size of wiring space is configured when the component to be mounted is mounted on surface or bottom surface.
For example, the signal wire being fanned out on the inside of connector area with blind hole 120 and its region are due to wiring space deficiency
The signal pins that can not be fanned out to through-hole.
That is, the quantity of blind hole 120 and position can be adjusted according to the wiring of connector, in wiring space not
The i.e. configurable one or more blind holes 120 in place that foot can not use via 110 to be connected up.
Wherein, the position of the blind hole 120 can be located in the topsheet surface or bottom surface of the printed circuit board 100
It on same vertical line, is oppositely arranged, can also be staggered a bit, wiring space is greatly saved.
Step S130, as shown in Figure 3 and Figure 4, the topsheet surface or bottom surface of the printed circuit board 100 are equipped with institute
State one or more vias 110 that the signal wire not being fanned out in component to be mounted by the blind hole 120 is fanned out to.
Via 110 (Via) is also referred to as through-hole, is all got through from (PCB) top layer of printed circuit board 100 to bottom,
Such as in 4 layers of PCB, via 110 is through 1,2,3,4 layers.Via 110 is broadly divided into two kinds：One kind is heavy copper hole PTH
(Plating Through Hole), hole wall has copper, usually excessively electric hole (VIA PAD) and component hole (DIP PAD)；It is another
It is non-heavy copper hole NPTH (Non Plating Through Hole), hole wall is without copper, usually location hole and screw hole.
For example, the signal wire being fanned out on the inside of connector area with blind hole 120 and its region are due to wiring space deficiency
The signal pins that can not be fanned out to through-hole.And other positions, the mode that via 110 may be used are fanned out to signal wire.Utilize blind hole
120 and the mode that is combined of through-hole, under the normal level of PCB manufacturing process, solve in PCB tables, two layers of bottom same position
Signal wire is smoothly fanned out to, and ensure that preferable signal integrity when installing QSFP-DD connectors simultaneously.
This embodiment also provides a kind of printed circuit board 100, as shown in Figure 3 and Figure 4, the printed circuit board 100
Topsheet surface and bottom surface set one or more blind holes 120 respectively；It is fanned out to by each blind hole 120 and is mounted on institute respectively
State one or more signal wires of the topsheet surface of printed circuit board 100 and two components to be mounted of bottom surface.
One layer therein in (PCB) top layer of printed circuit board 100 or bottom of blind hole 120 (Blind Via) is seen, separately
That outer layer can't see, that is to say, that blind hole 120 is bored from surface, but does not drill through all layers.Such as in 4 layers of PCB,
As long as blind hole 120 may be from 1 layer to 2 layer or from 4 layers to 3 layer, 120 advantage of blind hole is 1 layer, and 2 layers of conducting do not interfere with 3
Layer, 4 layers of cabling).But blind hole 120 generally requires laser drilling machine and drills.Blind hole 120 be applied to superficial layer and one or
The connection of multiple internal layers is exactly simply that 120 surface of blind hole can only see one side, and another side is in printed circuit board 100
(PCB) it is inner.It is typically employed in four layers or four layers or more of pcb board.
In this present embodiment, the component to be mounted is connector；Preferably, in this present embodiment, the connector is
QSFP-DD connectors.
Since one or more signal wires of the QSFP-DD connectors of the topsheet surface of the printed circuit board 100 pass through
Blind hole 120 is fanned out to, and one or more signal wires of the QSFP-DD connectors of the bottom surface of the printed circuit board 100 also lead to
It crosses blind hole 120 to be fanned out to, the blind hole 120 of the topsheet surface of the printed circuit board 100 and the bottom table of the printed circuit board 100
120 phase of blind hole in face is independent of each other, so the top layer and bottom same position in PCB can install QSFP-DD connectors simultaneously,
Each blind hole 120 can be when the top layer and bottom same position of PCB can install QSFP-DD connectors simultaneously by signal wire
It is smoothly fanned out to, and ensure that preferable signal integrity.
Wherein, in this present embodiment, as shown in Figure 3 and Figure 4, the quantity of the blind hole 120 and position are according to the printing
The size of wiring space is configured when mounting the component to be mounted in the topsheet surface or bottom surface of circuit board 100.
For example, the signal wire being fanned out on the inside of connector area with blind hole 120 and its region are due to wiring space deficiency
The signal pins that can not be fanned out to through-hole.
That is, the quantity of blind hole 120 and position can be adjusted according to the wiring of connector, in wiring space not
The i.e. configurable one or more blind holes 120 in place that foot can not use via 110 to be connected up.
Wherein, the position of the blind hole 120 can be located at together in the topsheet surface or bottom surface of the printed circuit board
It on one vertical line, is oppositely arranged, can also be staggered a bit, wiring space is greatly saved.
In this present embodiment, as shown in Figure 3 and Figure 4, the topsheet surface of the printed circuit board or bottom surface, which are equipped with, incites somebody to action
One or more vias 110 that the signal wire not being fanned out in the component to be mounted by the blind hole 120 is fanned out to.
Via 110 (Via) is also referred to as through-hole, is all got through from printed circuit board (PCB) top layer to bottom, such as
In 4 layers of PCB, via 110 is through 1,2,3,4 layers.Via 110 is broadly divided into two kinds：One kind is heavy copper hole PTH (Plating
Through Hole), hole wall has copper, usually excessively electric hole (VIA PAD) and component hole (DIP PAD)；Another kind is non-heavy copper
Hole NPTH (Non Plating Through Hole), hole wall is without copper, usually location hole and screw hole.
For example, the signal wire being fanned out on the inside of connector area with blind hole 120 and its region are due to wiring space deficiency
The signal pins that can not be fanned out to through-hole.And other positions, the mode that via 110 may be used are fanned out to signal wire.Utilize blind hole
120 and the mode that is combined of through-hole, under the normal level of PCB manufacturing process, solve in PCB tables, two layers of bottom same position
Signal wire is smoothly fanned out to, and ensure that preferable signal integrity when installing QSFP-DD connectors simultaneously.
In conclusion the present invention sets one or more blind respectively in the topsheet surface and bottom surface of printed circuit board
Hole, two that the topsheet surface for being mounted on the printed circuit board respectively and bottom surface are fanned out to by each blind hole are to be mounted
One or more signal wires of component do not pass through one or more mistakes in the component to be mounted by the signal wire that blind hole is fanned out to
Hole is fanned out to, the mode being combined using blind hole and through-hole, under the normal level of PCB manufacturing process, is solved at PCB tables, bottom
Signal wire is smoothly fanned out to, and ensure that preferable signal integrity when two layers of same position installs QSFP-DD connectors simultaneously.
So the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, technical field includes usual skill complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. signal wire during a kind of printed circuit board double-sided attachment is fanned out to method, it is characterised in that：The printed circuit board double-sided
Signal wire during attachment is fanned out to method and includes：
In the topsheet surface and bottom surface of printed circuit board, one or more blind holes are set respectively；
It is fanned out to by each blind hole and is mounted on the topsheet surface of the printed circuit board respectively and two of bottom surface wait to paste
Fill one or more signal wires of component.
2. signal wire during printed circuit board double-sided attachment according to claim 1 is fanned out to method, it is characterised in that：It is described
When the quantity and position of blind hole mount the component to be mounted in the topsheet surface or bottom surface according to the printed circuit board
The size of wiring space is configured.
3. signal wire during printed circuit board double-sided attachment according to claim 1 is fanned out to method, it is characterised in that：It is described
The topsheet surface or bottom surface of printed circuit board are equipped with the signal not being fanned out in the component to be mounted by the blind hole
One or more vias that line is fanned out to.
4. the signal wire when printed circuit board double-sided according to claim 1,2 or 3 mounts is fanned out to method, feature exists
In：
The component to be mounted is connector.
5. signal wire during printed circuit board double-sided attachment according to claim 4 is fanned out to method, it is characterised in that：It is described
Connector is QSFP-DD connectors.
6. a kind of printed circuit board, it is characterised in that：
The topsheet surface and bottom surface of the printed circuit board set one or more blind holes respectively；
It is fanned out to by each blind hole and is mounted on the topsheet surface of the printed circuit board respectively and two of bottom surface wait to paste
Fill one or more signal wires of component.
7. printed circuit board according to claim 6, it is characterised in that：The quantity of the blind hole and position are according to the print
The size of wiring space is configured when mounting the component to be mounted in the topsheet surface or bottom surface of circuit board processed.
8. printed circuit board according to claim 6, it is characterised in that：The topsheet surface or bottom of the printed circuit board
Surface is equipped with the one or more vias for being fanned out to the signal wire not being fanned out in the component to be mounted by the blind hole.
9. according to the printed circuit board described in claim 6,7 or 8, it is characterised in that：The component to be mounted is connector.
10. printed circuit board according to claim 9, it is characterised in that：The connector is QSFP-DD connectors.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711476766.7A CN108156748A (en) | 2017-12-29 | 2017-12-29 | Signal wire when printed circuit board double-sided mounts is fanned out to method and printed circuit board |
| US16/234,846 US20190208633A1 (en) | 2017-12-29 | 2018-12-28 | Signal trace fan-out method for double-sided mounting on printed circuit board and printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711476766.7A CN108156748A (en) | 2017-12-29 | 2017-12-29 | Signal wire when printed circuit board double-sided mounts is fanned out to method and printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108156748A true CN108156748A (en) | 2018-06-12 |
Family
ID=62462465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711476766.7A Pending CN108156748A (en) | 2017-12-29 | 2017-12-29 | Signal wire when printed circuit board double-sided mounts is fanned out to method and printed circuit board |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20190208633A1 (en) |
| CN (1) | CN108156748A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3675606A1 (en) * | 2018-12-27 | 2020-07-01 | Bull SAS | Printed circuit board making it possible to have a qsfp connector in belly-to-belly with a qsfp-dd connector and associated system |
| FR3092466A1 (en) * | 2018-12-27 | 2020-08-07 | Bull Sas | PRINTED CIRCUIT ALLOWING TO HAVE A BELLY-TO-BELLY QSFP CONNECTOR WITH A QSFP-DD CONNECTOR AND ASSOCIATED SYSTEM |
| US10834830B2 (en) | 2019-02-13 | 2020-11-10 | International Business Machines Corporation | Creating in-via routing with a light pipe |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4787853A (en) * | 1986-03-29 | 1988-11-29 | Kabushiki Kaisha Toshiba | Printed circuit board with through-hole connection |
| CN101790277A (en) * | 2009-04-21 | 2010-07-28 | 华为技术有限公司 | Method for manufacturing PCB (printed circuit board), PCB and device |
| CN101790289A (en) * | 2009-06-10 | 2010-07-28 | 华为技术有限公司 | PCB with interconnected blind holes and processing method thereof |
| CN103687308A (en) * | 2012-09-14 | 2014-03-26 | 北大方正集团有限公司 | Blind-hole Press-joint multilayer printed circuit board and manufacturing method thereof |
Family Cites Families (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5910255A (en) * | 1996-11-08 | 1999-06-08 | W. L. Gore & Associates, Inc. | Method of sequential laser processing to efficiently manufacture modules requiring large volumetric density material removal for micro-via formation |
| JP3395621B2 (en) * | 1997-02-03 | 2003-04-14 | イビデン株式会社 | Printed wiring board and manufacturing method thereof |
| US6452117B2 (en) * | 1999-08-26 | 2002-09-17 | International Business Machines Corporation | Method for filling high aspect ratio via holes in electronic substrates and the resulting holes |
| KR100333627B1 (en) * | 2000-04-11 | 2002-04-22 | 구자홍 | Multi layer PCB and making method the same |
| US6891260B1 (en) * | 2002-06-06 | 2005-05-10 | Lsi Logic Corporation | Integrated circuit package substrate with high density routing mechanism |
| US6777802B1 (en) * | 2002-06-06 | 2004-08-17 | Lsi Logic Corporation | Integrated circuit package substrate with multiple voltage supplies |
| US20040007762A1 (en) * | 2002-07-11 | 2004-01-15 | Lameres Brock J. | Method for fabricating adaptor for aligning and electrically coupling circuit devices having dissimilar connectivity patterns |
| US20040193989A1 (en) * | 2003-03-28 | 2004-09-30 | Sun Microsystems, Inc. | Test system including a test circuit board including through-hole vias and blind vias |
| JP4723178B2 (en) * | 2003-10-28 | 2011-07-13 | エルピーダメモリ株式会社 | Memory system and memory module |
| KR100796983B1 (en) * | 2006-11-21 | 2008-01-22 | 삼성전기주식회사 | Printed circuit board and method for manufacturing thereof |
| US8476770B2 (en) * | 2011-07-07 | 2013-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and methods for forming through vias |
| JP6443609B2 (en) * | 2012-07-10 | 2018-12-26 | パナソニックＩｐマネジメント株式会社 | Connector device and female connector used therefor |
| US10080287B2 (en) * | 2012-09-27 | 2018-09-18 | Dell Products L.P. | Blind via printed circuit board fabrication supporting press fit connectors |
| US9179546B2 (en) * | 2012-09-27 | 2015-11-03 | Dell Products L.P. | Blind via printed circuit board fabrication supporting press fit connectors |
| US9276335B2 (en) * | 2012-12-11 | 2016-03-01 | Advanced Micro Devices, Inc. | Double-sided circuit board with opposing modular card connector assemblies |
| US9337522B2 (en) * | 2013-10-30 | 2016-05-10 | Infineon Technologies Ag | Millimeter-wave system including a waveguide transition connected to a transmission line and surrounded by a plurality of vias |
| TWI684389B (en) * | 2015-04-17 | 2020-02-01 | 王忠寶 | A printing circuit board structure |
| CN105977666A (en) * | 2016-05-07 | 2016-09-28 | 富士康(昆山)电脑接插件有限公司 | Electric connector and electronic equipment equipped with the same |
| CN107994366B (en) * | 2016-10-26 | 2021-07-20 | 富士康(昆山)电脑接插件有限公司 | Socket connector |
| US10185109B2 (en) * | 2016-12-29 | 2019-01-22 | Mellanox Technologies, Ltd. | Modular system for datacenter switch systems and routers |
| US20180287314A1 (en) * | 2017-03-31 | 2018-10-04 | Intel Corporation | Mixed-signal connector and high-speed internal cable assembly |
| US10143100B2 (en) * | 2017-04-06 | 2018-11-27 | Dell Products L.P. | Modular networking device connection system |
| US10318461B2 (en) * | 2017-08-04 | 2019-06-11 | Dell Products L.P. | Systems and methods for interconnecting GPU accelerated compute nodes of an information handling system |
| US10056710B1 (en) * | 2017-10-18 | 2018-08-21 | All Best Precision Technology Co., Ltd. | Terminal module and electrical connector comprising the same |
| US10236645B1 (en) * | 2017-10-26 | 2019-03-19 | All Best Precision Technology Co., Ltd. | Electrical connector |
| US10244629B1 (en) * | 2017-11-03 | 2019-03-26 | Innovium, Inc. | Printed circuit board including multi-diameter vias |
-
2017
- 2017-12-29 CN CN201711476766.7A patent/CN108156748A/en active Pending
-
2018
- 2018-12-28 US US16/234,846 patent/US20190208633A1/en not_active Abandoned
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4787853A (en) * | 1986-03-29 | 1988-11-29 | Kabushiki Kaisha Toshiba | Printed circuit board with through-hole connection |
| CN101790277A (en) * | 2009-04-21 | 2010-07-28 | 华为技术有限公司 | Method for manufacturing PCB (printed circuit board), PCB and device |
| CN101790289A (en) * | 2009-06-10 | 2010-07-28 | 华为技术有限公司 | PCB with interconnected blind holes and processing method thereof |
| CN103687308A (en) * | 2012-09-14 | 2014-03-26 | 北大方正集团有限公司 | Blind-hole Press-joint multilayer printed circuit board and manufacturing method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3675606A1 (en) * | 2018-12-27 | 2020-07-01 | Bull SAS | Printed circuit board making it possible to have a qsfp connector in belly-to-belly with a qsfp-dd connector and associated system |
| FR3092466A1 (en) * | 2018-12-27 | 2020-08-07 | Bull Sas | PRINTED CIRCUIT ALLOWING TO HAVE A BELLY-TO-BELLY QSFP CONNECTOR WITH A QSFP-DD CONNECTOR AND ASSOCIATED SYSTEM |
| US10834830B2 (en) | 2019-02-13 | 2020-11-10 | International Business Machines Corporation | Creating in-via routing with a light pipe |
Also Published As
| Publication number | Publication date |
|---|---|
| US20190208633A1 (en) | 2019-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9560774B2 (en) | Method of fabricating a circuit board | |
| US10194524B1 (en) | Anti-pad for signal and power vias in printed circuit board | |
| JP2020009433A (en) | Routing assembly | |
| US10244629B1 (en) | Printed circuit board including multi-diameter vias | |
| US10716213B2 (en) | Direct connection of high speed signals on PCB chip | |
| CN108156748A (en) | Signal wire when printed circuit board double-sided mounts is fanned out to method and printed circuit board | |
| ITCO20070034A1 (en) | CONNECTION BETWEEN ELECTRIC CABLE AND PRINTED CIRCUIT FOR HIGH DATA TRANSFER AND HIGH FREQUENCY SIGNAL TRANSFER SPEED | |
| CN111308620B (en) | Optical module | |
| EP3641510B1 (en) | Systems and methods for providing a high speed interconnect system with reduced crosstalk | |
| EP3806592A1 (en) | Circuit board combination and electronic device | |
| EP3197112B1 (en) | Back panel structure and centralized switching device | |
| US10455691B1 (en) | Grid array pattern for crosstalk reduction | |
| KR20190044622A (en) | Alternative circuit devices for long host routing | |
| CN109587942B (en) | Clearance size reduction for backdrilled differential vias | |
| US8953337B2 (en) | Communication apparatus with removable circuit boards | |
| CN109792412B (en) | Network switch configured to use optical or electrical interfaces | |
| CN107548226B (en) | Printed circuit board preparation process and printed circuit board | |
| US20080087460A1 (en) | Apparatus and method for a printed circuit board that reduces capacitance loading of through-holes | |
| CN101653049B (en) | A printed board assembly and a method | |
| EP3301855B1 (en) | Network switches configured to employ optical or electrical interfaces | |
| CN100584145C (en) | Circuit board system | |
| WO2021184844A1 (en) | Optical module | |
| TW201611675A (en) | Improved method for structure of circuit board | |
| CN214540157U (en) | Optical module | |
| CN113946019B (en) | Optical module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180612 |