CN108139903B - 依dmb操作用加载/存储操作实施加载撷取/存储释放指令 - Google Patents

依dmb操作用加载/存储操作实施加载撷取/存储释放指令 Download PDF

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Publication number
CN108139903B
CN108139903B CN201580082189.6A CN201580082189A CN108139903B CN 108139903 B CN108139903 B CN 108139903B CN 201580082189 A CN201580082189 A CN 201580082189A CN 108139903 B CN108139903 B CN 108139903B
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China
Prior art keywords
memory
load
store
barrier
fetch
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Expired - Fee Related
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CN201580082189.6A
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English (en)
Chinese (zh)
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CN108139903A (zh
Inventor
M·阿什克拉夫特
C·纳尔逊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denver Intermediate Holdings LLC
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Applied Micro Circuits Corp
Ampere Computing LLC
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Priority to CN201910999320.5A priority Critical patent/CN110795150A/zh
Publication of CN108139903A publication Critical patent/CN108139903A/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Stored Programmes (AREA)
CN201580082189.6A 2015-07-21 2015-07-21 依dmb操作用加载/存储操作实施加载撷取/存储释放指令 Expired - Fee Related CN108139903B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910999320.5A CN110795150A (zh) 2015-07-21 2015-07-21 依dmb操作用加载/存储操作实施加载撷取/存储释放指令

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2015/041322 WO2017014752A1 (en) 2015-07-21 2015-07-21 Implementation of load acquire/store release instructions using load/store operation with dmb operation

Related Child Applications (1)

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CN201910999320.5A Division CN110795150A (zh) 2015-07-21 2015-07-21 依dmb操作用加载/存储操作实施加载撷取/存储释放指令

Publications (2)

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CN108139903A CN108139903A (zh) 2018-06-08
CN108139903B true CN108139903B (zh) 2019-11-15

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CN201580082189.6A Expired - Fee Related CN108139903B (zh) 2015-07-21 2015-07-21 依dmb操作用加载/存储操作实施加载撷取/存储释放指令
CN201910999320.5A Pending CN110795150A (zh) 2015-07-21 2015-07-21 依dmb操作用加载/存储操作实施加载撷取/存储释放指令

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Country Status (4)

Country Link
EP (1) EP3326059A4 (enExample)
JP (1) JP6739513B2 (enExample)
CN (2) CN108139903B (enExample)
WO (1) WO2017014752A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11175924B2 (en) 2017-10-06 2021-11-16 International Business Machines Corporation Load-store unit with partitioned reorder queues with single cam port
US10606590B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Effective address based load store unit in out of order processors
US10606591B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
US10417002B2 (en) 2017-10-06 2019-09-17 International Business Machines Corporation Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses
US10572256B2 (en) 2017-10-06 2020-02-25 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
US10394558B2 (en) 2017-10-06 2019-08-27 International Business Machines Corporation Executing load-store operations without address translation hardware per load-store unit port

Citations (4)

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JP2005332387A (ja) * 2004-05-04 2005-12-02 Sun Microsyst Inc メモリ命令をグループ化及び管理する方法及びシステム
CN101052954A (zh) * 2004-07-29 2007-10-10 索尼计算机娱乐公司 不对称型异构多处理器环境中的存储器屏障原语
CN104050033A (zh) * 2013-03-15 2014-09-17 辉达公司 用于有索引的屏障的硬件调度的系统和方法
CN104106043A (zh) * 2012-02-08 2014-10-15 国际商业机器公司 用于包括屏障指令的指令序列的处理器性能改进

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JPH07302200A (ja) * 1994-04-28 1995-11-14 Hewlett Packard Co <Hp> 順次付けロード動作および順序付け記憶動作を強制する命令を有するコンピュータのロード命令方法。
JP2000181891A (ja) * 1998-12-18 2000-06-30 Hitachi Ltd 共有メモリアクセス順序保証方式
WO2005121948A1 (en) * 2004-06-02 2005-12-22 Sun Microsystems, Inc. Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor
US8060482B2 (en) * 2006-12-28 2011-11-15 Intel Corporation Efficient and consistent software transactional memory
US20100241812A1 (en) * 2007-10-18 2010-09-23 Nxp B.V. Data processing system with a plurality of processors, cache circuits and a shared memory
GB2461716A (en) * 2008-07-09 2010-01-13 Advanced Risc Mach Ltd Monitoring circuitry for monitoring accesses to addressable locations in data processing apparatus that occur between the start and end events.
US8997103B2 (en) * 2009-09-25 2015-03-31 Nvidia Corporation N-way memory barrier operation coalescing
US9582276B2 (en) * 2012-09-27 2017-02-28 Apple Inc. Processor and method for implementing barrier operation using speculative and architectural color values
US9477599B2 (en) * 2013-08-07 2016-10-25 Advanced Micro Devices, Inc. Write combining cache microarchitecture for synchronization events

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005332387A (ja) * 2004-05-04 2005-12-02 Sun Microsyst Inc メモリ命令をグループ化及び管理する方法及びシステム
CN101052954A (zh) * 2004-07-29 2007-10-10 索尼计算机娱乐公司 不对称型异构多处理器环境中的存储器屏障原语
CN104106043A (zh) * 2012-02-08 2014-10-15 国际商业机器公司 用于包括屏障指令的指令序列的处理器性能改进
CN104050033A (zh) * 2013-03-15 2014-09-17 辉达公司 用于有索引的屏障的硬件调度的系统和方法

Also Published As

Publication number Publication date
JP6739513B2 (ja) 2020-08-12
CN110795150A (zh) 2020-02-14
CN108139903A (zh) 2018-06-08
EP3326059A1 (en) 2018-05-30
JP2018523235A (ja) 2018-08-16
WO2017014752A1 (en) 2017-01-26
EP3326059A4 (en) 2019-04-17

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