CN108132467A - The biradical Forward-looking SAR imaging methods of DSP+FPGA and imaging device based on enhanced ADC - Google Patents
The biradical Forward-looking SAR imaging methods of DSP+FPGA and imaging device based on enhanced ADC Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
- G01S13/904—SAR modes
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
- G01S13/904—SAR modes
- G01S13/9058—Bistatic or multistatic SAR
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0421—Multiprocessor system
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- G—PHYSICS
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
- G01S13/904—SAR modes
- G01S13/9043—Forward-looking SAR
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- G—PHYSICS
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/21—Pc I-O input output
- G05B2219/21137—Analog to digital conversion, ADC, DAC
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/22—Pc multi processor system
- G05B2219/2214—Multicontrollers, multimicrocomputers, multiprocessing
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Abstract
The invention discloses a kind of biradical Forward-looking SAR imaging methods of DSP+FPGA based on enhanced ADC.Include the following steps；Step 1. using enhanced ADC echo analog intermediate frequency signal is sampled and Digital Down Convert after obtain complex base band data, be transmitted to FPGA；Step 2. corrects complex base band data into row distance to compression, range walk and FDC corrections, curvature correction and remaining migration, obtains distance to processing data, is transmitted to DSP；Step 3. carries out the non-linear change mark of higher order polynomial-fitting, orientation successively, orientation high order phase filtering, orientation go tiltedly to handle with geometric correction；Form distance figure.The invention also discloses the biradical Forward-looking SAR imaging devices of DSP+FPGA based on enhanced ADC a kind of, including enhancing type analog-to-digital converter, FPGA and DSP, further include network interface chip.The present invention gives full play to the powerful floating-point operation ability of the Digital Down Convert function of analog-digital converter, the efficient parallel feature of FPGA and DSP to big data quantity, realizes biradical Forward-looking SAR high-resolution imaging.
Description
Technical field
The invention belongs to the art fields that communicates, and are related to biradical Forward-looking SAR imaging technique, and in particular to one kind is based on enhanced
The biradical Forward-looking SAR imaging method and imaging device of the DSP+FPGA of ADC.
Background technology
SAR（Synthetic aperture radar）Operation principle is the relative motion using radar and target the smaller true day of size
The method of string holes diameter data processing synthesizes the radar in larger equivalent aerial aperture.The characteristics of synthetic aperture radar is resolution ratio
Height, energy all weather operations can efficiently identify camouflage and penetrate cloak.Biradical synthetic aperture radar employs separation transmitter
And receiver, it flies and radar imagery is realized in different platform, using the special flight path of flying platform, obtain Forward-looking SAR
Image.
At the end of the seventies in last century, the U.S., which takes the lead in carrying out, has carried out the research work of double-base SAR system, by theoretical research and
A series of airborne and spaceborne Bistatic SAR experiment, tentatively solves many double-base SAR system problems, and demonstrate Bistatic SAR technology
Feasibility.Since the new century, with being constantly progressive for airborne and spaceborne technology, Bistatic SAR has been started in global range
Research boom, especially European Region, in the past 10 years, German applied science research institute and German Space Agency have carried out a system successively
The Bistatic SAR experiment under geometric configurations such as with arranging airborne, spaceborne and star, has obtained extraordinary experimental result.Major section of Britain
Mechanism, such as UCL, UOB university are ground, has been carried out airborne, real based on the Bistatic SAR under the geometric configurations such as non-radar external sort algorithm
It tests；Univ Catalunya Politecnica of Spain realizes the static reception Bistatic SAR experiment based on interventional applications.In addition, meaning is big
The scientific research institution of the country such as profit, France has also actively developed the research work of double-base SAR system.At the same time, above-mentioned biradical
Under the promotion of SAR experiments, Bistatic SAR imaging algorithm also deepens continuously, constantly improve, such as based on Smile operators, LBF operators, grade
The imaging algorithm of the thoughts such as number reversion operator.
The Research Centers such as domestic University of Electronic Science and Technology, the National University of Defense technology, Beijing Institute of Technology, Chinese Academy of Sciences electron institute
Related exploratory development is also carried out in terms of the biradical Forward-looking SAR imaging algorithm in place.The technology of more than ten years is passed through by University of Electronic Science and Technology
Tackling key problem, systematically solves the problems such as system system, theoretical method and key technology of biradical Forward-looking SAR, in 2009 for the first time
Comprehensive system to biradical Forward-looking SAR imaging theory and there are the problem of be discussed, and two-shipper Forward-looking SAR is differentiated theoretical
It is studied with optimal operating mode；For moving, change/shifting is constant to wait imaging patterns, it is proposed that quadravalence RNLCS, Keystone-
The series frequency domain imaging algorithm such as NLCS, 2D- ω k efficiently solves biradical Forward-looking SAR coarse migration, close coupling, two-dimentional space-variant etc. and asks
Topic.In terms of verification experimental verification, University of Electronic Science and Technology demonstrated biradical side view SAR imaging mechanisms in 2007, had obtained domestic the
One airborne Bistatic SAR image, resolution ratio reach 1.5 meters（Orientation）× 3 meters（Distance）.In biradical side view SAR theories and experiment
On the basis of research, University of Electronic Science and Technology was successfully realized international biradical positive Forward-looking SAR imaging test airborne for the first time in 2012,
Biradical Forward-looking SAR imaging mechanism is demonstrated to comprehensive system, so as to which research of the China in the field be made to walk in international forefront.
At present, biradical Forward-looking SAR imaging method is more mature, it is necessary to promote the work of biradical Forward-looking SAR imaging method
Journeyization is studied so that biradical Forward-looking SAR imaging method can really be used for science and techniques of defence, and final profit favour is favorable to the people.It is double using
When base Forward-looking SAR imaging method is imaged interested target area, except require flying platform flight path meet into
As requirement is outer, radar is also required to have good lateral distance resolving power in forward sight, which causes radar bearing to must accumulate
Tired sufficiently large data volume.So the main difficulty of biradical Forward-looking SAR high-resolution imaging method engineering is to big data
The real time implementation processing of amount.
Invention content
To overcome the difficulty of biradical Forward-looking SAR engineering, the invention discloses a kind of DSP+FPGA based on enhanced ADC
Biradical Forward-looking SAR imaging method and imaging device.
The technical solution adopted by the present invention to solve the technical problems is a kind of the double of DSP+FPGA based on enhanced ADC
Base Forward-looking SAR imaging method, includes the following steps；
Step 1. the echo analog intermediate frequency signal that synthetic aperture radar receives is sampled and Digital Down Convert after answered
Complex base band data are transmitted to FPGA by base band data by serially sending form；
Step 2. is multiplied to the first intermediate result by complex base band data spectrum and local reference signal frequency spectrum conjugate complex, among first
As a result conjugate multiplication is done with range walk and FDC correction functions, obtains the second intermediate result；Second intermediate result is done in orientation
Conjugate complex is done with range curvature correction function to multiply, obtain third intermediate result after Fourier transformation；Third intermediate result and remnants
Migration correction function does conjugate multiplication, and inverse Fourier transform is done to the data that conjugate multiplication obtains, and obtains distance to processing data；
Distance is carried out the non-linear change mark of higher order polynomial-fitting, orientation, orientation high order by step 3. successively to processing data
Phase filtering, orientation go tiltedly to handle with geometric correction；Form the distance figure being combined with real scene.
Preferably：In the step 1, Digital Down Convert is realized in enhanced ADC.
Preferably：Distance is obtained in the step 2 after processing data, transmits data to DSP progress
Step 3, specific transmission process is：Distance is packaged into stream write packet to processing data, header packet information, the packet header are set
Information includes Packet type, sends address, doorbell information；DSP is sent to after packing, after having sent a frame data, sends door immediately
Bell data packet notice DSP carries out subsequent processing.
Preferably：In the step 3 between DSP and FPGA by SRIO patterns into row data communication.
Biradical Forward-looking SAR imaging method as described in claim 1, it is characterised in that：The FPGA leads to
It crosses JESD204B agreements and carries out data receiver
Preferably：It adjusts the distance in the step 3 and is handled to processing data progress data processing using multinuclear cooperative cooperating, specifically
For：By the data transfer in need for carrying out calculation processing to hinge core；Hinge core is by data distribution to multiple process cores, processing
After the completion, the result respectively obtained is aggregated into hinge core by each process cores；Hinge core summarizes result of calculation.
Preferably：It adjusts the distance in the step 3 and carries out data processing using the table tennis data based on EDMA3 to processing data
The data processing method of transmission；Specially：Divide in built-in LL2 static RAMs and DDR3 registers in DSP
Two pieces of regions are not opened up, the flow work for using ping-pong alternately move and calculate, wherein LL2 static random-access
Memory is as data processor, and DDR3 registers are as data buffer storage device.
The invention also discloses a kind of biradical Forward-looking SAR imaging devices of DSP+FPGA based on enhanced ADC, including network interface
Chip further includes analog-digital converter, FPGA and DSP；It data link and is supported between the analog-digital converter and FPGA
JESD204B communication protocols；The analog-digital converter has been internally integrated digital down converter, using more between the FPGA and DSP
Channel SRIO interconnect, the DSP be multinuclear digital signal processor, further include two respectively with FPGA and DSP data connections
Random access memory, data connection between the network interface chip and DSP.
Preferably：The DSP is TMS320C6678, and the FPGA is in Xilinx companies Virtex-7 series
XC7VX690T, the analog-digital converter are the ADS54J66 of TI companies.
Preferably：The network interface chip is the 88E1111 ethernet physical layer chips of MAXIM companies
The present invention has the advantages that：
The present invention gives full play to mould using the system integrated framework for the enhanced ADC+FPGA+DSP for having Digital Down Convert function
The sampling of number converter and digital frequency down-conversion function, field programmable gate array（FPGA）Efficient parallel processing and data
The characteristics of rich interface and digital signal processor（DSP）To the powerful floating-point operation ability of big data quantity, before reaching biradical
Depending on the purpose of SAR Real-time High Resolutions rate imaging.
Description of the drawings
Fig. 1 is a kind of specific embodiment schematic diagram of biradical Forward-looking SAR imaging device of the present invention.
Fig. 2 is a kind of specific embodiment structure diagram of biradical Forward-looking SAR imaging method of the present invention.
Fig. 3 is that ADC of the present invention and FPGA is shown by the data transmission of JESD204B serial line interfaces into row data communication
It is intended to.
Fig. 4 is using the data transmission schematic diagram of SRIO interconnections between FPGA and DSP of the present invention.
Fig. 5 is the flow diagram of multinuclear cooperative cooperating tupe of the present invention.
Fig. 6 is that the data processing data of the table tennis data transmission based on EDMA3 flows to schematic diagram.
Fig. 7 is the flow diagram of the data processing pipeline schematic diagram of the table tennis data transmission based on EDMA3；Fig. 6 and
PING in Fig. 7, PONG represent table tennis and pang operation in table tennis data transmission respectively.
Specific embodiment
More detailed description is done to embodiments of the present invention below in conjunction with attached drawing and reference numeral.
The biradical Forward-looking SAR imaging method of DSP+FPGA of the present invention based on enhanced ADC, based on following imaging
Device, the imaging device include analog-digital converter, FPGA and DSP；Data link is simultaneously between the analog-digital converter and FPGA
Support JESD204B communication protocols；The analog-digital converter has been internally integrated digital down converter, between the FPGA and DSP
Using multichannel SRIO interconnect, the DSP be multinuclear digital signal processor, further include two respectively with FPGA and DSP data
The random access memory of connection, if Fig. 1 provides a specific embodiment of imaging device, except analog-digital converter ADC, DSP and
Outside FPGA, the necessary peripheral module that power module and clock module etc. make imaging device work is further included.
Analog-digital converter (ADC) chip carries out Digital Down Convert immediately after collecting intermediate-freuqncy signal, is translated into complex radical
Band signal is transferred to by HSSI High-Speed Serial Interface in FPGA again, and fpga core chip passes through after processing the signal into row distance
SRIO interfaces are transferred data in the plug-in DDR3 of DSP, and then DSP progress orientation handles to obtain the image of imaging region,
Target information is uploaded into host computer finally by network interface.
Wherein ADC chip models preferably use the ADS54J66 chips of TI companies.ADS54J6 be a four-way, 14,
500 MSPS (million Million Samples per Second of sampling per second) analog-digital converter (ADC) is supported
JESD204B serial line interfaces, message transmission rate are up to 10Gbps.ADS54J66 is with super low-power consumption in width input frequency range
Outstanding spurious-free dynamic range is provided.Embedded digital signal processing module includes complex mixer, is followed by low-pass filter, supports
The up to receiver bandwidth of 200MHz.ADC chips provide become lower to the high-fidelity acquisition of intermediate frequency analog input signal and number
Frequency function.
Fpga chip is the XC7VX690T in Xilinx companies Virtex-7 series, and configuration passes through PC28F00AP30TF
Chip is completed.The chip performance is high, low in energy consumption, and there is the high-performance FPGA based on real six input lookup table technologies to patrol
Volume, I/O interface bandwidth 2.4Tb/s, logic unit up to 2,000,000, Digital Signal Processing performance reaches 4.7 TMACS,
It can complete complicated signal processing function.Rich interface, built-in many thousands of megabits grade high speed serialization transceiver, speed reach as high as
13.1Gb/s, and the DDR3 interfaces of 2,133Mb/s can be up to supporting rate, carrying out igh-speed wire-rod production line for FPGA carries
For ensureing.Specifically in the present invention, fpga chip, can be into row distance after the complex baseband signal that ADC chips are passed back is received
It corrects, is transferred in the plug-in DDR3 registers of DSP to compression, range walk and FDC corrections, curvature correction and remaining migration,
After transferring a frame data, dsp chip carries out higher order polynomial-fitting, the non-linear change of orientation to the frame data sended over
Mark, orientation high order phase filtering, orientation go tiltedly to handle with geometric correction.
Used multi-core DSP chip model is TMS320C6678 in the present invention.It is 8 using KeyStone frameworks
Core dsp processor, the frequency per core is up to 1.25 GHz, provides powerful fixed point and floating-point operation ability, while in chip
Portion is integrated with the modules such as multinuclear omniselector, SRIO, function gigabit Ethernet and EDMA3.TMS320C6678 has 8 C66x cores, allusion quotation
Type speed is 1GHz, and each caryogamy is set to 1 Data SRAM of 32KB Level, it and DSP cores are operated in identical speed,
It is used as common data storage or data cache；1 Program SRAM of 32KB Level, it and DSP cores are transported
Row is used as common program storage or program cache in identical speed；512KB LL2 SRAM, its fortune
Scanning frequency degree is the half of DSP cores, is used as normal memory or cache, can store data or store journey
Sequence；All DSP cores share 4MB SL2 SRAM, its speed of service is the half of DSP cores, can store data or
Store program.After the frame data that FPGA transmission is received using SRIO, DSP carries out the distribution of multinuclear task and processing, parallel
Ground carries out data orientation high order phase filtering, goes oblique and geometric correction, finally obtains the Bistatic SAR front view of imaging region
Picture, then host computer is uploaded to by network interface.The 88E1111 ethernet physical layer chips of MAXIM companies may be used in network interface chip,
Under the control of the EMAC modules of dsp chip, Bistatic SAR forward sight image is transmitted in the form of gigabit Ethernet with host computer.
Biradical Forward-looking SAR imaging method of the present invention includes the following steps；
Step 1. the echo analog intermediate frequency signal that synthetic aperture radar receives is sampled and Digital Down Convert after answered
Complex base band data are transmitted to FPGA by base band data by serially sending form；
In the present invention, sampling, becoming under number for the analog intermediate frequency signal received to synthetic aperture radar is completed in ADC chips
Frequency and high speed serialization are sent；ADC preferentially selects ADS54J66, inside other than with traditional analog-digital converter, also in
Be equipped with Digital Down Converter Module and JESD204B high speed serialization sending modules, ADS54J66 Digital Down Converter Modules by frequency mixer,
Low-pass filter, decimation filter composition can use FPGA by the way that its inside is configured with the SPI interface that ADS54J66 is interconnected
Related register makes ADC acp chips that the if sampling data down-conversion that bandpass sampling obtains is obtained complex base band data.
JESD204B high speed serialization sending modules are responsible for complex base band serial mode being sent in FPGA, and the configuration of the module can be by
FPGA is completed by SPI (the Serial Peripheral Interface-- Serial Peripheral Interface (SPI)s) interface interconnected with it.
It can be interconnected between fpga chip and ADC chips by JESD204B protocol interfaces, as shown in figure 3, JESD204B
For agreement tool there are four key stratum, transport layer completes the mapping and demapping between sample and not scrambled frame data, optional to add
It disturbs layer to can be used to scramble and descramble octet data, EMI is lowered with spread spectrum spike, data link layer deals link
Synchronous, foundation and holding, and the data after scrambling are carried out with 8b/10b codings or decoding, physical layer is responsible for bit rates at a high speed
Send and receive the character after coding.JESD204BB single channel rates are 10Gbps, which is encoded using 8b/10b, that is, are counted
8Gbps is up to according to transmission effective bandwidth, can support the transmission of ADC high-speed, high precision sampled datas.Utilize the IP of JESD204B
Core completes the function of scrambling layer, data link layer and physical layer, and passes through local transmission layer module by the defeated of JESD204B IP kernels
Go out data frame demapping to complex base band data sample, realize the data transmission of high speed fidelity.
Step 2. is multiplied to the first intermediate result by complex base band data spectrum and local reference signal frequency spectrum conjugate complex, the
One intermediate result does conjugate multiplication with range walk and FDC correction functions, obtains the second intermediate result, the second intermediate result is in side
Position is done conjugate complex with range curvature correction function after Fourier transformation is done and is multiplied, and obtains third intermediate result, third intermediate result
Conjugate multiplication is done with remaining migration correction function, inverse Fourier transform is done to the data that conjugate multiplication obtains, obtains distance to place
Manage data.
Different from ordinary radar imaging, biradical forward-looking radar imaging method of the present invention is apart from upward data processing
Four modules are corrected from distance to pulse compression, range walk and FDC correction, range curvature correction and remaining migration to complete.Its
The pulse of middle-range descriscent is compressed in distance and is completed to frequency domain orientation time domain, i.e., by the ADC complex base band data spectrums passed back and local
It after the frequency spectrum conjugate complex of reference signal multiplies, then does inverse Fourier transform and converts to obtain as a result, specifically, including coordinate rotation number
Word computational methods (CORDIC) operation Fourier transformation (FFT), multiplies, inverse Fourier transform (IFFT) again.
Due to biradical forward-looking radar imaging configuration, needed before inverse Fourier transform is done into row distance to school
Just.Wherein range walk and FDC corrections is completed in distance to frequency domain orientation time domain, will distance conjugate complex into pulse compression
Intermediate result after multiplying does conjugate multiplication with range walk and FDC correction functions, eliminates range walk and Doppler frequency center
Influence on RT is deviated, image is avoided to obscure, is multiplied including CORDIC operations and again；Range curvature correction is in distance to frequently
Domain orientation frequency domain is completed, i.e., by the intermediate result after range walk and FDC corrections after orientation does Fourier transformation with away from
Conjugate complex is done from curvature correction function to multiply, and is eliminated distance to influence on RT is bent, is avoided image defocus, including
CORDIC operations multiply, FFT again；Remaining migration correction is completed in distance to frequency domain orientation frequency domain, i.e., will be after range curvature correction
Intermediate result do conjugate multiplication with remaining migration correction function, inverse Fourier transform finally is done to the intermediate result of conjugate multiplication
Biradical forward-looking radar imaging device is completed apart from upward processing, including CORDIC operations, is multiplied again；Idiographic flow such as Fig. 2 institutes
Show.
Distance passes through four-way SRIO between FPGA and dsp chip after the completion of processing data are handled in fpga chip
Interconnection, SRIO are writing a Chinese character in simplified form for serial protocol Serial Rapid I/O, and SRIO single channel rates are 5Gbps, and using 8b/10b
Coding, valid data bandwidth are up to 16Gbps.
Distance is obtained in the step 2 after processing data, transmits data to the tool that DSP carries out step 3
Body transmission process can be：Distance is packaged into stream write packet to processing data, header packet information, the header packet information are set
Including Packet type, send address, doorbell information；DSP is sent to after packing, after having sent a frame data, sends doorbell number immediately
Subsequent processing is carried out according to packet notice DSP.
More than transmission process utilizes the serial RapidIO IP kernels that xilinx companies provide, and can design software form in advance
Resolve packet module and data packet packetization module, communication is using HELLO foramt（Logical layer packet header code optimization form,
Header Encoded Logical Layer Optimizated format）Stream write-in (swrite, stream write,
Stream is written) it wraps and is wrapped with doorbell data (doorbell), as shown in figure 4, what data decoder module sended over for reception from DSP
Data, data packing block are sent to DSP for distance to be packaged into stream write packet to pulse compressed data, have sent one
After frame data, send a doorbell data packet notice DSP and carry out subsequent processing.
When FPGA sends data to DSP, transmission caching is write the data to first, is opened after writing by transmission controller module
Dynamic signal；When sending data, header packet information is set, including Packet type, sends address, doorbell data information etc.；These packets
After the processing of IP kernel, DSP is transferred to by the stone high speed serialization transceiver built in FPGA.DSP gives FPGA transmission datas
When is also required to setting, and similarly these information, FPGA are cached to after receiving data in plug-in random access memory DDR3,
It is handled when needed in taking-up.
The SRIO modules at dsp chip end are formed by being loaded into, setting out module and physical layer block, are loaded into, are set out module in CPU
With EDMA mechanism（Enhanced direct memory access, Enhanced Direct Memory Access）Control under to appearance
DDR3 memories send VBUSM（Virtual multiple instructions performs bus, Virtual Bus Multi-issue）Request receives VBUSM
Response；It is being loaded into, setting out in module, MMR（Memory map registers, Memory Mapped Register）Command register
Device control send caching and order caching, and with the FIFO of physical layer（First in, first out, First Input First Output）
Memory is connected；In dsp chip, CSL is used（Chip Support Library, chip Support Library）On piece supports library function
The configuration of SRIO is realized, including enabling, initializing, opening and establishing communication functions；The realization of SRIO is divided into 4 steps：Address of cache,
Identity information is configured（ID）, SRIO ports, interrupt vector；Configuration register, the configuration including transmission mode and rate；Wait for chain
It connects, upon connecting, dsp chip can receive and send SRIO data packets, need to know between DSP and fpga core chip pair
The purpose identity information and true address of side could correctly transmit data；Input/output port direct connection is selected in data transmission
（DirectIO）Mode, value need the address mapping relation for sending and receiving data both sides that transmission can be realized.Wherein SRIO
（Serial Rapid I/O）Refer to the highly reliable of embedded system exploitation proposition, high-performance, new one based on packet switch
For high speed interconnection technique, ISO/ is approved as by International Organization for standardization (ISO) and International Power association (IEC) in 2004
18372 standards of IECDIS.
DSP receives distance after data, enters step 3, and distance is carried out higher order polynomial plan successively to processing data
It closes, non-linear become of orientation is marked（Non-Linear Chirp Scaling, NLCS is non-linear to become mark）, orientation high order phase filter
Wave, orientation are gone tiltedly（Dechirp, it is tiltedly a kind of matching pulse compress technique to go, and echo and one are believed with reference to linear frequency modulation
It number is mixed, then carries out Fourier transformation again, obtain the compression processing of echo）It is handled with geometric correction；It is formed and true
The distance figure that scene is combined.
Higher order polynomial-fitting module be obtained imaging space defined parameters k1, k2 needed for radar return imaging process,
K3, k4 and cubic perturbation factor beta.Wherein, k1 ~ k4 is round trip distance and heart point in the scene in biradical Forward-looking SAR model, with Thailand
1 item after series expansion is strangled to 4 this coefficients.Under the premise of 4 order polynomial series, fitting of a polynomial is carried out.If
Orientation phase does not generate space-variant effect with distance, then data can be handled according to unified change scalar functions.But by
In orientation phase also to distance to related.Therefore, the change scalar functions corresponding to each range cell are inconsistent.Orientation is non-thread
Property become mark using k1 ~ k4 coefficient of polynomial fitting, generate with the relevant change scalar functions of real scene space-variant effect, remove orientation
To with distance to space-variant effect.Coupled interference caused by orientation high order phase filtering removal cubic perturbation factor beta, orientation
Inclined module processing echo-signal is gone to form synthetic aperture radar echo.After orientation goes the processing of inclined module, original is returned
Quadratic term in wave signal phase is removed so that the energy of output signal is only concentrated in a certain single frequency.Geometry
Synthetic aperture radar echo by interpolated sample of layouting, is formed the distance being combined with real scene by correction process module
Figure.
The present invention gives full play to the Digital Down Convert function of analog-digital converter, field programmable gate array（FPGA）'s
The characteristics of efficient parallel and data rich interface and digital signal processor（DSP）To the powerful floating-point operation energy of big data quantity
Power realizes the purpose of biradical Forward-looking SAR high-resolution imaging；Using the system integrated framework of ADC+FPGA+DSP, quickly and effectively
Ground carries out extensive real-time operation.High-volume simple calculations（Such as：FFT）It is placed in FPGA and completes.DSP is allowed to complete multiple
Miscellaneous serial arithmetic（Such as：Matrix transposition, numerical fitting）.In this way, both ensure that the operational performance handled in real time, in turn ensure
The sustainability of exploitation.
DSP algorithm processing stage in step 3, there are two types of the modes of data processing：The processing of multinuclear cooperative cooperating and base
In the data processing method of the table tennis data transmission of EDMA3.
Wherein multinuclear cooperative cooperating tupe is based on using the TMS320C6678 chips of multicore architecture as DSP.It is first
First, by the use of core 0 as the hinge in data set.The required data for carrying out calculation processing can all pass to core 0 first；Then, core 0
As data distribution person, the data received are divided into 8 parts, 7 parts of data are distributed to 1 ~ core of core 7 by bus respectively.Then,
8 cores carry out identical calculating operation to the data that respective core receives respectively and handle.After the completion of 8 are assessed calculation, 1 ~ core of core 7 is each
Core 0 is aggregated by bus again from the result obtained.Finally, core 0 summarizes the data block result of calculation.This scheme of the present invention
Thinking is that 8 cores of TMS320C6678 chips is made to run identical program segment, and different data are handled.To reach section
Save time and improve the purpose of chip cpu busy percentage.This multinuclear cooperative cooperating process chart is as shown in Figure 6.
Another way is the data processing method of the table tennis data transmission based on EDMA3 data transfer engines.EDMA3 is
An efficient data transfer engine in DSP, structure are suitble to the high-speed transfer of data, and EDMA3 data transfer engines are transmitting
The method of synchronization, address saltus step, all become more flexible on triggering mode.EDMA3 data transfer engines can be in no CPU
In the case of participation, the data that DSP memory spaces are completed by EDMA3 controllers shift.Due to the LL2 built in DSP（Local
Level 2:Localized second stores）The arithmetic speed of static RAM is faster than the arithmetic speed of DDR3.And by institute
The data volume that need to be calculated is excessive, can only leave concentratedly in DDR3.The thinking of which is to utilize EDMA3 data transfer engines will
One fritter of the data of required calculating, is moved from DDR3 to LL2.Then, institute is carried out in LL2 static RAMs
The calculating needed.Finally, the result being calculated is moved back in DDR3 using EDMA3.Further, using ping-pong, in LL2
Two pieces of regions are opened up respectively in static RAM and DDR3.It carries out alternately moving and calculating step, forms assembly line
Work.This data processing method of the present invention can improve data processing speed.Table tennis based on EDMA3 data transfer engines
It is as shown in Figure 7 that the data processing data of data transmission flows to schematic diagram.
Ping-pong operation makes full use of the characteristics of FPGA and distance are to signal processing, and the mode of parallel computation can be selected to realize
Relevant processing procedure.In calculating process in dsp, the processing of multinuclear cooperative cooperating and the table tennis data based on EDMA3 are utilized
The data processing method of transmission.To improve the purpose of arithmetic speed, reach requirement of real-time.
Finally, DSP will be ultimately imaged data by network interface and be uploaded to host computer.
The above content is combine specific preferred embodiment to the further description of the invention made, it is impossible to assert this
The specific embodiment of invention is confined to these explanations.For those of ordinary skill in the art to which the present invention belongs,
The other embodiment obtained in the case where not departing from technical scheme of the present invention, should be included within the scope of the present invention.
Claims (10)
1. a kind of biradical Forward-looking SAR imaging methods of DSP+FPGA based on enhanced ADC, it is characterised in that：Include the following steps；
Step 1. the echo analog intermediate frequency signal that synthetic aperture radar receives is sampled and Digital Down Convert after answered
Complex base band data are transmitted to FPGA by base band data by serially sending form；
Step 2. is multiplied to the first intermediate result by complex base band data spectrum and local reference signal frequency spectrum conjugate complex, among first
As a result conjugate multiplication is done with range walk and FDC correction functions, obtains the second intermediate result；Second intermediate result is done in orientation
Conjugate complex is done with range curvature correction function to multiply, obtain third intermediate result after Fourier transformation；Third intermediate result and remnants
Migration correction function does conjugate multiplication, and inverse Fourier transform is done to the data that conjugate multiplication obtains, and obtains distance to processing data；
Distance is carried out the non-linear change mark of higher order polynomial-fitting, orientation, orientation high order by step 3. successively to processing data
Phase filtering, orientation go tiltedly to handle with geometric correction；Form the distance figure being combined with real scene.
2. biradical Forward-looking SAR imaging method as described in claim 1, it is characterised in that：In the step 1, in enhanced ADC
Middle realization Digital Down Convert.
3. biradical Forward-looking SAR imaging method as described in claim 1, it is characterised in that：In the step 2
Distance is obtained after processing data, DSP is transmitted data to and carries out step 3, specific transmission process is：
Distance is packaged into stream write packet to processing data, header packet information is set, the header packet information includes Packet type, sends ground
Location, doorbell information；DSP is sent to after packing, after having sent a frame data, after sending the notice DSP progress of doorbell data packet immediately
Continuous processing.
4. biradical Forward-looking SAR imaging method as described in claim 1, it is characterised in that：The step 3
By SRIO patterns into row data communication between middle DSP and FPGA.
5. biradical Forward-looking SAR imaging method as described in claim 1, it is characterised in that：The FPGA leads to
It crosses JESD204B agreements and carries out data receiver.
6. biradical Forward-looking SAR imaging method as described in claim 1, it is characterised in that：It is adjusted the distance in the step 3 to processing
Data are carried out data processing and are handled using multinuclear cooperative cooperating；
Specially：By the data transfer in need for carrying out calculation processing to hinge core；Hinge core is by data distribution to multiple places
Core is managed, after the completion of processing, the result respectively obtained is aggregated into hinge core by each process cores；Hinge core summarizes result of calculation.
7. biradical Forward-looking SAR imaging method as described in claim 1, it is characterised in that：It is adjusted the distance in the step 3 to processing
Data carry out the data processing method that data processing uses the table tennis data transmission based on EDMA3；Specially：It is built-in in DSP
LL2 static RAMs and DDR3 registers in open up two pieces of regions respectively, using ping-pong carry out alternately remove
The flow work for moving and calculating, wherein LL2 static RAMs are as data processor, DDR3 register conducts
Data buffer storage device.
8. a kind of biradical Forward-looking SAR imaging devices of DSP+FPGA based on enhanced ADC, including network interface chip, which is characterized in that
Further include analog-digital converter, FPGA and DSP；Between the analog-digital converter and FPGA data link and support JESD204B lead to
Believe agreement；The analog-digital converter has been internally integrated digital down converter, mutual using multichannel SRIO between the FPGA and DSP
Connection, the DSP be multinuclear digital signal processor, further include two respectively in the arbitrary access of FPGA and DSP data connections
It deposits, data connection between the network interface chip and DSP.
9. biradical Forward-looking SAR imaging device as claimed in claim 8, it is characterised in that：The DSP be TMS320C6678, institute
It is the XC7VX690T in Xilinx companies Virtex-7 series to state FPGA, and the analog-digital converter is the ADS54J66 of TI companies.
10. biradical Forward-looking SAR imaging device as claimed in claim 8, it is characterised in that：The network interface chip is public for MAXIM
The 88E1111 ethernet physical layer chips of department.
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