CN108122886A - The method of integrated circuit two-dimensional interconnection - Google Patents

The method of integrated circuit two-dimensional interconnection Download PDF

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Publication number
CN108122886A
CN108122886A CN201710395335.1A CN201710395335A CN108122886A CN 108122886 A CN108122886 A CN 108122886A CN 201710395335 A CN201710395335 A CN 201710395335A CN 108122886 A CN108122886 A CN 108122886A
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dimensional
layer
dielectric
conducting wire
interconnection
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CN201710395335.1A
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CN108122886B (en
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吴佳典
刘相玮
杨岱宜
朱韦臻
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure

Abstract

This exposure discloses integrated circuit with two dimension (two dimensional；2 D) and one-dimensional (one dimensional；1 D) pattern layout interconnection.This exposure is provided via the two-dimensional interconnection on y directions come the even lines being connected on the x directions of one-dimensional patterns layout or the method for odd lines.Needs are designed according to device, two-dimensional interconnection can perpendicular to or be not orthogonal to even lines or odd lines.More patterning (self aligned multiple patterning are automatically aligned to compared to the routine used in one-dimensional patterns processing procedure；SAMP) processing procedure provides two-dimensional patterned degree of freedom.It is described herein two-dimensional patterned to provide and the matched line width of critical dimension on both x and y direction.Spacing between one dimensional line or between two-dimensional interconnection and the tail end of one dimensional line can remain constant and minimum value.

Description

The method of integrated circuit two-dimensional interconnection
Technical field
The embodiment of the present invention is on a kind of method of integrated circuit two-dimensional interconnection.
Background technology
In general, integrated circuit (integrated circuits；ICs each device formed on substrate) is included in, Such as transistor, capacitor etc..Front-end process (Front-end-of-line；FEOL it is) first portion of IC manufactures, and it is each A device (transistor, capacitor, resistor etc.) is patterned in wafer.Back-end process (Back end of line； BEOL it is) second portion of IC manufactures, and each device interconnects on wafer with electric wire or metal layer.It includes connecting It touches, the junction that metal layer and chip are connected to packaging.
As technology develops, IC characteristics are that the opposite size requirement with prior-generation device constantly reduces.However, this ruler Reduction on very little is subject to the photolithography tools used in the manufacture of device to be limited.By photolithography tools manufacture feature and The minimum dimension of spacing depends on the analytic ability of instrument.Alternative may be present to increase analytic ability and reduce minimum pitch (for example, summation of the width of spacing between characteristic size and feature)；However, this methods of cannot also provide it is enough critical Size.Furthermore the usual efficiency of method for reducing pattern magnitude is low, such as increases cost and the time of device manufacturing.
The content of the invention
According to the multiple embodiments of this exposure, a kind of method of integrated circuit two-dimensional interconnection, which includes, provides substrate；On substrate It is square into multiple dielectric structures with multiple the first side walls, wherein at least one first dielectric structure of dielectric structure and second be situated between Electric structure is parallel to each other；A part for the first dielectric structure is removed to form multiple second sidewalls, wherein removing part has width Degree, width is about three times of critical dimension；Spacer is formed on the first side wall and second sidewall；Remove dielectric structure； Not by forming multiple grooves in the region of the substrate of spacer protection, wherein groove has the width for being approximately equal to critical dimension； And conductive material is set in the trench to form multiple conducting wires, wherein at least one first conducting wire of conducting wire and the connection of the second conducting wire It is but not parallel each other.
Description of the drawings
When read in conjunction with the accompanying drawings, from the aspect described in detail below for being best understood by this disclosure.It should be noted that basis Convention in industry, each feature are not drawn on scale.In fact, in order to illustrate and discuss it is clear, the size of each feature can be arbitrarily Increase or reduce.
The part manufacture, the demonstration that are suitable for the integrated circuit with the limited layout of orientation of some embodiments according to Figure 1A Property be electrically interconnected arrangement top view；
Figure 1B is the sectional view that the exemplary electrical interconnection manufactured along the part of line A-A Figure 1A intercepted is arranged；
The exemplary electrical interconnection arrangement of the manufacture of the part after photolithographic processes of some embodiments according to Fig. 2A Top view；
Fig. 2 B are the exemplary electrical interconnection cloth that the part of Fig. 2A intercepted along line B-B after photolithographic processes manufactures The sectional view put；
The part of Fig. 2A intercepted along line A-A after spacer deposition processing procedure of some embodiments according to Fig. 3 A The sectional view of the exemplary electrical interconnection arrangement of manufacture；
The part of Fig. 2A intercepted along line B-B after spacer deposition processing procedure of some embodiments according to Fig. 3 B The sectional view of the exemplary electrical interconnection arrangement of manufacture；
The exemplary electrical interconnection cloth of the part manufacture after spacer layer removes processing procedure of some embodiments according to Fig. 4 The top view put；
Fig. 5 A to Fig. 5 B are after spacer removes processing procedure, respectively along the part of line A-A and line B-B Fig. 4 intercepted The sectional view of the exemplary electrical interconnection arrangement of manufacture；
According to Fig. 6 A to Fig. 6 B some embodiments dielectric structure remove processing procedure after respectively along line A-A and line B- The sectional view of the exemplary electrical interconnection arrangement of the part manufacture of Fig. 4 of B interceptions；
Respectively along line A-A and line after the groove of formation between the spacers of some embodiments according to Fig. 7 A to Fig. 7 B The sectional view of the exemplary electrical interconnection arrangement of the part manufacture of Fig. 4 of B-B interceptions；
Some embodiments is using conductive material filling groove and then grinding and planarization top surface according to Fig. 8 The top view of the exemplary electrical interconnection arrangement of part manufacture afterwards；
Some embodiments is using conductive material filling groove and then grinding and planarization according to Fig. 9 A to Fig. 9 B After top surface, respectively along the sectional view arranged of the exemplary electrical interconnection that manufactures of part of line A-A and line B-B Fig. 8 intercepted；
The exemplary embodiment that the electrical interconnection that the conducting wire of some embodiments is formed with wanted angle according to Figure 10 is arranged Top view；
Figure 11 is the exemplary process suitable for having the formation of the integrated circuit of the limited layout of orientation that arrangement is electrically interconnected Flow chart.
Specific embodiment
Content disclosed below provides many different embodiments or examples, is used to implement the different spies of provided subject matter Sign.The specific example of component and arrangement is described below to simplify this disclosure.Certainly, these are only example and are not intended to limit System.For example, the formation of fisrt feature may include first above second feature or in second feature in subsequent description And second feature be formed as the embodiment contacted directly and also may include additional features may be provided at first and second feature it Between so that the embodiment that first and second feature can be not directly contacted with.In addition, this disclosure repeats element in each example Symbol and/or letter.This repetition is for simplicity and clearly purpose, and do not indicate that each embodiment discussed in itself And/or the relation between configuration.
Further, for ease of description, herein can be used space relative terms (such as " under ", " lower section ", " under Portion ", " top ", " top " and fellow) a depicted element or feature and another element (or multiple members are described in all figures Part) or feature (or multiple features) relation.In addition to the discribed orientation of all figures, space relative terms are intended to comprising use Or device is differently directed in operation.Equipment can be oriented through other modes and (is rotated by 90 ° or in other orientations), therefore can be same Sample understands relativity descriptor in space used herein.
The component or processing that " nominal " instruction of term as used herein is set during the design phase of product or processing procedure The feature of operation and parameter to be worth or desired value and be higher than and/or less than the large-scale numerical value to be worth.Numerical value model Enclose the slight change being commonly due in manufacture processing procedure or tolerance.
It is provided according to the various embodiments of this exposure and is produced in integrated circuit one-dimensional (1-D) pattern layout, such as metal wire The method of raw two dimension (2-D) interconnection.Two-dimentional and one-dimensional term refers to the direction of circuit layout rather than the thickness of conducting wire or width.When The minimum dimension of layout patterns close to lithographic limit when, pure one-dimensional placement be commonly used as patterning solution.However, it originally takes off The two-dimensional interconnection of dew description provides the two-dimensional patterned degree of freedom in one-dimensional placement patterning.Specifically, one-dimensional Even lines or odd lines on the x directions of pattern layout can be connected via the two-dimensional interconnection on y directions.Need are designed according to device Will, two-dimensional interconnection can be connected to even lines or odd lines perpendicular to even lines or odd lines or to be less than 90 degree of angle.Root The analytic ability that currently available one-dimensional patterns are laid out is extended to according to the method for this exposure two-dimensional patterned.According to this exposure Two-dimensional patterned degree of freedom in the multi-exposure pattern processing procedure that various embodiment offers use in one-dimensional patterns.It is all Such as it is automatically aligned to double patterning (self-aligned double patterning；SADP four patternings are automatically aligned to) or (self-aligned quadruple patterning；Being automatically aligned to SAQP) patterns (self-aligned more multiple patterning；SAMP) allow to reduce feature spacing compared to single exposure technique.Such as SADP's is automatically aligned to Patterning techniques improve the pattern variability compared with other multiple exposure techniques, such as variable by excluding some shade overlays Photoetching-etching-photoetching-etching (litho-etch-litho-etch of property；LELE).
According to the method for this exposure benefit for even number or the line width of odd lines and two-dimensional interconnection can be configured with Critical dimension with SAMP processing procedures.
It is only to need minimum area that can obtain the two dimension between one dimensional line mutually according to another benefit of the method for this exposure Between company and one dimensional line or the spacing between two-dimensional interconnection and the tail end of one dimensional line can remain constant minimum value.Constant is minimum Spacing can be with the critical dimension of SAMP processing procedures or low as the parsing limit of this isostructural lithography apparatus for manufacturing.For example, Critical dimension can be for 5 nanometers or no more than 30 nanometers.It is that can also be hindered in spite of overlay influence that constant minimum spacing, which also provides benefit, The only leakage between Line To Line.When apply the voltage on electrical insulator be more than its breakdown voltage when, the line of such as dielectric breakdown Insulation bulk resistor can be reduced to the leakage of line.Line To Line leakaging cause can be inter-metal dielectric (inter-metal dielectric；IMD breakdown) and leakage current in adjacent line can be caused.Line To Line leakage problem annoyings reduction geometry always The manufacturer of the device of size.
It is provided in the ability based on the two dimensional topology in one-dimensional patterns and increases logic density and reduction in integrated circuits The further benefit of metal layer stack.These benefits are very useful in transmission grid or closing circuit, wherein two-dimensional interconnection height Favorably.The example of circuit is closed as phase inverter latch circuit, wherein the output of inverter circuit is through being connected to another phase inverter electricity The input on road.Using such method, the size of the logic unit containing transmission grid can reduce in y-direction.
Figure 1A to Fig. 8 provides the various views of the integrated circuit of the operation of diagram two-dimensional interconnection manufacture.Provided herein is system Processing procedure is made to be exemplary, and the executable replacement processing procedure (not illustrated in these schemas) on this exposure.
Figure 1A is the vertical view of the integrated circuit 100 with hard mask layer 115 and dielectric structure 109a to dielectric structure 109c Figure.Hard mask layer 115 is partially exposed between adjacent dielectric structure 109a, dielectric structure 109b and dielectric structure 109c, and With the width W that may be about at least three times equal to critical dimensionT.Each dielectric structure has can be as critical dimension It is low, such as 5 nanometers or the width W no more than 30 nanometersL.The hard of more dielectric structures and the exposure formed on substrate may be present Mask regions, but it is not shown for the sake of simplicity.
Figure 1B is the sectional view along the integrated circuits 100 intercepted of the line A-A in Figure 1A.It is cutd open along what the line B-B of Figure 1A was intercepted Face is identical.Substrate 101 can include doping or non-impurity-doped block silicon or silicon-on-insulator (silicon-on-insulator；SOI) The active layers of substrate.In general, SOI substrate is multilayer silicon-on-insulator-silicon substrate.Alternatively, such as germanium, SiGe or its combination Other semi-conducting materials can be square into active layers on insulator.Other workable substrates include multilager base plate, gradient base Plate or hybrid orientation substrate.
Aggressive device can be formed on the substrate 101 and/or in substrate 101.Such as transistor, diode, capacitor, electricity A variety of actives of resistance device, inductor etc. and passive device can be used to implement to want circuit.Can be used any suitable method or Aggressive device is formed on the surface of substrate 101 or in the surface of substrate 101.These devices simplification figure 1B is saved, with more preferable Ground understands this exposure.
Quasi- interconnection (the multi-level interconnect of multidigit；MTI) layer 103 forms and on the substrate 101 through design Functional circuit is formed to connect various aggressive devices.Although being illustrated as individual layer in fig. ib, the quasi- interconnection layer 103 of multidigit can wrap Alternating layer containing dielectric material and conductive material can simultaneously come via any suitable processing procedure (deposit, inlay, dual-inlaid etc.) It is formed.
First dielectric layer 105 is formed above the quasi- interconnection layer 103 of multidigit.In various embodiments, according to selected materials, One dielectric layer 105 can be the dielectric material formed using deposition or spin coating processing procedure.For example, the first dielectric layer 105 is by dielectric material Composition, and by silica, silicon nitride, silicon oxynitride, Fluorin doped silicate glass (fluorine-doped silicate glass；FSG), low-k dielectric material, SiCxOyNz(x, y, z=0~n) and/or other suitable insulating materials are formed. However, it can or utilize other any suitable dielectric materials formed using other any applicable process.
Conductive region 107 is formed in opening in the first dielectric layer 105.In various embodiments, conductive region 107 is The region being electrically connected will be generated with interconnection (do not illustrate in fig. ib but illustrate and describe below with reference to Fig. 9 A to Fig. 9 B).Multiple In embodiment, conductive region 107 is the conducting wire formed by such as copper, although being alternatively utilized other any suitable conductive materials Material.Damascene process can be used to be formed in conductive region 107, and the part of the first dielectric layer 105 is removed by this processing procedure and is made to be formed The opening filled with conductive material.
Second dielectric layer 111 and hard mask layer 115 are formed above 107 and first dielectric layer 105 of conductive region.It is similar to First dielectric layer 105 as described above, the second dielectric layer 111 are made of dielectric material, and can be by silica, silicon nitride, nitrogen oxygen SiClx, Fluorin doped silicate glass (fluorine-doped silicate glass；FSG), low-k dielectric material, SiCxOyNz(x, y, z=0~n) and/or other suitable insulating materials are formed.Hard mask layer 115 is made of dielectric material, such as Silica, silicon nitride, titanium nitride, silicon, titanium oxide, tungsten carbide, SiCxOyNz(x, y, z=0~n) and/or other suitable insulation Material.
Dielectric structure 109a to dielectric structure 109c is the fin shapes nonmetal structure formed above hard mask layer 115 And with height HLAnd width WL.According to device needs, height HLIt can be about 1 to 3 times and width W of critical dimensionLIt can be with facing Ungraduated ruler cun is equally low.Each dielectric structure has the side wall on the surface for being approximately orthogonal to hard mask layer 115.Dielectric structure spacing WT For at least three times of critical dimension.Dielectric structure 109a to dielectric structure 109c is made of nonmetallic dielectric material, such as is aoxidized Silicon, silicon nitride, titanium nitride, silicon, titanium oxide, tungsten carbide, SiCxOyNz(x, y, z=0~n) and/or other suitable insulating materials.
First dielectric layer 105, the second dielectric layer 111, hard mask layer 115 and dielectric structure 109a to dielectric structure 109c can Pass through chemical oxidation, thermal oxide, atomic layer deposition (atomic layer deposition；ALD), chemical vapor deposition (chemical vapor deposition；CVD) and/or other are formed suitable for forming processing procedure.Or appoint using using Other any suitable dielectric materials that one other applicable process are formed.Other processing procedures can be comprised in be formed in processing procedure, such as light Micro-photographing process is defining dielectric structure 109a to dielectric structure 109c and chemical mechanical grinding (chemical mechanical polishing；CMP) processing procedure can be used to planarize selected surface.
Note that two-dimensional interconnection is formed in integrated circuit 100 can be not necessarily required to the quasi- interconnection layer 103 of multidigit, the first dielectric Layer 105, conductive region 107, the second dielectric layer 111 and hard mask layer 115.
Fig. 2A is the integrated circuit 100 after the part for having used light lithography and etch process removal dielectric structure 109b Top view.The exemplary optical micro-photographing process for removing the part of dielectric structure 109b is included in the surface shape of integrated circuit 100 Into photoresist layer, by resist exposed to having figuratum cutting shade on it, perform post-exposure baking processing procedure and development is against corrosion Agent is to form the shade element including resist.It is not used by the region of the dielectric structure 109b of shade element protection and for example reacted Property ion(ic) etching (reactive ionetching；RIE) processing procedure and/or other applicable process etch.Photoresist layer is then by appointing Meaning peels off processing procedure to remove suitable for resist.The part that removes of dielectric structure 109b can be at least three times for critical dimension Width WC.Furthermore the pattern that can be generated with wanted angle on cutting shade causes on the tail end of remaining dielectric structure 109b Side wall is compared with conducting wire 119b or 119d into wanted angle (from top view).According to some embodiments, angle that can be 90°。
Fig. 2 B are the sectional view along the integrated circuits 100 intercepted of the line B-B in Fig. 2A.As shown in Fig. 2 B, dielectric knot is removed The part of structure 109b, and during processing procedure is removed, hard mask layer 115 is used as etch stop.
After Fig. 3 A and Fig. 3 B deposit for spacer layer 117 on the surface of integrated circuit 100, respectively along the line in Fig. 2A The sectional view of the integrated circuit 100 of A-A and line B-B interceptions.Spacer layer 117 is isotropically deposited at integrated circuit 100 On exposed surface, the top surface of exposed surface and dielectric structure 109a including hard mask layer 115 to dielectric structure 109c and Side surface.Spacer layer 117 is comparably formed on the exposed surfaces, and its thickness is equal to or more than critical dimension.Spacer layer 117 can be by titanium oxide, silica, silicon nitride, titanium nitride, SiCxOyNz(x, y, z=0~n) and/or other suitable for insulation material shape Into.Spacer layer 117 can by chemical oxidation, thermal oxide, atomic layer deposition (ALD), chemical vapor deposition (CVD) and/or its He forms suitable for forming processing procedure.Or using other any suitable dielectric materials that other any applicable process is used to be formed Material.Spacer layer, hard mask layer and dielectric structure preferably are made of to provide for subsequent removal processing procedure different materials Different etching selectivities.
Fig. 4 is the top view of the integrated circuit 100 after the part for removing processing procedure removal spacer layer 117 has been used. Spacer layer 117 is anisotropically etched back in the vertical direction compared with substrate surface, so as to be formed adjacent to dielectric structure The spacer 117s of each side wall of 109a to dielectric structure 109c.This mainly realizes via anisotropic etching processing procedure, Divider layer 117 is more faster than in horizontal direction in vertical direction compared with the etching of substrate surface.Between being formed The material of parting layer 117, this etch process are realized via suitable plasma or wet chemical etch.After processing procedure is removed, Spacer 117s is existed only on the side wall of dielectric structure 109a, dielectric structure 109b and dielectric structure 109c.Configurable interval The deposition and etch process of nitride layer 117 cause the width W of spacer 117sSEqual to critical dimension.Such as above for Figure 1A to figure 1B and 2A to Fig. 2 B is discussed, spacing WTAnd spacing WCThe two is approximately equal to three times of critical dimension, and because each spacer 117s has the width W for being approximately equal to critical dimensionS, so the hard mask layer 115 of the exposure between spacer 117s has There is the width W for being also approximately equal to critical dimensionL。
Fig. 5 A and Fig. 5 B are the sectional view that integrated circuit 100 intercepts respectively along the line A-A in Fig. 4 and line B-B.As above articles and opinions It states, spacer layer 117 is anisotropically etched back in the vertical direction compared with substrate surface, so as to form spacer 117s. The deposition and etch process of configurable interval nitride layer 117 cause the width W of spacer 117sSEqual to critical dimension.Due to etching Processing procedure, the height of spacer 117s can be slightly less than dielectric structure 109a to the height of dielectric structure 109c.Spacer 117s it Between exposure hard mask layer 115 part.
In fig. 5, by adjusting dielectric structure spacing and deposition/etch process of spacer layer 117, in spacer layer After 117 etch process, the expose portion of hard mask layer 115 may have about the width equal to critical dimension.
In figure 5B, because removing the part of dielectric structure 109b, hard mask layer 115 will be exposed to dielectric structure Between 109a and the spacer 117s of dielectric structure 109c and between the spacer 117s of remaining dielectric structure 109b.
Fig. 6 A and Fig. 6 B are respectively along line A-A in Fig. 4 after dielectric structure 109a to dielectric structure 109c is removed And the sectional view of the integrated circuit 100 of line B-B interceptions.According to dielectric structure material, using any suitable etch process, including but Plasma etching or wet chemical etch are not limited to remove dielectric structure 109a to dielectric structure 109c.Etch process selectivity It etches away dielectric structure material and hard mask layer 115 is used to be used as etch stop.Removing processing procedure also may include photolithographic processes.
Fig. 7 A and Fig. 7 B are in the second dielectric for removing the part of hard mask layer 115 and being exposed between spacer 117s Respectively along the sectional view of the line A-A in Fig. 4 and line B-B integrated circuits 100 intercepted after the part of matter 111.Using in Fig. 6 A And the spacer 117s illustrated in Fig. 6 B performs one or more as etching shade on the exposed region between spacer 117s Etch process.Thus, the pattern formed by spacer 117s is after through being transmitted on hard mask layer 115 and extending through second Jie Electric layer 111.Etch process can be continued until exposes the first dielectric layer 105 and conductive region 107 at least partly.It is made according to etching Journey, the angle of sides of remaining 115 and second dielectric layer 111 of hard mask layer vertically or can be approximately perpendicular to the first dielectric layer 105.Erosion It scribes journey and generates the groove 701 formed between remaining second dielectric 111 and the abutment post of hard mask layer 115.
Fig. 8 is the integrated circuit after conductive material is used to fill groove 701 and then grinding and planarization top surface 100 top view.
Filling processing procedure may begin at the processing procedure that adds the cushions (not illustrating in fig. 8), wherein side wall and bottom of the laying along groove 701 Portion is formed.Plasma reinforced chemical vapour deposition (plasma enhancedchemical vapor can be used in laying deposition；PECVD) processing procedure is formed, although other applicable process, such as physical vapour deposition (PVD) or heat is alternatively used Processing procedure.
Once laying is formed along the side wall and bottom of groove 701, then conducting metal can be used to fill for groove 701.It is conductive Material can include copper, although it is alternative using such as aluminium, alloy, DOPOS doped polycrystalline silicon, above-mentioned each combination etc. other are suitable Suitable material.Conductive material is formed by the electro-coppering on seed layer (not shown) and filling groove 701.Once fill groove 701, although any suitable can be used to remove processing procedure, but it is removed via the planarization process of such as CMP outside groove 701 Extra pad, seed layer and conductive material.During this planarization process, also removable remaining hard mask layer 115, so as to exposure The second beneath dielectric layer 111.
Filling processing procedure forms conducting wire 119a to conducting wire 119e in groove 701.As shown in Fig. 8, conducting wire 119a to conducting wire 119e in the x direction and can be divided into odd lines 119a, odd lines 119c and odd lines 119e and even lines 119b and even lines 119d.It should be noted that definition the being merely to illustrate property purpose of this paper odd lines and even lines.Each conducting wire, which may have about to be equal to, to be faced The width W of ungraduated ruler cunL.Fig. 8 illustrates even lines 119b and even lines 119d via interconnection 119y electrical connections.Conductive interconnection 119y Connection is being provided on the y directions of x directions conducting wire 119b and conducting wire 119d.As described above, spacer 117s and dielectric knot Each width W of structure 109bSAnd WLThe two is approximately equal to critical dimension.Therefore, connected at them by conductive interconnection 119y outer Spacing between the parallel portion of the conducting wire 119b and conducting wire 119d in portion is approximately equal to three times of critical dimension.It is if for example, critical Size is equal to 5 nanometers, then the spacing between conducting wire 119b and conducting wire 119d will be 15 nanometers.
Fig. 9 A and Fig. 9 B be use conductive material fill groove 701 and then grinding and planarization top surface after, Respectively along the sectional view of the line A-A in Fig. 8 and line B-B integrated circuits 100 intercepted.It is such as discussed above for Fig. 8, fills processing procedure Can be since the processing procedure that adds the cushions (not illustrated in Fig. 9 A or Fig. 9 B), wherein laying is formed along the side wall and bottom of groove 701. Then pass through the first dielectric layer 111 using conducting metal filling groove to form conducting wire 119a to conducting wire 119e and adjacent conductor To separate.However, in figures 9 b and 9, conductive interconnection 119y is on the y directions between the even lines 119b in x directions and even lines 119d Electrical connection is provided.
It is such as discussed above for Fig. 8, the planarization process of such as CMP is removing extra laying, the seed outside groove Crystal layer and conductive material.As shown in Fig. 9 A and Fig. 9 B, hard mask layer 115 is also removed in this processing procedure, so as to the second dielectric of exposure The top surface of layer 111.Due to this planarization process, conducting wire 119a to conducting wire 119e, conductive interconnection 119y and the second dielectric layer 111 Top surface it is substantially coplanar.Furthermore conducting wire 119a to conducting wire 119e, conductive interconnection 119y are in same metallization level.
Furthermore when forming groove to expose conductive region 107 at least partly, conducting wire 119a to conducting wire 119e and conduction An at least subclass of interconnection 119y is electrically connected to conductive region 107, so as to provide electricity between multiple layers of integrated circuit 100 Connection.
Figure 10 for the integrated circuit 100 with the conductive interconnection 119y formed with conducting wire into wanted angle top view.Such as Discussed above, conductive interconnection 119y can be perpendicular to conducting wire 119b or conducting wire 119d, as shown in Figure 8.However, generating cutting shade makes It is also possible to obtain conductive interconnection 119y opposing leads 119b or conducting wire 119d and form angle, θ.According to device needs, angle, θ can Arbitrarily to be wanted angle, include but not limited to 45 ° or 60 °.This can by cutting shade on generate want the pattern of angle come Reach so that angle is turned into the side wall on the tail end of remaining dielectric structure 109b.
Figure 11 is the flow chart for the illustrative method 1100 to form integrated circuit two dimension conductive interconnection.Methods provided herein To be exemplary.It can perform other operations in an alternative embodiment and save here for the sake of simplicity.It can be with different order It performs operation or is not performed according to specific application.
Method 1100 starts since operation 1102, and providing has on it and/or structure formed therein that and layer are partly led Structure base board.Semiconductor substrate can include doping or the active layers of undoped block of silicon or silicon-on-insulator (SOI) substrate.Semiconductor Substrate can include semi-conducting material, such as silicon, germanium, SiGe, sige-on-insulator (silicon germanium on insulator；SGOI) or it is combined.
Aggressive device can be formed on a semiconductor substrate and/or in semiconductor substrate.Such as transistor, diode, electricity Structure is wanted in the design that a variety of actives of container, resistor, inductor etc. and passive device can be used to generate integrated circuit And functional requirement.
The quasi- interconnection layer of multidigit is formed above semiconductor substrate and aggressive device, and is configured to connect various aggressive devices To form circuit.The quasi- interconnection layer of multidigit can be formed by the alternating layer of dielectric material and conductive material and can be via any suitable processing procedure It is formed.
First dielectric layer is formed in metallization layer.First dielectric layer can be made of dielectric material, this dielectric material bag Silicon oxide-containing, silicon nitride, silicon oxynitride, Fluorin doped silicate glass (FSG), low-k dielectric material, SiCxOyNz(x, Y, z=0~n) and/or other suitable insulating materials.
Conductive region is formed in opening in the first dielectric layer.Conductive region is to interconnect the region of electrical connection.It is conductive Region is as the conducting wire made by such as copper, although being alternatively utilized other any suitably electrically conductive materials.Conductive region can make It is formed with damascene process.
Second dielectric layer and hard mask layer are formed in conductive region and the first dielectric layer.Second dielectric layer is by dielectric material Made by material, such as, but not limited to silica, silicon nitride, silicon oxynitride, Fluorin doped silicate glass (FSG), low-k Dielectric material, SiCxOyNz(x, y, z=0~n) and/or other suitable insulating materials.Hard mask layer as made by dielectric material, Such as, but not limited to silica, silicon nitride, titanium nitride, silicon, titanium oxide, tungsten carbide, SiCxOyNz(x, y, z=0~n) and/or Other suitable insulating materials.
Dielectric structure is the dielectric structure of the fin shapes formed above hard mask layer.According to device needs, they Highly may be about critical dimension one again to three times and width can as critical dimension it is small.Dielectric structure spacing is critical ruler Very little at least three times.Dielectric structure is as made by nonmetallic dielectric material, such as silica, silicon nitride, titanium nitride, silicon, oxidation Titanium, tungsten carbide, SiCxOyNz(x, y, z=0~n) and/or other suitable insulating materials.
The structure and layer formed on a semiconductor substrate can pass through chemical oxidation, thermal oxide, atomic layer deposition (ALD), change Vapor deposition (CVD) and/or other suitable formation processing procedures are learned to be formed.Or using using other any applicable process Other any suitable dielectric materials formed.Other processing procedures can be comprised in be formed in processing procedure, such as photolithographic processes or CMP Processing procedure.
Method 1100 continues operation 1104, and the part of dielectric structure is removed using micro-photographing process and etch process.It is moving Except during processing procedure, hard mask layer is used as etch stop.More than one dielectric structure can be subjected to this removal processing procedure to form one More than conductive interconnection.
The part that removes of dielectric structure can be at least width of three times critical dimension and the tail end in remaining dielectric structure On side wall compared with conducting wire into desired angle.For example, side wall on the tail end of remaining dielectric structure can perpendicular to conducting wire, Or in another example, they can be into a certain angle of non-90 degree, such as, but not limited to 30 °, 45 ° or 60 °.
Method 1100 continues operation 1106, the disposable spacer nitride layer on the surface of integrated circuit.Spacer layer isotropism Ground is deposited on the exposed surface of integrated circuit, the top surface of exposed surface and dielectric structure including hard mask layer and side table Face.Spacer layer comparably deposits on the exposed surfaces, and its thickness is equal to or more than critical dimension.
Method 1100 continues operation 1108, is formed adjacent to the spacer of each side wall of dielectric structure.This can be via each The spacer layer in the vertical direction compared with substrate surface is etched back to anisotropy to reach.After processing procedure is removed, spacer It only occurs on the side wall of dielectric structure.The deposition and etch process of configurable interval nitride layer cause the width of spacer about etc. In critical dimension.Therefore, the hard mask layer of the exposure between spacer has the width for being approximately equal to critical dimension.It is grasping Making the tail end of remaining dielectric structure formed in 1104 also has a spacer being formed on, and this spacer is by about etc. It is separated in the distance of critical dimension.
Method 1100 continues operation 1110, and dielectric structure is removed using suitable etch process.Etch process is according to dielectric Structural material includes but not limited to plasma etching or wet chemical etch.Etch process selective etch falls dielectric structure material And hard mask layer is used as etch stop.
Method 1100 continues operation 1112, is situated between by the part and second that remove the hard mask layer of exposure between the spacers Electric matter forms groove.Using spacer as etching shade, one or more erosions are performed on exposed region between the spacers Scribe journey.Thus, the pattern formed by spacer is after through being transmitted on hard mask layer and extending through the second dielectric layer.Etching Processing procedure can be continued until exposes the first dielectric layer and conductive region at least partly.Etch process is generated in remaining second dielectric layer And the groove formed between the abutment post of hard mask layer.
Method 1100 continues operation 1114, and groove and then grinding and planarization top surface are filled using conductive material.It fills It fills and presents the Cheng Kecong processing procedures that add the cushions to start, wherein side wall and bottom along groove forms laying.Laying once being formed, ditch Slot can fill conducting metal, such as copper.Conductive material can by the electro-coppering on seed layer and filling or excessively filling groove come It is formed.Once groove has been filled or excessively filled, then can extra pad, the seed layer outside groove be removed by planarization process And conductive material.During this planarization process, also removable remaining hard mask layer, so as to expose the second beneath dielectric layer.
Filling processing procedure forms conducting wire and conductive interconnection in the trench.Only here using term wire and conductive interconnection with area Point x direction lines and y direction lines and they formed using identical material and via same process.Conducting wire and conductive interconnection difference In the x direction and on y directions, and the width with equal to critical dimension.In this way, it is electrically connected via conductive interconnection strange Number conducting wire or even number conducting wire.As discussed above, conductive interconnection can be formed perpendicular to conducting wire or in wanted angle.
It is provided according to the various embodiments of this exposure and generates two-dimensional interconnection cloth in the one-dimensional patternsization layout of integrated circuit The method of office.Specifically, the even number on the x directions of one-dimensional patternsization layout or odd lines can be via the two dimensions on y directions It interconnects to connect.Two-dimensional interconnection can perpendicular to even number or odd lines or compared with even number or odd lines into wanted angle.Compared to The conventional SAMP processing procedures used in one-dimensional patterns processing procedure provide two-dimensional patterned degree of freedom according to the method for this exposure. It can be configured to match often for the line width of both even number or odd lines and two-dimensional interconnection according to the method for this exposure benefit Advise the critical dimension of SAMP processing procedures.According to another benefit of the method for this exposure for only need minimum area reach one dimensional line it Between two-dimensional interconnection and one dimensional line between or the spacing between two-dimensional interconnection and the tail end of one dimensional line can remain constant and minimum Value.Constant minimum spacing can be with the critical dimension of SAMP processing procedures or for manufacturing the semiconductor structure in this exposure lithography apparatus The parsing limit it is equally low, for example, critical dimension can be 5 nanometers.It is in spite of overlay shadow that constant minimum spacing, which also provides benefit, Ring the leakage that can also prevent between Line To Line.
It is provided in the ability based on the two dimensional topology in one-dimensional patterns and increases logic density and reduction in integrated circuits The further benefit of metal layer stack.For example, in transmission grid or cut-out circuit, wherein two-dimensional interconnection is favourable.It uses Such method, the size of the logic unit containing transmission grid can reduce in y-direction.
In various embodiments, method includes providing substrate and forms multiple dielectric structures in this surface, wherein this Dielectric structure has side wall.At least first and second dielectric structure of multiple dielectric structures is set so that they are parallel to each other.It moves Except the part of the first dielectric structure with the part for forming second sidewall and removing is of approximately the width of three times critical dimension. Spacer is formed on first and second each side wall, and removes multiple dielectric structures.In the substrate do not protected by multiple spacers Region in form groove, and this groove has the width for being approximately equal to critical dimension.Conductive material is set in the trench with shape It is connected into multiple conducting wires and at least first and second conducting wire but not parallel each other.
In other multiple embodiments, the method for two-dimensional interconnection is formed on substrate to be included providing a substrate, this substrate tool Have on the first layer it is square into hard mask layer and form above hard mask layer multiple non-metal components.Multiple nonmetallic members Part is parallel to each other.The method is further included by forming patterned photoresist layer and use at least one non-metal component This patterned photoresist layer etches at least one non-metal component to form first and second portion of at least one non-metal component Divide at least one non-metal component for patterning multiple non-metal components, there is spacing between this first and second part.This Spacing has the width for being approximately equal to three times critical dimension.The method, which is also included on substrate, sets spacer layer and anisotropy For ground spacer etch layer to form spacer on the side wall of non-metal component, the width of wherein this spacer is approximately equal to critical Size.The method is further comprised removing non-metal component using etch process, be etched using spacer as shade element Hard mask layer and substrate are to form groove and conductive material is set to be approximately equal to critical dimension to be formed to have in the trench The conducting wire of width.At least one conducting wire forms between first portion and second portion and multiple the another of conducting wire is physically contacted and leads Line.
In other multiple embodiments, device includes the dielectric layer of surface and comprising with 5 nanometer or less The first conducting wire, the second conducting wire and the privates of width.Conducting wire includes each trench portions for extending through dielectric layer.First and Privates is parallel to each other and is connected via the second conducting wire.
According to the multiple embodiments of this exposure, a kind of method of integrated circuit two-dimensional interconnection, which includes, provides substrate；On substrate Square at least one first and one second dielectric structure into multiple dielectric structures with multiple the first side walls, wherein dielectric structure It is parallel to each other；A part for the first dielectric structure is removed to form multiple second sidewalls, wherein removing part has width, width About three times of critical dimension；Spacer is formed on first and second side wall；Remove dielectric structure；It is not being protected by spacer Multiple grooves are formed in the region of the substrate of shield, wherein groove has the width for being approximately equal to critical dimension；And in the trench Conductive material is set to form multiple conducting wires, wherein at least one first and one second conducting wire connection of conducting wire but not parallel each other.
In the multiple embodiments of this exposure, above-mentioned critical dimension is 5 nanometers or less.
In the multiple embodiments of this exposure, above-mentioned critical dimension is between 5 nanometers and 30 nanometers.
In the multiple embodiments of this exposure, above-mentioned dielectric structure has height and width, highly in critical dimension One times between three times, width is approximately equal to critical dimension.
In the multiple embodiments of this exposure, the one of first and second above-mentioned conducting wire is formed between second sidewall.
In the multiple embodiments of this exposure, above-mentioned method further includes grinding conducting wire and substrate to form the table of planarization Face.
In the multiple embodiments of this exposure, above-mentioned spacer tool width, width is approximately equal to critical dimension.
In the multiple embodiments of this exposure, first and second above-mentioned conducting wire is orthogonal.
In the multiple embodiments of this exposure, first and second above-mentioned conducting wire is connected with the angle for being less than 90 degree relative to each other It connects.
In the multiple embodiments of this exposure, comprising isotropically setting spacer layer the step of above-mentioned formation spacer In surface and it is etched anisotropically through spacer layer.
According to the multiple embodiments of this exposure, a kind of method that two-dimensional interconnection is formed on substrate, which includes, provides substrate, substrate With on the first layer it is square into hard mask layer；Multiple non-metal components are formed above hard mask layer, wherein nonmetallic member Part is parallel to each other；An at least non-metal component is patterned, wherein patterned step, which is included on non-metal component, forms pattern Change photoresist layer；And non-metal component is etched to form first and second portion of non-metal component using patterned photoresist layer Point, there are spacing, the pitch wherein between first portion and second portion to have width, and width is approximately equal to critical dimension Three times；On substrate set spacer layer and be etched anisotropically through spacer layer on the side wall of non-metal component formed it is more The width of a spacer, wherein spacer is approximately equal to critical dimension；Remove non-metal component；It is first using spacer as shade Part etches hard mask layer and substrate to form multiple grooves；And conductive material is set in the trench to form multiple conducting wires, Conducting wire has width, and width is equal to critical dimension, and a wherein at least conducting wire is formed between first and second part and and conducting wire Another physical contact.
In the multiple embodiments of this exposure, above-mentioned non-metal component has height and width, is highly approximately equal to face For the one of ungraduated ruler cun between three times, width is approximately equal to critical dimension.
In the multiple embodiments of this exposure, the width of above-mentioned conducting wire is approximately equal to critical dimension.
In the multiple embodiments of this exposure, above-mentioned critical dimension is 5 nanometers.
In the multiple embodiments of this exposure, above-mentioned critical dimension is between 5 nanometers and 30 nanometers.
According to the multiple embodiments of this exposure, a kind of device is led comprising dielectric layer, the first conducting wire, the second conducting wire and the 3rd Line.Dielectric layer is located on substrate.First conducting wire, the second conducting wire and privates are respectively provided with width, and width is for 5 nanometers or more Few, respectively comprising trench portions, trench portions extend through dielectric layer, wherein ditch for the first conducting wire, the second conducting wire and privates The corresponding multiple top surfaces of slot part are substantially coplanar, and the first conducting wire is parallel to each other with privates and connects via the second conducting wire It connects.
In the multiple embodiments of this exposure, it is above-mentioned not with the first conducting wire of the second conductive contact and the part of privates It is separated by 15 nanometers or less.
In the multiple embodiments of this exposure, the second above-mentioned conducting wire is perpendicular to the first conducting wire and privates.
In the multiple embodiments of this exposure, the second above-mentioned conducting wire is not parallel with the first conducting wire and privates.
In the multiple embodiments of this exposure, the first above-mentioned conducting wire, the second conducting wire and privates are in same metal It is in level and substantially coplanar.
It is to be understood that this exposure【Embodiment】Part rather than【Summary】It is intended for explaining claim.This exposure portion Point【Summary】One or more exemplary embodiments can be illustrated and not all exemplary embodiment, therefore be not intended to limit this Additional claims.
The feature of several embodiments of above-outlined so that those skilled in the art is better understood the aspect of this exposure. Those skilled in the art it will be appreciated that this exposure can be used easily as design or change the basis of other processing procedures and structure, so as to Implement the identical purpose of embodiments described herein and/or realize identical advantage.Those skilled in the art also should be understood that this Class equivalent structure and can not depart from the spirit and scope of additional claims without departing from the spirit and scope of this exposure In the case of make the various change, replacement and change of this paper.

Claims (1)

  1. A kind of 1. method of integrated circuit two-dimensional interconnection, which is characterized in that include：
    One substrate is provided；
    It is square into multiple dielectric structures with multiple the first side walls on the substrate, wherein the multiple dielectric structure is at least One first dielectric structure and one second dielectric structure are parallel to each other；
    A part for first dielectric structure is removed to form multiple second sidewalls, wherein the removal part has a width, should Width is three times of a critical dimension；
    A spacer is formed on each the first side wall and each second sidewall；
    Remove the multiple dielectric structure；
    Multiple grooves are formed in the region for the substrate do not protected by the spacer, are equal to wherein each groove has One width of the critical dimension；And
    One conductive material is set in the trench to form multiple conducting wires, wherein at least one first conducting wire of the multiple conducting wire And one second conducting wire connection but it is not parallel each other.
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