CN108122841A - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
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- CN108122841A CN108122841A CN201611081247.6A CN201611081247A CN108122841A CN 108122841 A CN108122841 A CN 108122841A CN 201611081247 A CN201611081247 A CN 201611081247A CN 108122841 A CN108122841 A CN 108122841A
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- stressor layers
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- semiconductor structure
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- forming method
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided；First grid structure is formed on the substrate；The first stressor layers are formed in the substrate of the first grid structure both sides, there are the first Doped ions in first stressor layers；Dielectric layer is formed in first stressor layers；It is formed after the dielectric layer, carries out the first annealing, described first makes annealing treatment to activate first Doped ions.The dielectric layer can inhibit first stressor layers in the deformation on the direction of dielectric layer and the contact surface of substrate, reduce the dislocation between the first stressor layers and the first stressor layers lower substrates, so as to reduce the first stressor layers in the stress release on the direction of dielectric layer and the contact surface of substrate, and then it is capable of the deformation or damage of suppressor grid structure lower substrate, reduce the leakage current for forming semiconductor structure, and enhance the driving force of semiconductor devices, improve semiconductor structure performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of forming methods of semiconductor structure.
Background technology
With the continuous progress of semiconductor technology, the direction of semiconductor devices towards high integration, high quality is developed, is partly led
The characteristic size of body device accordingly reduces.
The reduction of the reduction of feature sizes of semiconductor devices, particularly gate structure width, makes gate structure lower channels
Length constantly reduce.The reduction of channel length adds the possibility of charge break-through between stressor layers in transistor, and easily
Cause channel leakage stream.It is often brilliant by the use of SiGe as PMOS in the forming process of semiconductor structure in order to reduce channel leakage stream
The material of body pipe stressor layers, SiGe can provide compression for the raceway groove of PMOS transistor, so as to reduce channel leakage stream.
However, the semiconductor structure that the forming method of existing semiconductor structure is formed still has, leakage current is larger to be lacked
Point.
The content of the invention
The present invention solves the problems, such as to be to provide a kind of forming method of semiconductor structure, can reduce leakage current, improve half
Conductor structure performance.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided；Institute
State formation first grid structure in substrate；Form the first stressor layers in the substrate of the first grid structure both sides, described
There are the first Doped ions in one stressor layers；Dielectric layer is formed in first stressor layers；It is formed after the dielectric layer, into
Row first makes annealing treatment, and described first makes annealing treatment to activate first Doped ions.
Optionally, the material of first stressor layers is SiGe or carbon silicon.
Optionally, the technological parameter of first annealing includes：Annealing temperature is 1100 DEG C~1250 DEG C；Described
One annealing is laser annealing.
Optionally, first stressor layers are formed by the first epitaxial growth technology, and in the first epitaxial growth work
During skill, first Doped ions are mixed in first stressor layers by the first doping process in situ.
Optionally, the material of the dielectric layer is silica.
Optionally, forming the technique of the dielectric layer includes chemical vapor deposition method.
Optionally, before carrying out the first annealing, further include：First stressor layers are carried out with the first supplement ion implanting,
The first supplement of injection ion in first stressor layers.
Optionally, the first supplement ion is boron ion.
Optionally, the substrate includes：First area and second area；The first grid structure is located at firstth area
In the substrate of domain；Before carrying out first annealing, the formation side further includes：Is formed in the second area substrate
Two gate structures；The second stressor layers are formed in the second stressor layers both sides substrate.
Optionally, formed after first stressor layers, second is formed in the substrate of the second grid structure both sides
Stressor layers have the second Doped ions in second stressor layers.
Optionally, formed after first stressor layers, formed before second stressor layers, further included：Carry out second
Annealing, described second makes annealing treatment that first Doped ions is made to be evenly distributed in first stressor layers.
Optionally, the technological parameter of second annealing includes：Annealing temperature is 900 DEG C~1100 DEG C；Described
Two annealings are spike annealing.
Optionally, the material of second stressor layers is silicon or carbon silicon.
Optionally, second stressor layers are formed by the second epitaxial growth technology, and in the second epitaxial growth work
During skill, second Doped ions are mixed in second stressor layers by the second doping process in situ.
Optionally, formed before first stressor layers, further included：The first protection is formed in the second area substrate
Layer；It is formed before second stressor layers, further included：The second protective layer is formed in the first area substrate；Described in removal
The first protective layer in the substrate of first area.
Optionally, the step of forming second protective layer includes：In first protective layer and the first area base
Initial second protective layer is formed on bottom；Initial second protective layer in the second area substrate is removed, forms the second protective layer.
Optionally, further include：It is formed after initial second protective layer, removed initial in the second area substrate
Before second protective layer, first stressor layers are carried out with the second annealing.
Optionally, before carrying out second annealing, formed after the second protective layer, further included：To described second
Stressor layers carry out the second supplement ion implanting, and the second supplement ion is injected in second stressor layers.
Optionally, the second supplement ion is phosphonium ion or arsenic ion.
Compared with prior art, technical scheme has the following advantages：
In the forming method for the semiconductor structure that technical solution of the present invention provides, medium is formed in first stressor layers
After layer, the first annealing is carried out.In first annealing process, the dielectric layer can inhibit described first should
Power layer is in the growing space on the direction of dielectric layer and the contact surface of substrate, so as to inhibit first stressor layers
In the deformation on the direction of dielectric layer and the contact surface of substrate, reduce around the first stressor layers and first stressor layers
Dislocation between substrate.Therefore, the dielectric layer can reduce the first stressor layers in the contact surface perpendicular to dielectric layer and substrate
Direction on stress release, so as to inhibit to occur between the first stress and substrate crack, reduction forms semiconductor
The leakage current of structure, and enhance the driving force of semiconductor devices, improve semiconductor structure performance.
Further, second annealing carries out before second stressor layers are formed, and can inhibit the second stress
The diffusion of the second Doped ions in layer so as to reduce the leakage current of formed semiconductor structure, inhibits short-channel effect.
Further, formed after initial second protective layer, carry out second annealing.In the described second annealing
In processing procedure, initial second protective layer can stop that first Doped ions are spread into ambient enviroment, so as to
Enough reduce the loss of the first Doped ions.
Description of the drawings
Fig. 1 to Fig. 4 is a kind of structure diagram of each step of the forming method of semiconductor structure；
Fig. 5 to Figure 16 is the structure diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Specific embodiment
The forming method of semiconductor structure there are problems, such as：The leakage current of the semiconductor structure formed is larger.
In conjunction with a kind of forming method of semiconductor structure, the larger original of the leakage current of formed semiconductor structure is analyzed
Cause：
Fig. 1 to Fig. 4 is a kind of structure diagram of each step of the forming method of semiconductor structure.
It please refers to Fig.1, substrate is provided, the substrate includes：Substrate 100 and the fin 102 on the substrate 100.
With continued reference to Fig. 1, isolation structure 101, the isolation structure are formed on the substrate 100 between the fin 102
The 101 covering 102 partial sidewall surfaces of fin.
It please refers to Fig.2, is developed across the gate structure 110 of the fin 102, the gate structure 110 covers the fin
102 partial sidewall of portion and top surface.
It please refers to Fig.3, stressor layers 120 is formed in the fin 102 of 110 both sides of gate structure.
The material of the stressor layers 120 is the SiGe containing boron ion.
It please refers to Fig.4, the stressor layers 120 is made annealing treatment.
Wherein, in order to reduce the short-channel effect of formed transistor, the material of the stressor layers 120 is to contain boron ion
SiGe.The lattice constant of germanium atom is larger in SiGe, compression can be provided for the transistor channel formed, so as to reduce
The short-channel effect of formed transistor.
However, during the annealing is carried out, annealing temperature higher (1200 DEG C~1250 DEG C) is close to SiGe
Fusing point, be changed into solid solution state so as to be easy to cause stressor layers 120, volume increases, and causes the change of stressor layers 120 and fin 102
Shape mismatches, and so as to generate excessive stress in the contact position of the stressor layers 120 and fin 102, the release of stress causes should
Power layer 120 misplaces with 102 surrounding fin 102 of stressor layers, makes to generate crack between stressor layers 120 and fin 102.And then hold
Easily increase the leakage current for forming transistor.
To solve the technical problem, the present invention provides a kind of forming method of semiconductor structure, including：Base is provided
Bottom；First grid structure is formed on the substrate；The first stressor layers are formed in the substrate of the first grid structure both sides,
There are the first Doped ions in first stressor layers；Dielectric layer is formed in first stressor layers；Form the dielectric layer
Afterwards, the first annealing is carried out, described first makes annealing treatment to activate first Doped ions.
Wherein, formed in first stressor layers after dielectric layer, carry out the first annealing.In the described first annealing
In processing procedure, the dielectric layer can inhibit first stressor layers perpendicular to the direction of dielectric layer and the contact surface of substrate
On growing space, so as to inhibit first stressor layers on the direction of dielectric layer and the contact surface of substrate
Deformation reduces the dislocation between substrate around the first stressor layers and first stressor layers.Therefore, the dielectric layer can reduce
First stressor layers the stress on the direction of dielectric layer and the contact surface of substrate release, so as to inhibit first should
Occur crack between power and substrate, reduce the leakage current for forming semiconductor structure, and enhance the driving force of semiconductor devices,
Improve semiconductor structure performance.
It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 5 to Figure 16 is the structure diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Fig. 5 is refer to, substrate is provided.
In the present embodiment, the substrate includes：First area I and second area II.
In the present embodiment, the substrate is used to form fin formula field effect transistor.In other embodiments, the substrate is also
It can be used for forming planar transistor.
In the present embodiment, the first area I is used to form PMOS transistor；The second area II is used to form NMOS
Transistor.In other embodiments, the first area can be also used for being formed NMOS transistor, and the second area can be with
For forming PMOS transistor.
In the present embodiment, the substrate includes：Substrate 200；The first fin on the first area I substrates 200
201；The second fin 202 on the second area II substrates 200.
In the present embodiment, the step of forming the substrate, includes：Initial substrate is provided；The graphical initial substrate, shape
Into substrate 200, the first fin 201 on first area I substrates 200 and on the second area II substrates 200
The second fin 202.
In the present embodiment, the material of the initial substrate is silicon.In other embodiments, the initial substrate can also be
The Semiconductor substrates such as germanium substrate, silicon-Germanium substrate, silicon-on-insulator or germanium on insulator.
In the present embodiment, 201 and second fin 202 of the first fin is located at 200 surface of substrate.In other implementations
In example, there can also be oxide layer between first fin, the second fin and the substrate.
In the present embodiment, the material of 201 and second fin 202 of the first fin is silicon.In other embodiments, it is described
The material of first fin and the second fin can also be germanium or SiGe.
It is formed after substrate, the forming method further includes：Isolation structure 203 is formed on 200 over the substrate, it is described
Isolation structure 203 covers 201 and second fin of the first fin, the 202 partial sidewall surface.
The isolation structure 203 is used to implement the electrical isolation between different semiconductor devices.
In the present embodiment, the material of the isolation structure 201 is silica.In other embodiments, the isolation structure
Material can also be silicon oxynitride.
Fig. 6 is refer to, forms first grid structure 211 on the substrate.
In the present embodiment, the substrate includes：First area I and second area II.The first grid structure 211 is located at
In the first area I substrates.There is second grid structure 212 in the second area II substrates.
Specifically, in the present embodiment, the first grid structure 211 is across first fin 201, the first grid
Structure 211 covers 201 partial sidewall of the first fin and top surface；The second grid structure 212 is across second fin
202, the second grid structure 212 covers 202 partial sidewall of the second fin and top surface.
In the present embodiment, the first grid structure 211 includes：Across the first gate dielectric layer of first fin 201,
First gate dielectric layer covers 201 partial sidewall of the first fin and top surface；On first gate dielectric layer
First grid.
The second grid structure 212 includes：Across the second gate dielectric layer of second fin 202, the second gate
Dielectric layer covers 202 partial sidewall of the second fin and top surface；Second grid on second gate dielectric layer.
It is formed after the first grid structure 211 and second grid structure 212, the forming method further includes：Institute
It states 211 sidewall surfaces of first grid structure and forms the first side wall；The second side is formed in 212 sidewall surfaces of second grid structure
Wall；It is mask with first side wall and first grid structure 211, the first fin in 211 both sides of first grid structure
The first lightly doped district is formed in 201；It is mask with second side wall and second grid structure 212, in the second grid knot
The second lightly doped district is formed in second fin 202 of 212 both sides of structure.
The first stressor layers are subsequently formed in the first fin 201 of 211 both sides of first grid structure, described first should
There are the first Doped ions, specifically as shown in Figure 7 and Figure 8 in power layer.
Fig. 7 is refer to, the first protective layer 221 is formed in the second area II substrate surfaces.
First protective layer 221 is used for during the first stressor layers are subsequently formed, and protects second area II substrates,
It avoids forming the first stressor layers in second area II substrates.
In the present embodiment, first protective layer 211 is also located at 212 top of second grid structure and sidewall surfaces.
In other embodiments, first protective layer can also be only located at the second area substrate surface.
In the present embodiment, the material of first protective layer 221 is silicon nitride.In other embodiments, described first protect
The material of sheath can also be silica or silicon oxynitride.
In the present embodiment, formed the first protective layer 221 the step of include：Form covering first area I substrates and the
Initial first protective layer of two region II substrates；Patterned first is formed on initial first protective layers of the second area II
Photoresist (not shown)；Initial first protective layer is performed etching using first photoresist as mask, removes institute
Initial first protective layer in the I substrates of first area is stated, forms the first protective layer；It removes first in the first area I substrates
Begin after the first protective layer, remove the photoresist.
Fig. 8 is refer to, is formed after first protective layer 221, in the substrate of 211 both sides of first grid structure
Form the first stressor layers 231.
In the present embodiment, first stressor layers 231 are located at the first fin 201 of 211 both sides of first grid structure
In.
In the present embodiment, the material of first stressor layers 231 is SiGe.The lattice constant of germanium atom in SiGe is more than
The lattice constant of first fin, 201 material can provide compression for the transistor formed, crystalline substance is formed so as to reduce
The leakage current of body pipe.In other embodiments, the first area is used to form NMOS transistor, the material of first stressor layers
Material can also be carbon silicon.
In the present embodiment, formed the first stressor layers 231 the step of include：In 211 both sides of first grid structure
The first fin 201 in form the first groove；First stressor layers 231 are formed in first groove.
In the present embodiment, first stressor layers 231 are formed in first groove by the first epitaxial growth technology,
And during first epitaxial growth technology, mixed by the first doping process in situ in first stressor layers 231
Enter the first Doped ions.
In the present embodiment, first stressor layers 231 are doped by the first doping process in situ, to described first
The loss of stressor layers 231 is small.In other embodiments, first stressor layers can also be mixed by ion implantation technology
It is miscellaneous.
In the present embodiment, first Doped ions are boron ion or BF2 -Ion.
Refer to Fig. 9, formed after first stressor layers 231, first stressor layers 231 are carried out first supplement from
The first supplement ion is injected in son injection in first stressor layers 231.
The first supplement ion implanting is for compensation 231 first Doped ions of surface of the first stressor layers caused by diffusion
Loss.
During first stressor layers 231 are carried out with the first supplement ion implanting, have on second fin 202
There is the first protective layer 221, can prevent the first supplement of injection ion in the second fin 202.
In the present embodiment, the first supplement ion is identical with the conduction type of first Doped ions.Specifically, institute
The first supplement ion is stated as boron ion or BF2 -Ion.
It should be noted that in other embodiments, can not also first stressor layers be carried out with first supplement
Ion implanting.
It is subsequently formed after the first stressor layers 231, first stressor layers 231 is carried out with the second annealing；Described
The second protective layer is formed in the I substrates of first area.
In the present embodiment, formed second protective layer the step of include：In the first area I substrates and described first
Initial second protective layer is formed on protective layer 221；It removes initial second protective layer on first protective layer 221, forms the
Two protective layers.It is formed after initial second protective layer, before being performed etching to initial second protective layer, to described
One stressor layers 231 carry out the second annealing.Specifically, first stressor layers 231 are carried out with the second annealing；Described
The step of forming the second protective layer 220 in the I substrates of first area is as shown in Figure 10 to Figure 12.
It should be noted that in the present embodiment, after initial second protective layer 240 is formed, removal described first
Before initial second protective layer 240 on protective layer 221, first stressor layers 231 are carried out with the second annealing.At other
In embodiment, second annealing can also be carried out after second protective layer is formed.
0 is please referred to Fig.1, initial second protective layer is formed in the first area I substrates and first protective layer 221
240。
Initial second protective layer 240 is used to be subsequently formed the second protective layer.
In the present embodiment, the material of initial second protective layer 240 and the material identical of first protective layer 221.
Initial second protective layer 240 of material identical can subsequently be performed etching with the first protective layer 221 by same etching technics, from
It and being capable of simplification of flowsheet.Specifically, the material of initial second protective layer is silicon nitride.In other embodiments, institute
The material for stating initial second protective layer can also be silicon oxynitride.
In the present embodiment, initial second protective layer 240 is formed by chemical vapor deposition method.In other embodiment
In, initial second protective layer can also be formed by physical gas-phase deposition.
1 is please referred to Fig.1, is formed after initial second protective layer 240, second is carried out to first stressor layers 231
Annealing.
Second annealing is for making first Doped ions and the first supplement Doped ions described the
It is uniformly distributed in one stressor layers 231.
The material of first stressor layers 231 is containing boron ion or BF2 -SiGe, germanium atom is to first Doped ions
Diffusion have barrier effect, therefore, in second annealing process, first Doped ions are not easy to diffuse into
In the raceway groove for entering formed transistor, so as to be not easy to influence the performance for forming semiconductor structure.
It should be noted that in the present embodiment, after second initial protective layers 240 are formed, described second is carried out
Annealing.Second initial protective layers 220 can in second annealing process, stop described first adulterate from
Sub and described first supplement Doped ions outwardly Environmental diffusion, so as to reduce the first Doped ions and first supplement
The loss of Doped ions.
In other embodiments, can also after initial second protective layer is formed, the first supplement ion implanting it
Afterwards, first stressor layers are carried out with the second annealing.
If the annealing temperature of second annealing is too low, it is not easy to make first Doped ions and described first
Supplement ion is evenly distributed in first stressor layers；If the annealing temperature of second annealing is excessively high, easily make first
Stressor layers deformation is excessive, is mismatched so as to cause the deformation of the first stressor layers and the substrate, makes the first stressor layers should with first
Crack is generated between substrate around power layer.Specifically, the annealing temperature of second annealing is 900 DEG C~1100 DEG C.
If the annealing time of second annealing is long, first Doped ions is easily made to enter to form crystalline substance
In body pipe trench road, so as to influence formed semiconductor structure performance.Specifically, second annealing is spike annealing.
2 are please referred to Fig.1, removes initial second protective layer 240 (as shown in figure 11) on first protective layer 221, shape
Into the second protective layer 241.
Second protective layer 241 is used for during second stressor layers are subsequently formed, and protects first fin
Portion 201 avoids forming the second stressor layers on first fin 201.
In the present embodiment, the step of removing initial second protective layer 240 on first protective layer 221, includes：Institute
It states and forms the second photoresist (not shown) on initial second protective layers 240 of first area I；Using second photoresist to cover
Film performs etching initial second protective layer 240, removes initial second protective layer 240 of the second area II, is formed
Second protective layer 241.
In the present embodiment, the technique performed etching to initial second protective layer 240 includes：Dry etch process is wet
Method etching technics.
It is subsequently formed before the second stressor layers, further includes the first protective layer 221 removed on second fin 202.
In the present embodiment, the first protective layer 221 on second fin 202 is removed by etching technics.
It should be noted that the material identical of first protective layer 221 and initial second protective layer 240, therefore,
In the present embodiment, initial second protective layer 240 and first protective layer 221 are carved by same etching technics
Erosion, removes the first protective layer 221 in the second area II substrates and initial second protective layer 240.
3 are please referred to Fig.1, is formed after second protective layer 241, the substrate in 212 both sides of second grid structure
It is middle to form the second stressor layers 232, there are the second Doped ions in second stressor layers 232.
It should be noted that after the described second annealing, second stressor layers 232 are formed, it can be second
In annealing process, second Doped ions is avoided to diffuse into the raceway groove of institute's transistor, the shape so as to improve
Into semiconductor structure performance.
In the present embodiment, second stressor layers 232 are located at the second fin 202 of 212 both sides of second grid structure
In.
In the present embodiment, formed the second stressor layers 232 the step of include：In 212 both sides of second grid structure
The second fin 202 in form the second groove；Second stressor layers 232 are formed in second groove.
In the present embodiment, second stressor layers 232 are formed by the second epitaxial growth technology, and in second extension
During growth technique, the second Doped ions are mixed in second stressor layers 232 by the second doping process in situ.
Second doping process in situ is small to the damage of second fin 202.It can also pass through ion implanting work at other
Skill is doped second stressor layers.
In the present embodiment, second Doped ions are phosphonium ion or arsenic ion.
In the present embodiment, the material of second stressor layers 232 is silicon, and the formation process of silicon is simple.In other embodiment
In, the material of second stressor layers can also be carbon silicon.
4 are please referred to Fig.1, second stressor layers 232 are carried out with the second supplement ion implanting, in second stressor layers
The second supplement of injection ion in 232.
Second ion is used to compensate the damage of second Doped ions on 231 surface of the second stressor layers caused by diffusion
Consumption.
In the present embodiment, the second supplement ion is identical with the conduction type of second Doped ions.Specifically, the
Two supplement ions are phosphonium ion or arsenic ion.
5 are please referred to Fig.1, dielectric layer 250 is formed in first stressor layers 231.
The dielectric layer 250 is used to implement the electric isolution of formed transistor and external circuit.
In the present embodiment, the material of the dielectric layer 250 is silica.In other embodiments, the material of the dielectric layer
Material can also be silicon oxynitride.
In the present embodiment, forming the technique of the dielectric layer 250 includes chemical vapor deposition method.In other embodiment
In, atom layer deposition process or physical gas-phase deposition can also be included by forming the technique of the dielectric layer.
6 are please referred to Fig.1, is formed after the dielectric layer 250, carries out the first annealing, first annealing is used
In activation first Doped ions.
In the present embodiment, it is described first annealing for activate first Doped ions and described second adulterate from
Son makes first Doped ions occupy the lattice position of the first stressor layers 231, and makes the first Doped ions and first stress
231 atom of layer being capable of bonding；Meanwhile second Doped ions is made to occupy 232 lattice position of the second stressor layers, and second adulterate from
Son and 232 atomic bonding of the second stressor layers.
During described first makes annealing treatment, the dielectric layer 250 can inhibit first stressor layers 231 and hang down
Directly in the growing space on the direction of dielectric layer 250 and the contact surface of substrate, exist so as to inhibit first stressor layers 231
Deformation on the direction of dielectric layer 250 and the contact surface of substrate reduces the first stressor layers 231 and first stressor layers
Dislocation between 231 surrounding substrates, so as to reduce the first stressor layers 231 on 250 direction with the contact surface of substrate
Stress release, and then can inhibit occur crack between first stressor layers 231 and substrate, reduction forms semiconductor
The leakage current of structure, and enhance the driving force of semiconductor devices, improve semiconductor structure performance.
In addition, in the present embodiment, during described first makes annealing treatment, the dielectric layer 250 can inhibit described
Growing space of second stressor layers 232 on the direction perpendicular to dielectric layer 250 and the contact surface of substrate, so as to inhibit
The second stressor layers 232 are stated in the deformation on the direction of dielectric layer 250 and the contact surface of substrate, the second stressor layers of reduction
Dislocation between 232 and second stressor layers, 232 surrounding substrate, so as to reduce the second stressor layers 232 perpendicular to 250 and base
The release of stress on the direction of the contact surface at bottom, and then can inhibit to split between second stressor layers 232 and substrate
Seam reduces the leakage current for forming semiconductor structure, and enhances the driving force of semiconductor devices, improves semiconductor structure
Energy.
If the annealing temperature of first annealing is too low, it is not easy to activate first Doped ions and described the
Two Doped ions；If the annealing temperature of first annealing is excessively high, easily increase by first stressor layers 231 and described
The deformation of second stressor layers 232.Specifically, in the present embodiment, the annealing temperature of first annealing for 1100 DEG C~
1250℃。
In the present embodiment, the annealing time of first annealing is long, easily increases by 231 He of the first stressor layers
The deformation of second stressor layers 232；If the annealing time of first annealing is too short, mixed it is difficult to activate described first
Heteroion and second Doped ions.Specifically, first annealing is laser annealing.
To sum up, in the forming method of the semiconductor structure of embodiment, formed in first stressor layers after dielectric layer,
Carry out the first annealing.In first annealing process, the dielectric layer can inhibit first stressor layers and exist
Growing space on the direction of dielectric layer and the contact surface of substrate, so as to inhibit first stressor layers vertical
Deformation on the direction of dielectric layer and the contact surface of substrate, reduce around the first stressor layers and first stressor layers substrate it
Between dislocation.Therefore, the dielectric layer can reduce the first stressor layers perpendicular to the direction of dielectric layer and the contact surface of substrate
On stress release, so as to inhibit to occur between the first stress and substrate crack, reduction forms semiconductor structure
Leakage current, and enhance the driving force of semiconductor devices, improve semiconductor structure performance.
Further, second annealing carries out before second stressor layers are formed, and can inhibit the second stress
The diffusion of the second Doped ions in layer so as to reduce the leakage current of formed semiconductor structure, inhibits short-channel effect.
Further, formed after initial second protective layer, carry out second annealing.In the described second annealing
In processing procedure, initial second protective layer can stop that first Doped ions are spread into ambient enviroment, so as to
Enough reduce the loss of the first Doped ions.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the scope of restriction.
Claims (19)
1. a kind of forming method of semiconductor structure, which is characterized in that including：
Substrate is provided；
First grid structure is formed on the substrate；
The first stressor layers are formed in the substrate of the first grid structure both sides, there is the first doping in first stressor layers
Ion；
Dielectric layer is formed in first stressor layers；
It is formed after the dielectric layer, carries out the first annealing, first annealing is adulterated for activating described first
Ion.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of first stressor layers is
SiGe or carbon silicon.
3. the forming method of semiconductor structure as described in claim 1, which is characterized in that the technique of first annealing
Parameter includes：Annealing temperature is 1100 DEG C~1250 DEG C；First annealing is laser annealing.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that pass through the first epitaxial growth technology shape
Into first stressor layers, and during first epitaxial growth technology, by the first doping process in situ described
First Doped ions are mixed in first stressor layers.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material of the dielectric layer is oxidation
Silicon.
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that form the technique bag of the dielectric layer
Include chemical vapor deposition method.
7. the forming method of semiconductor structure as described in claim 1, which is characterized in that before carrying out the first annealing, also wrap
It includes：First stressor layers are carried out with the first supplement ion implanting, the first supplement ion is injected in first stressor layers.
8. the forming method of semiconductor structure as claimed in claim 7, which is characterized in that it is described first supplement ion for boron from
Son.
9. the forming method of semiconductor structure as described in claim 1, which is characterized in that the substrate includes：First area
And second area；The first grid structure is located in the first area substrate；
Before carrying out first annealing, the formation side further includes：Second gate is formed in the second area substrate
Pole structure；The second stressor layers are formed in the second stressor layers both sides substrate.
10. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that formed first stressor layers it
Afterwards, the second stressor layers are formed in the substrate of the second grid structure both sides, there is the second doping in second stressor layers
Ion.
11. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that formed first stressor layers it
Afterwards, formed before second stressor layers, further included：The second annealing is carried out, second annealing is described for making
First Doped ions are evenly distributed in first stressor layers.
12. the forming method of semiconductor structure as claimed in claim 11, which is characterized in that the work of second annealing
Skill parameter includes：Annealing temperature is 900 DEG C~1100 DEG C；Second annealing is spike annealing.
13. the forming method of semiconductor structure as claimed in claim 9, which is characterized in that the material of second stressor layers
For silicon or carbon silicon.
14. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that pass through the second epitaxial growth technology
Second stressor layers are formed, and during second epitaxial growth technology, by the second doping process in situ in institute
It states and second Doped ions is mixed in the second stressor layers.
15. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that formed first stressor layers it
Before, it further includes：The first protective layer is formed in the second area substrate；It is formed before second stressor layers, further included：
The second protective layer is formed in the first area substrate；Remove the first protective layer in the first area substrate.
16. the forming method of semiconductor structure as claimed in claim 15, which is characterized in that form second protective layer
Step includes：Initial second protective layer is formed on first protective layer and the first area substrate；Remove described second
Initial second protective layer on substrate areas forms the second protective layer.
17. the forming method of semiconductor structure as claimed in claim 16, which is characterized in that further include：It is formed described initial
After second protective layer, before removing initial second protective layer in the second area substrate, to first stressor layers into
Row second makes annealing treatment.
18. the forming method of semiconductor structure as claimed in claim 17, which is characterized in that carry out second annealing
Before, formed after the second protective layer, further included：Second stressor layers are carried out with the second supplement ion implanting, described the
The second supplement of injection ion in two stressor layers.
19. the forming method of semiconductor structure as claimed in claim 18, which is characterized in that the second supplement ion is phosphorus
Ion or arsenic ion.
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