CN108122831B - Forming a protective layer to prevent formation of leakage paths - Google Patents

Forming a protective layer to prevent formation of leakage paths Download PDF

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Publication number
CN108122831B
CN108122831B CN201710857999.5A CN201710857999A CN108122831B CN 108122831 B CN108122831 B CN 108122831B CN 201710857999 A CN201710857999 A CN 201710857999A CN 108122831 B CN108122831 B CN 108122831B
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protective layer
forming
interlayer dielectric
hole
spacer
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CN108122831A (en
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徐永昌
林郁翔
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask over the gate electrode. The hard mask includes a first dielectric material. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises a second dielectric material different from the first dielectric material. A first via is formed in the first ILD. Sidewalls of the first via are surrounded by a spacer comprising a first dielectric material. A second ILD is formed over the first ILD. A through via is formed in the second ILD. The through hole exposes the first through hole. A protective layer is formed in the through hole. And removing the bottom of the protective layer. An etching process is then performed. The remaining portion of the protective layer prevents etching of the spacers during the etching process. Embodiments relate to a method of manufacturing a semiconductor device.

Description

Forming a protective layer to prevent formation of leakage paths
Technical Field
Embodiments relate to a method of manufacturing a semiconductor device, and more particularly, to forming a protective layer to prevent a leakage path from being formed.
Background
The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have resulted in one generation of another, where each generation of ICs has smaller and more complex circuits than previous generation ICs. However, these advances have increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required in order to achieve these advances. In the evolution of integrated circuits, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry (i.e., the smallest component (or line) that can be produced using a fabrication process) has decreased.
However, existing semiconductor manufacturing may still have certain drawbacks. One disadvantage is that as semiconductor devices are scaled down, certain manufacturing processes may lead to unexpected consequences. For example, the formation of the conductive vias/contacts may involve etching a hard mask. This etching process may result in other components (of the same or similar material composition as the hard mask) being inadvertently etched through. As a result, leakage paths may be created, which may create undesirable electrical shorts that may lead to reduced device performance or failure.
Thus, while existing semiconductor devices and their manufacture have generally met with their intended purpose, they have not been entirely satisfactory in every aspect.
Disclosure of Invention
According to some embodiments of the present invention, there is provided a method of manufacturing a semiconductor device, including: receiving a semiconductor device comprising a first interlayer dielectric (ILD) and a second interlayer dielectric disposed over the first interlayer dielectric, wherein a first via is disposed in the first interlayer dielectric, and wherein a spacer is disposed on a sidewall of the first via; forming a through hole in the second interlayer dielectric, the through hole exposing the first through hole; forming a protective layer in the through hole; and performing an etching process after forming the protective layer.
According to further embodiments of the present invention, there is also provided a method of manufacturing a semiconductor device, including: forming a gate structure over a substrate, the gate structure comprising a gate electrode and a hard mask over the gate electrode, wherein the hard mask comprises a first dielectric material; forming a first interlayer dielectric (ILD) over the gate structure, wherein the first interlayer dielectric comprises a second dielectric material different from the first dielectric material; forming a first via in the first interlayer dielectric, wherein a sidewall of the first via is surrounded by a spacer comprising the first dielectric material; forming a second interlayer dielectric over the first interlayer dielectric; forming a through hole in the second interlayer dielectric, the through hole exposing the first through hole; forming a protective layer in the through hole; removing the bottom of the protective layer; and thereafter performing an etching process, wherein the remaining portion of the protective layer prevents etching of the spacer during the etching process.
There is also provided, in accordance with yet other embodiments of the present invention, a method of manufacturing a semiconductor device, including: forming a gate structure over a substrate, the gate structure comprising a gate electrode and a hard mask over the gate electrode, wherein the hard mask comprises silicon nitride; forming a first interlayer dielectric (ILD) over the gate structure, wherein the first interlayer dielectric comprises silicon oxide; forming a first via in the first interlayer dielectric, wherein a sidewall of the first via is surrounded by a spacer comprising silicon nitride; forming a second interlayer dielectric over the first interlayer dielectric, wherein the second interlayer dielectric comprises silicon nitride; forming a through hole in the second interlayer dielectric, the through hole exposing the through hole and exposing a first portion of the spacer; forming a protective layer in the through-hole, wherein the protective layer includes a polymer; removing a bottom portion of the protective layer, wherein a remaining portion of the protective layer still covers the first portion of the spacer; and performing an etch process to remove portions of the hard mask to expose portions of the gate electrode, wherein the polymer has an etch selectivity to the silicon nitride such that remaining portions of the protective layer prevent the spacers from being inadvertently etched during the etch process.
Drawings
The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1-4 and 6 are cross-sectional side views of a semiconductor device at various stages of fabrication according to various embodiments of the present invention.
Fig. 5 is a cross-sectional side view of a semiconductor device illustrating the formation of a leakage path.
Fig. 7 illustrates a perspective view of an exemplary FinFET device.
Fig. 8 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "under" can include both an orientation above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As semiconductor fabrication technology nodes progress to smaller generations, more transistors may be implemented on a single IC chip. This improves the performance of IC chips while reducing their cost. However, conventional semiconductor fabrication methods may still have drawbacks. For example, the fabrication of semiconductor devices involves the formation of interconnect structures to provide electrical connections to various components (e.g., gate, source, drain) of the semiconductor device. Wherein the interconnect structure may include conductive vias/contacts formed to electrically connect to the semiconductor device. The vias/contacts are typically formed by etching the vias/contact holes in an electrically insulating layer and then filling the vias/contact holes with a conductive material. As semiconductor device dimensions continue to scale down, the etching of via/contact holes (e.g., etching openings in a hard mask over a gate) may inadvertently pierce other layers having the same or similar material composition as the hard mask. These unintentionally pierced layers may then create leakage paths that become conductive when they are filled with conductive material (forming vias/contacts as a result of the deposition process). Such conductive leakage paths may lead to undesirable electrical shorts (e.g., shorts between the gate and other vias/contacts of a semiconductor device), which results in reduced device performance or device failure.
In order to overcome the above problems, the present invention forms a protective layer on the sidewalls of the via/contact holes. The protective layer prevents inadvertent etching of the layer and thus reduces the likelihood of forming a leakage path that would result in an electrical short. Various aspects of the invention are discussed in more detail below with reference to fig. 1-5 and 7-8.
Fig. 1-6 are simplified schematic cross-sectional side views of a semiconductor device 35 during various stages of fabrication. The semiconductor device 35 may be part of an Integrated Circuit (IC) chip, a system on a chip (SoC), or a portion thereof. Which may include various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Complementary Metal Oxide Semiconductor (CMOS) transistors, laterally diffused MOS (ldmos) transistors, high power MOS transistors, or other types of transistors. It should be appreciated that fig. 1-6 have been simplified to provide a better understanding of the inventive concepts of the present invention. It should therefore be noted that additional processes may be provided before, during, and after the processes shown in fig. 1-6 to complete the fabrication of semiconductor device 35, and that some other processes may only be briefly described herein.
Referring to fig. 1, semiconductor device 35 includes a substrate 40. The substrate 40 may be a silicon substrate (e.g., a P-type substrate) doped with a P-type dopant such as boron. Alternatively, the substrate 40 may be another suitable semiconductor material. For example, the substrate 40 may be a silicon substrate (N-type substrate) doped with an N-type dopant such as phosphorus or arsenic. Substrate 40 may alternatively be made of some other suitable elemental semiconductor such as diamond or germanium; a suitable compound semiconductor such as silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor such as silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. In some embodiments, substrate 40 may include an epitaxial layer (epi layer), the substrate may be strained for performance enhancement, and substrate 40 may include a silicon-on-insulator (SOI) structure.
The illustrated portion of the substrate 40 may be an active area (OD). A plurality of source/drain regions (e.g., source/drain regions 50-51) may be formed in the active region. The source/drain regions 50-51 may serve as source/drain components for transistors such as FinFET transistors.
An interlayer dielectric (ILD)70 is formed over the substrate 40. In some embodiments, the ILD 70 comprises silicon oxide (SiO)2). The ILD 70 may be formed by a suitable deposition process followed by a polishing process such as Chemical Mechanical Polishing (CMP) to planarize an upper surface of the ILD 70. ILD 70 may also be referred to as an ILD0 layer.
A plurality of gate structures, such as gate structures 100 and 103, are formed over substrate 40. The gate structures 100-103 include gate dielectric layers 110-113. The gate dielectric layer 110-113 may be formed by a suitable deposition process such as Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), or Physical Vapor Deposition (PVD). In some embodiments, gate dielectric layer 110-113 comprises a high-k dielectric material. The high-k dielectric material has a dielectric constant greater than that of SiO2A dielectric constant of about 4. In one embodiment, the gate dielectric layer 110-113 comprises hafnium oxide (HfO)2) Having a dielectric constant in the range of from about 18 to about 40. In alternative embodiments, gate dielectric layer 110-113 may comprise ZrO2、Y2O3、La2O5、Gd2O5、TiO2、Ta2O5One of HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfTiO, HfTaO and SrTiO.
The gate structures 100-103 include gate electrode layers 120-123. The gate electrode layers 120-123 are respectively located above the gate dielectric layers 110-113. In some embodiments, gate electrode layer 120 and 123 comprise metal gate electrodes. The metal gate electrode may include a workfunction metal component and a fill metal component. The work function metal component is configured to adjust the work function of its corresponding FinFET to achieve a desired threshold voltage Vt. In various embodiments, the work function metal component may include: TiAl, TiAlN, TaCN, TiN, WN or W or a combination thereof. The fill metal component is configured to serve as the primary conductive portion of the functional gate structure 320. In various embodiments, the filler metal component may include aluminum (Al), tungsten (W), copper (Cu), or combinations thereof.
The gate structure 100-103 includes a hard mask 130-133. Hard masks 130-133 are located over gate electrode layers 120-123, respectively. Hard mask 130-133 is formed by a patterning process and may include a dielectric material. In some embodiments, hard mask 130-133 comprises silicon nitride (Si)3N4). In some other embodiments, hard mask 130-133 comprises a silicon nitride layer and a silicon oxide layer.
In some embodiments, the gate structure 100-103 may be formed by a gate replacement process, wherein the dummy gate structure is replaced by the gate structure 100-103. For example, each of the dummy gate structures may include a polysilicon dummy gate electrode. After the source/drain regions 50-51 are formed, the dummy gate electrode is removed and gate electrodes 120-123 are formed to replace the dummy gate electrode. In some other embodiments, the gate replacement process may also involve forming a dummy gate dielectric layer for each gate structure. The dummy gate dielectric layer may include silicon oxide. The dummy gate dielectric layer (replaced along with the dummy gate electrode layer) may also be replaced by a gate dielectric layer 110-113 (e.g., comprising a high-k dielectric material).
A plurality of gate spacers are formed on the sidewalls of the gate structures 100 and 103. For example, gate spacers 150A-150A are formed on opposing sidewalls of gate structure 100, gate spacers 151A-151A are formed on opposing sidewalls of gate structure 101, gate spacers 152A-152A are formed on opposing sidewalls of gate structure 102, and gate spacers 153A-153A are formed on opposing sidewalls of gate structure 103. Gate spacers 150A-153A and 150B-153B comprise a dielectric materialAnd (5) feeding. In some embodiments, gate spacers 150A-153A and 150B-153B comprise silicon nitride (Si)3N4) Which is the same material as hard mask 130-133.
A plurality of vias are formed over substrate 40 and provide electrical connections to source/drain regions 50-51. For example, via 180 is formed over source/drain region 50 (and between gate structures 100-101), and via 181 is formed over source/drain region 51 (and between gate structures 102-103). Vias 180 and 181 extend vertically through ILD 70. For example, the vias 180-181 may be formed by etching openings (vias) in the ILD 70 and subsequently filling the openings with a conductive material. The conductive material may include tungsten, copper, aluminum, or combinations thereof.
An etch stop layer 200 is formed over the ILD 70, over the gate structure 100 and 103, and over the vias 180 and 181. The etch stop layer 200 is formed to function as a double-patterned etch stop layer. The etch stop layer 200 comprises a dielectric material. In some embodiments, the dielectric material is silicon nitride (Si)3N4) Which is the same material as hard mask 130-133.
An interlayer dielectric (ILD)220 is formed over the etch stop layer 200. In some embodiments, the ILD 220 comprises silicon oxide (SiO)2). The ILD 220 may be formed by a suitable deposition process followed by a polishing process, such as Chemical Mechanical Polishing (CMP), to planarize an upper surface of the ILD 220. ILD 220 may also be referred to as an ILD1 layer.
Conductive vias 230-231 are formed over vias 180-181, respectively, to provide electrical connections to vias 180-181 (and thus to source/drain regions 50-51). Vias 230 and 231 extend vertically through ILD 220. For example, the vias 230 and 231 can be formed by etching openings (through holes) in the ILD 220 and subsequently filling the openings with a conductive material. The conductive material may include tungsten, copper, aluminum, or combinations thereof. In the illustrated embodiment, the sidewalls of the via 230 are in direct physical contact with the spacers 240A-240B, and the sidewalls of the via 231 are in direct physical contact with the spacers 241A-241B. The spacers 240A-240B and 241A-241B may be formed first, and the vias 230-231 formed later. The spacers 240A-240B and 241A-241B includeA dielectric material. In some embodiments, the dielectric material is silicon nitride (Si)3N4) Which is the same material as the hard mask 130-133 and the etch stop layer 200. Each of the spacers 240A-240B and 241A-241B has a thickness 245. In some embodiments, thickness 245 is in a range from 0.5 microns to 100 microns.
Another interlayer dielectric (ILD)250 is formed over ILD 220 and over vias 230 and 231. In some embodiments, ILD250 comprises silicon oxide (SiO)2). The ILD250 may be formed by a suitable deposition process followed by a polishing process such as CMP to planarize the upper surface of the ILD 250. ILD250 may also be referred to as an ILD2 layer.
Through vias 270 and 273 are then formed as part of the through vias to provide electrical connection to the through vias 230 and the gate structure 103. In more detail, using an etch process, through holes 273 (extending vertically through ILDs 250 and 220) are etched in ILDs 250 and 220 until etch stop layer 200 is reached due to the etch selectivity between the silicon oxide material of ILD 250/220 and the silicon nitride material of etch stop layer 200.
Through the same etch process that forms through-hole 273, through-hole 270 is etched in ILD250 (and extends vertically through ILD250) until via 230 is exposed, due to the etch selectivity between the silicon oxide material of ILD250 and the conductive material of via 230. The through- holes 270 and 273 are later filled with a conductive material to form conductive vias therein.
It should be appreciated that the through-holes 270 are not perfectly aligned with the through-holes 230 due to process limitations. If the through-holes 270 are offset (e.g., laterally to the left or right), portions of the upper surfaces of the spacers 240A-240B may be exposed through the through-holes 270. Alternatively, even if the alignment between the through-hole 270 and the through-hole 230 is perfect, the through-hole 270 is still formed wider than the upper surface of the through-hole 230, which will expose a portion of the upper surface of the spacer 240A or 240B. This unintentional exposure of the spacers 240A-240B (through the through vias 270) may result in the formation of leakage paths when an etch process is performed later. To address this problem, the present invention reduces the likelihood of exposing the spacers 240A-240B, as discussed in more detail below.
Referring now to fig. 2, a protective layer 300 is formed in the through-hole 270, and a protective layer 303 is formed in the through-hole 273. The formation of the protective layer 300 is one of the novel aspects of the present invention, which is not implemented in conventional semiconductor fabrication processes. The protective layers 300 and 303 help prevent inadvertent puncturing of the various components during a via etching process that will be performed later (discussed in more detail below). In other words, the protective layer 300-303 reduces the likelihood of inadvertently creating a leakage path that will later lead to an undesirable electrical short problem. Wherein the protective layer 300 may help cover the spacers 240A-240B even if the through-holes 270 are laterally offset with respect to the through-holes 230. This helps prevent inadvertent etching of the spacers 240A-240B. The function of the protective layer 300 and 303 will be discussed in more detail below with reference to fig. 3-4.
In order to fully exert their protective function, the protective layers 300-303 have a material composition such that they have sufficient etching selectivity with respect to the materials of the spacers 240A-240B, the etch stop layer 200, and the hard mask 130-133. In the illustrated embodiment, this means that the protective layers 300-303 have an etch selectivity to silicon nitride. This means that the protective layer 300-303 and the silicon nitride will have substantially different etch rates during the etching process. In some embodiments, the silicon nitride will be etched away at a significantly higher rate (e.g., 10 times or 20 times higher) than the protective layer 300-303. By way of example, the protective layer 300-303 comprises a polymer material. In various embodiments, the polymer material may include, for example, CH4Or it may comprise, for example
Figure GDA0002465810860000081
A methylene or methylene bridge of (a). In an alternative embodiment, the protective layer 300-303 may comprise another suitable material having a sufficiently high etch selectivity relative to the materials of the spacers 240A-240B and the hard mask 130-133 (e.g., a high etch selectivity relative to silicon nitride).
The protective layer 300-303 may be formed using a deposition process 310. In some embodiments, in having CH4The deposition process 310 is performed in a deposition chamber of the precursors. The deposition chamber may be filled with a plasma (with a reactive cathode)Ions). The deposition process 310 can have a pressure between 2 millitorr (m-Torr) and 8m-Torr (e.g., 5 m-Torr). The deposition process 310 may use thermal-chromatography pulsed (TCP) Radio Frequency (RF) power between 400 watts (W) and 800W (e.g., 600W). The deposition process 310 may have a process time (or duration) between 10 seconds and 30 seconds (e.g., 19 seconds). The deposition process 310 may have a temperature between 40 degrees celsius and 60 degrees celsius.
The protective layer 300 is formed to have a thickness 320. In some embodiments, the thickness 320 is in a range between 4 nanometers (nm) and 6 nm. The thickness range is configured such that even after the bottom of the protective layer 300 is removed (in a polymer "punch-through" process to be performed later), the remaining portion of the protective layer 300 may still sufficiently cover any potentially exposed portion of the spacer 240A or 240B.
Referring now to fig. 3, an etch process 330 is performed to "penetrate" the protective layers 300 and 303. As shown in fig. 3, the bottom (the portion above the via 230 and the etch stop layer 200) of the protection layer 300 and 303 is removed by an etching process 330. The removal of the bottom of the protective layers 300 and 303 exposes the etch stop layer 200 (and also exposes the via 230). The exposure of the etch stop layer 200 allows one or more subsequent etch processes to be performed to etch through the etch stop layer 200 and through the hard mask 133 so that the gate electrode 123 may be exposed. At the same time, the side portions of the protective layers 300 and 303 (disposed on the sidewalls of the ILD250 and 220) remain after the etching process 330 is performed, and thus they may still serve their protective function in a subsequent etching process.
Referring now to fig. 4, an etch process 360 is performed to extend the through-holes 273 further down through the etch stop layer 200 and through the hard mask 133. The etch process 360 is configured such that it etches away silicon nitride (the material composition of the etch stop layer 200 and the hard mask 133) without substantially etching away the protective layer 300-. Thus, as a result of the etching process 360, the gate electrode 123 is exposed.
As described above, the protection provided by protective layer 300 is important because it prevents the formation of undesirable leakage paths. In more detail, if the protection layer 300 is not formed, a leakage path may be unintentionally formed through the etching process 360. This is illustrated in fig. 5, where an exemplary leakage path 400 may be formed as a result of the etching process 360 if the protective layer 300 is not formed.
For example, as described above, the through-hole 270 may unintentionally expose a portion of the spacer 240A or the spacer 240B. Since the material composition for the spacers 240A-240B, the etch stop layer 200 and the hard mask 130-133 is silicon nitride, this means that if the spacers 240A or 240B are exposed by the through-holes 270, the spacers 240A or 240B may also be unintentionally etched away by "opening" the hard mask 133 by the etch process 360 to expose the gate electrode 123. In the example shown, during the etch process 360, portions of the spacers 240B (as exposed through the through-holes 270) are etched away, while portions of the etch stop layer 200, the hard mask 131, and possibly the spacers 151A are also etched away together. Thus, a portion of the gate electrode 121 is exposed. When a deposition process is later performed to fill the vias 270 and 273 with conductive material, the conductive material will also fill the leakage path 400. Thus, the gate electrode 121 will be electrically connected to the via 230 through the conductive material filling the leakage path 400. In other words, the gate electrode 121 will electrically short to the via 230, which may create unforeseen problems and may cause the IC to fail or even suffer from failure.
Referring again to fig. 4, the present invention solves this problem by forming a protective layer 300 to cover the potentially exposed portions of the spacers 240A-240B. As the etch process 360 is performed to further etch the through holes 273 down (until the gate electrodes 123 are exposed), the protective layer 300 protects the underlying spacers 240A-240B from etching. This is due to the etch selectivity between the protective layer 300 (having a polymer material composition) and the spacers 240A-240B (having a silicon nitride material composition), as described above. Thus, it is not possible to form a leakage path (e.g., a leakage path similar to leakage path 400 discussed above with reference to fig. 5). Therefore, an electrical short between the via 230 and the gate electrode 120-121 will not occur.
Referring now to FIG. 6, the passivation layer 300 and 303 are removed. For example, the removal of the protective layer 300-303 may be performed using oxygen and/or hydrogen plasma. Then, a deposition process 450 is performed to fill the through holes 270 and 273 to form conductive vias 470 and 473 therein. Via 470 is electrically connected to vias 230 and 180 and thus provides an electrical connection to source/drain region 50 through vias 230 and 180. The via 473 is electrically connected to the gate electrode 123. Again, if the protective layer 300 is not formed, the vias 230 and 470 may be electrically shorted with the gate electrodes 120 or 121. This will create an electrical short between the gate 100/101 and the source/drain region 50, which will interfere with the intended operation of the transistor. The formation of protective layer 300 prevents the occurrence of such potential device defects and thus improves the quality and integrity of semiconductor device 35.
It should be understood that the above-described process may be applied to FinFET devices such as semiconductor device 35. The use of FinFET devices is becoming increasingly popular in the semiconductor industry. The FinFET device is a fin field effect transistor device. For example, the FinFET device may be a Complementary Metal Oxide Semiconductor (CMOS) device that includes a P-type metal oxide semiconductor (PMOS) FinFET device and an N-type metal oxide semiconductor (NMOS) FinFET device.
Referring to fig. 7, a perspective view of an exemplary FinFET device 550 is shown. FinFET device 550 is a non-planar multi-gate transistor built over a substrate, such as a bulk substrate. A thin silicon "fin" structure (referred to as a fin) forms the body of the FinFET device 550. The fin has a fin width WFin. The gate 560 of the FinFET device 550 wraps around this fin. Lg represents the length (or width, depending on the perspective view) of the gate 560. Gate 560 may include a gate electrode assembly 560A and a gate dielectric assembly 560B. Gate dielectric 560B has a thickness tox. Portions of the gate 560 are located on a dielectric isolation structure, such as a Shallow Trench Isolation (STI). The source 570 and drain 580 of the FinFET device 550 are formed in extensions of the fin on opposite sides of the gate 560. The fin itself acts as a channel. The effective channel length of the FinFET device 550 is determined by the size of the fin.
FinFET devices offer several advantages over traditional Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices, also known as planar devices. These advantages may include better chip area efficiency, improved carrier mobility, and a fabrication process that is compatible with the fabrication process of planar devices. Accordingly, it is desirable to design an Integrated Circuit (IC) chip for a portion of the IC chip or the entire IC chip using FinFET devices. However, it should be understood that the inventive process discussed above may also be applied to non-FinFET devices, such as conventional planar devices.
Fig. 8 is a flow chart of a method 600 for fabricating a semiconductor device in accordance with various aspects of the present invention. The method 600 includes a step 610 of receiving a semiconductor device including a first interlayer dielectric (ILD) and a second ILD disposed over the first ILD. A first via is disposed in the first ILD, and wherein a spacer is disposed on a sidewall of the first via. In some embodiments, the spacer has a first material composition and the first ILD or the second ILD has a second material composition different from the first material composition.
The method 600 includes a step 620 of forming a through via in the second ILD. The through hole exposes the first through hole.
The method 600 includes a step 630 of forming a protective layer in the through vias. In some embodiments, the forming of the protective layer includes forming the protective layer to include a material different from the first dielectric material.
The method 600 includes a step 640 of performing an etch process after forming the protective layer. In some embodiments, the etching process is configured to etch away the first dielectric material, and the spacers comprise the first dielectric material. In some embodiments, the material of the protective layer has an etch selectivity relative to the first dielectric material during the etching process. In some embodiments, the first dielectric material comprises silicon nitride and the material of the protective layer comprises a polymer.
In some embodiments, the semiconductor device further includes a gate disposed under the first ILD. The gate includes a gate electrode and a hard mask disposed over the gate electrode, and an etch process removes portions of the hard mask to expose the gate electrode. In some embodiments, the hard mask and the spacer have the same material composition.
It should be understood that additional steps may be performed before, during, or after steps 610-640. For example, the method 600 may include the steps of: the bottom of the protective layer is removed prior to the etching process. The first portion of the spacer is exposed through the through hole before forming the protective layer. After removing the bottom portion, the remaining portion of the protective layer still covers the first portion of the spacer. In some embodiments, the remaining portion of the protective layer protects the first portion of the spacer from etching during the etching process. As another example, method 600 may include the step of removing the protective via and then forming a second conductive via in the through via.
Based on the above discussion, it can be seen that the present invention provides advantages over conventional semiconductor device fabrication. However, it is to be understood that other embodiments may provide additional advantages, and that not all advantages need be disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that by forming a protective layer in the through-hole as described above, the present invention prevents the formation of a leakage path that may cause an electrical short. The protective layer covers the spacers around the through-holes, which may otherwise be exposed through the through-holes. Since the spacers and the hard mask have the same material composition (e.g., silicon nitride), performing an etch process that opens the hard mask (as part of forming the via to provide electrical connection to the gate electrode) may also inadvertently etch away the unintentionally exposed spacers, which may form a leakage path between the via and the underlying gate electrode. When a subsequent deposition process is performed to fill the through-hole, the gate electrode may be electrically shorted with the via hole. Here, the presence of the protective layer substantially reduces this risk because the protective layer has a high etch selectivity with respect to the spacers and the hard mask during the etching process. Thus, the protective layer may prevent inadvertent etching of the spacer during the etching process, thereby reducing the likelihood of an electrical short condition between the via and the gate electrode. Other advantages include compatibility with existing processing steps and ease of implementation. Thus, practicing the invention will not significantly increase manufacturing costs.
One aspect of the present invention relates to a method of manufacturing a semiconductor device. A semiconductor device is received. The semiconductor device includes a first interlayer dielectric (ILD) and a second ILD disposed over the first ILD. A first via is disposed in the first ILD, and a spacer is disposed on a sidewall of the first via. A through via is formed in the second ILD. The through hole exposes the first through hole. A protective layer is formed in the through hole. An etching process is performed after the protective layer is formed.
Another aspect of the invention relates to a method of manufacturing a semiconductor device. A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask over the gate electrode. The hard mask includes a first dielectric material. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises a second dielectric material different from the first dielectric material. A first via is formed in the first ILD. Sidewalls of the first via are surrounded by a spacer comprising a first dielectric material. A second ILD is formed over the first ILD. A through via is formed in the second ILD. The through hole exposes the first through hole. A protective layer is formed in the through hole. And removing the bottom of the protective layer. Thereafter, an etching process is performed. The remaining portion of the protective layer prevents etching of the spacers during the etching process.
Another aspect of the invention relates to a method of manufacturing a semiconductor device. A gate structure is formed over a substrate. The gate structure includes a gate electrode and a hard mask over the gate electrode. The hard mask comprises silicon nitride. A first interlayer dielectric (ILD) is formed over the gate structure. The first ILD comprises silicon oxide. A first via is formed in the first ILD. The sidewalls of the first via are surrounded by a spacer comprising silicon nitride. A second ILD is formed over the first ILD. The second ILD comprises silicon nitride. A through via is formed in the second ILD. The through hole exposes the through hole and exposes the first portion of the spacer. A protective layer is formed in the through hole. The protective layer includes a polymer. And removing the bottom of the protective layer. The remaining portion of the protective layer still covers the first portion of the spacer. An etch process is performed to remove portions of the hard mask such that portions of the gate electrode are exposed. The polymer has an etch selectivity to silicon nitride such that the remaining portion of the protective layer prevents inadvertent etching of the spacer during the etching process.
According to some embodiments of the present invention, there is provided a method of manufacturing a semiconductor device, including: receiving a semiconductor device comprising a first interlayer dielectric (ILD) and a second interlayer dielectric disposed over the first interlayer dielectric, wherein a first via is disposed in the first interlayer dielectric, and wherein a spacer is disposed on a sidewall of the first via; forming a through hole in the second interlayer dielectric, the through hole exposing the first through hole; forming a protective layer in the through hole; and performing an etching process after forming the protective layer.
In the above method, further comprising: removing a bottom portion of the protective layer prior to the etching process.
In the above method, before forming the protective layer, the first portion of the spacer is exposed through the through hole; and after removing the bottom portion, a remaining portion of the protective layer still covers the first portion of the spacer.
In the above method, the remaining portion of the protective layer protects the first portion of the spacer from being etched in the etching process.
In the above method, the etching process is configured to etch away the first dielectric material; and the spacer comprises the first dielectric material.
In the above method, the forming of the protective layer includes forming the protective layer, a material of the protective layer being different from the first dielectric material.
In the above method, the material of the protective layer has an etch selectivity to the first dielectric material during the etching process.
In the above method, the first dielectric material comprises silicon nitride; and the material of the protective layer comprises a polymer.
In the above method, the spacer has a first material composition, and the first interlayer dielectric or the second interlayer dielectric has a second material composition different from the first material composition.
In the above method, the semiconductor device further comprises a gate disposed under the first interlayer dielectric; the gate includes a gate electrode and a hard mask over the gate electrode; and the etching process removes portions of the hard mask to expose the gate electrode.
In the above method, the hard mask and the spacer have the same material composition.
In the above method, further comprising: a second conductive via is formed in the through-hole.
In the above method, further comprising: removing the protective layer before forming the second conductive via.
According to further embodiments of the present invention, there is also provided a method of manufacturing a semiconductor device, including: forming a gate structure over a substrate, the gate structure comprising a gate electrode and a hard mask over the gate electrode, wherein the hard mask comprises a first dielectric material; forming a first interlayer dielectric (ILD) over the gate structure, wherein the first interlayer dielectric comprises a second dielectric material different from the first dielectric material; forming a first via in the first interlayer dielectric, wherein a sidewall of the first via is surrounded by a spacer comprising the first dielectric material; forming a second interlayer dielectric over the first interlayer dielectric; forming a through hole in the second interlayer dielectric, the through hole exposing the first through hole; forming a protective layer in the through hole; removing the bottom of the protective layer; and thereafter performing an etching process, wherein the remaining portion of the protective layer prevents etching of the spacer during the etching process.
In the above method, the etching process is configured to etch away the first dielectric material; and during the etching process, the protective layer comprises a material having an etch selectivity to the first dielectric material.
In the above method, the first dielectric material comprises silicon nitride; and the material of the protective layer comprises a polymer.
In the above method, the etching process is configured to etch away a portion of the hard mask to expose the gate electrode.
In the above method, further comprising: removing the protective layer after the etching process; and forming a second conductive via in the through hole after removing the protective layer.
There is also provided, in accordance with yet other embodiments of the present invention, a method of manufacturing a semiconductor device, including: forming a gate structure over a substrate, the gate structure comprising a gate electrode and a hard mask over the gate electrode, wherein the hard mask comprises silicon nitride; forming a first interlayer dielectric (ILD) over the gate structure, wherein the first interlayer dielectric comprises silicon oxide; forming a first via in the first interlayer dielectric, wherein a sidewall of the first via is surrounded by a spacer comprising silicon nitride; forming a second interlayer dielectric over the first interlayer dielectric, wherein the second interlayer dielectric comprises silicon nitride; forming a through hole in the second interlayer dielectric, the through hole exposing the through hole and exposing a first portion of the spacer; forming a protective layer in the through-hole, wherein the protective layer includes a polymer; removing a bottom portion of the protective layer, wherein a remaining portion of the protective layer still covers the first portion of the spacer; and performing an etch process to remove portions of the hard mask to expose portions of the gate electrode, wherein the polymer has an etch selectivity to the silicon nitride such that remaining portions of the protective layer prevent the spacers from being inadvertently etched during the etch process.
In the above method, further comprising: removing the protective layer after the etching process; and then forming a second conductive via in the through-hole.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (20)

1. A method of manufacturing a semiconductor device, comprising:
receiving a semiconductor device comprising a first interlayer dielectric (ILD) and a second interlayer dielectric disposed over the first interlayer dielectric, wherein a first via is disposed in the first interlayer dielectric, and wherein a spacer is disposed on a sidewall of the first via;
forming a through hole in the second interlayer dielectric, the through hole exposing the first through hole;
forming a protective layer in the through hole; and
an etching process is performed after removing the bottom of the protective layer,
wherein, prior to forming the protective layer, a first portion of the spacer is exposed through the through hole; and
after removing the bottom portion, a remaining portion of the protective layer still covers the first portion of the spacer.
2. The method of claim 1, further comprising: after the etching process, the remaining portion of the protective layer is removed.
3. The method of claim 1, wherein:
forming the protective layer includes forming methane, methylene, or a methylene bridge into the protective layer.
4. The method of claim 3, wherein the remaining portion of the protective layer protects the first portion of the spacer from etching during the etching process.
5. The method of claim 1, wherein:
the etching process is configured to etch away the first dielectric material; and
the spacer includes the first dielectric material.
6. The method of claim 5, wherein the forming of the protective layer comprises forming the protective layer of a material different from the first dielectric material.
7. The method of claim 6, wherein a material of the protective layer has an etch selectivity to the first dielectric material during the etching process.
8. The method of claim 6, wherein:
the first dielectric material comprises silicon nitride; and
the material of the protective layer comprises a polymer.
9. The method of claim 1, wherein the spacer has a first material composition and the first interlayer dielectric or the second interlayer dielectric has a second material composition different from the first material composition.
10. The method of claim 1, wherein:
the semiconductor device further includes a gate disposed below the first interlayer dielectric;
the gate includes a gate electrode and a hard mask over the gate electrode; and
the etch process removes portions of the hard mask to expose the gate electrode.
11. The method of claim 10, wherein the hard mask and the spacer have the same material composition.
12. The method of claim 1, further comprising: a second conductive via is formed in the through-hole.
13. The method of claim 12, further comprising: removing the protective layer before forming the second conductive via.
14. A method of manufacturing a semiconductor device, comprising:
forming a gate structure over a substrate, the gate structure comprising a gate electrode and a hard mask over the gate electrode, wherein the hard mask comprises a first dielectric material;
forming a first interlayer dielectric (ILD) over the gate structure, wherein the first interlayer dielectric comprises a second dielectric material different from the first dielectric material;
forming a first via in the first interlayer dielectric, wherein a sidewall of the first via is surrounded by a spacer comprising the first dielectric material;
forming a second interlayer dielectric over the first interlayer dielectric;
forming a through hole in the second interlayer dielectric, the through hole exposing the first through hole;
forming a protective layer in the through hole;
removing the bottom of the protective layer; and
an etching process is then performed, wherein the remaining portion of the protective layer prevents etching of the spacer during the etching process.
15. The method of claim 14, wherein:
the etching process is configured to etch away the first dielectric material; and
during the etching process, the protective layer includes a material having an etch selectivity to the first dielectric material.
16. The method of claim 15, wherein:
the first dielectric material comprises silicon nitride; and
the material of the protective layer comprises a polymer.
17. The method of claim 14, wherein the etching process is configured to etch away portions of the hard mask to expose the gate electrode.
18. The method of claim 14, further comprising:
removing the protective layer after the etching process; and
after removing the protective layer, a second conductive via is formed in the through hole.
19. A method of manufacturing a semiconductor device, comprising:
forming a gate structure over a substrate, the gate structure comprising a gate electrode and a hard mask over the gate electrode, wherein the hard mask comprises silicon nitride;
forming a first interlayer dielectric (ILD) over the gate structure, wherein the first interlayer dielectric comprises silicon oxide;
forming a first via in the first interlayer dielectric, wherein a sidewall of the first via is surrounded by a spacer comprising silicon nitride;
forming a second interlayer dielectric over the first interlayer dielectric, wherein the second interlayer dielectric comprises silicon nitride;
forming a through hole in the second interlayer dielectric, the through hole exposing the through hole and exposing a first portion of the spacer;
forming a protective layer in the through-hole, wherein the protective layer includes a polymer;
removing a bottom portion of the protective layer, wherein a remaining portion of the protective layer still covers the first portion of the spacer; and
an etch process is performed to remove portions of the hard mask to expose portions of the gate electrode, wherein the polymer has an etch selectivity to the silicon nitride such that remaining portions of the protective layer prevent the spacers from being inadvertently etched during the etch process.
20. The method of claim 19, further comprising:
removing the protective layer after the etching process; and
a second conductive via is then formed in the through via.
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