CN108122757B - Semiconductor structure and its manufacturing method - Google Patents
Semiconductor structure and its manufacturing method Download PDFInfo
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- CN108122757B CN108122757B CN201611073169.5A CN201611073169A CN108122757B CN 108122757 B CN108122757 B CN 108122757B CN 201611073169 A CN201611073169 A CN 201611073169A CN 108122757 B CN108122757 B CN 108122757B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 61
- 239000002184 metal Substances 0.000 claims abstract description 61
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 239000000463 material Substances 0.000 claims description 44
- 125000006850 spacer group Chemical group 0.000 claims description 29
- 229910052797 bismuth Inorganic materials 0.000 claims description 6
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- 229910000859 α-Fe Inorganic materials 0.000 claims description 5
- WSMQKESQZFQMFW-UHFFFAOYSA-N 5-methyl-pyrazole-3-carboxylic acid Chemical compound CC1=CC(C(O)=O)=NN1 WSMQKESQZFQMFW-UHFFFAOYSA-N 0.000 claims description 4
- 239000002253 acid Substances 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052744 lithium Inorganic materials 0.000 claims description 2
- CWYNVVGOOAEACU-UHFFFAOYSA-N Fe2+ Chemical group [Fe+2] CWYNVVGOOAEACU-UHFFFAOYSA-N 0.000 claims 1
- 239000002019 doping agent Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910002902 BiFeO3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005621 ferroelectricity Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Present invention discloses a kind of semiconductor structure and its manufacturing methods.In the manufacturing method of semiconductor structure provided by the invention, including provide a substrate；Fin structure is formed over the substrate；The two sides of the fin structure of exposure form germanium-silicon layer over the substrate；Side wall is formed away from the side of the fin structure in the germanium-silicon layer；First grid metal layer is formed away from the side of the germanium-silicon layer in the side wall；Ferroelectric layer is formed away from the side of the side wall in the first grid metal layer；And second grid metal layer is formed away from the side of the first grid metal layer in the ferroelectric layer.Thus obtained semiconductor structure, the concentration of dopant that short channel in the prior art can be improved is big, the situation of short channel damage (SCE) is generated to the short channel of semiconductor structure, and contact resistance can be reduced, to obtain lower supply voltage (Vdd), the performance of semiconductor structure is significantly improved.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of semiconductor structure and its manufacturing method.
Background technique
In advanced complementary metal oxide semiconductor (CMOS) industry, with 22nm and smaller size of arrival, in order to
Improve short-channel effect and improves the performance of device, fin formula field effect transistor (Fin Field-effect transistor,
FinFET it) is widely used by its unique structure.
FinFET is a kind of special metal oxide semiconductor field effect tube, and structure is usually silicon substrate on insulator
On piece is formed, including narrow and independent silicon strip, as vertical channel structure, also referred to as fin, is arranged in the two sides of fin
There is gate structure.Specifically as shown in Figure 1, the structure of FinFET in the prior art a kind of includes: substrate 10, source electrode 11, drain electrode
12, fin 13 and it is centered around the gate structure 14 of 13 two sides of fin and top.
But still there is needs to be enhanced place by FinFET, for example, contact resistance is higher, in the fabrication process can
Cause short channel damage etc..
Summary of the invention
The purpose of the present invention is to provide a kind of semiconductor structure and its manufacturing methods, improve short channel damage, and reduction connects
Electric shock resistance.
To solve the technical problem, the present invention provides a kind of manufacturing method of semiconductor structure, comprising:
One substrate is provided；
Fin structure is formed over the substrate；
The two sides of the fin structure of exposure form germanium-silicon layer over the substrate；
Side wall is formed away from the side of the fin structure in the germanium-silicon layer；
First grid metal layer is formed away from the side of the germanium-silicon layer in the side wall；
Ferroelectric layer is formed away from the side of the side wall in the first grid metal layer；And
Second grid metal layer is formed away from the side of the first grid metal layer in the ferroelectric layer.
Optionally, for the manufacturing method of the semiconductor structure, the width of the germanium-silicon layer is 5nm-50nm.
Optionally, for the manufacturing method of the semiconductor structure, there is the first oxide layer, the fin on the substrate
Formula structure runs through first oxide layer, and the upper surface of the fin structure is higher than the upper surface of first oxide layer.
Optionally, for the manufacturing method of the semiconductor structure, in the germanium-silicon layer away from the fin structure
Side formed side wall the step of include:
Mask layer is formed in the fin structure；
Spacer material layer is formed, the spacer material layer covers the mask layer, germanium-silicon layer and first oxide layer；
Sacrificial layer is formed, the sacrificial layer covers the spacer material layer；
Removal is located at sacrificial layer and spacer material layer in first oxide layer, and removes sacrificial above mask layer
Domestic animal layer, remaining spacer material layer cover the mask layer and germanium-silicon layer, and remaining sacrificial layer is located at spacer material layer back
Side from the germanium-silicon layer；
The second oxide layer is formed in first oxide layer；
Remove the portion that the sacrificial layer is higher than the fin structure higher than the part of the fin structure and spacer material layer
Point, the mask layer is exposed, the remaining spacer material layer forms side wall.
Optionally, for the manufacturing method of the semiconductor structure, deviate from the side of the germanium-silicon layer in the side wall
Formed first grid metal layer the step of include:
The sacrificial layer is removed to form opening；
First grid metal layer is formed in said opening.
Optionally, for the manufacturing method of the semiconductor structure, the width of the first grid metal layer is
Optionally, for the manufacturing method of the semiconductor structure, deviate from the side in the first grid metal layer
The side of wall forms the step of ferroelectric layer and includes:
The segment thickness of second oxide layer is thinned；
Ferroelectric material layer is formed in second oxide layer using atom layer deposition process；
It etches the ferroelectric material layer and forms the ferroelectric layer.
Optionally, for the manufacturing method of the semiconductor structure, the material of the ferroelectric layer is bismuth ferrite or tantalic acid
Lithium.
Optionally, for the manufacturing method of the semiconductor structure, the width of the ferroelectric layer is 1nm-20nm.
Optionally, for the manufacturing method of the semiconductor structure, the width of the second grid metal layer is
The present invention also provides a kind of semiconductor structures, comprising:
One substrate,
Fin structure on the substrate；
The germanium-silicon layer of the fin structure two sides of exposure on the substrate；
Positioned at the germanium-silicon layer away from the side wall of the side of the fin structure；
Positioned at the side wall away from the first grid metal layer of the side of the germanium-silicon layer；
Positioned at the first grid metal layer away from the ferroelectric layer of the side of the side wall；
Positioned at the ferroelectric layer away from the second grid metal layer of the side of the first grid metal layer.
Optionally, for the semiconductor structure, the width of the germanium-silicon layer is 5nm-50nm.
Optionally, for the semiconductor structure, there is the first oxide layer on the substrate, the fin structure runs through
First oxide layer, the upper surface of the fin structure are higher than the upper surface of first oxide layer.
Optionally, for the semiconductor structure, the width of the first grid metal layer is
Optionally, for the semiconductor structure, the material of the ferroelectric layer is bismuth ferrite or lithium tantalate.
Optionally, for the semiconductor structure, the width of the ferroelectric layer is 1nm-20nm.
Optionally, for the semiconductor structure, the width of the second grid metal layer is
In the manufacturing method of semiconductor structure provided by the invention, including provide a substrate；Fin is formed over the substrate
Formula structure；The two sides of the fin structure of exposure form germanium-silicon layer over the substrate；Deviate from the fin in the germanium-silicon layer
The side of formula structure forms side wall；First grid metal layer is formed away from the side of the germanium-silicon layer in the side wall；Described
First grid metal layer forms ferroelectric layer away from the side of the side wall；And in the ferroelectric layer away from the first grid gold
The side for belonging to layer forms second grid metal layer.Thus obtained semiconductor structure can improve short channel in the prior art
Concentration of dopant is big, and the situation of short channel damage (SCE) is generated to the short channel of semiconductor structure, and can reduce contact electricity
Resistance, to obtain lower supply voltage (Vdd), significantly improves the performance of semiconductor structure.
Detailed description of the invention
Fig. 1 is the schematic diagram of FinFET structure in the prior art；
Fig. 2 is the flow chart of the manufacturing method of semiconductor structure in the present invention；
Fig. 3 is the schematic diagram of the substrate provided in an embodiment in the present invention；
Fig. 4 is the schematic diagram for forming fin structure in the present invention in an embodiment；
Fig. 5 is to form the schematic diagram of germanium-silicon layer in fin structure two sides in an embodiment in the present invention；
Fig. 6-Fig. 8 is the schematic diagram for forming side wall in the present invention in an embodiment；
Fig. 9 is the schematic diagram for forming first grid metal layer in the present invention in an embodiment；
Figure 10 is the schematic diagram that ferroelectric layer is formed in one embodiment of the invention；
Figure 11 is the schematic diagram that second grid metal layer is formed in one embodiment of the invention.
Specific embodiment
Semiconductor structure and its manufacturing method of the invention are described in more detail below in conjunction with schematic diagram, wherein
Illustrating the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can modify invention described herein, and still
So realize advantageous effects of the invention.Therefore, following description should be understood as the widely known of those skilled in the art,
And it is not intended as limitation of the present invention.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Core of the invention thought is to provide a kind of manufacturing method of semiconductor structure, with improve semiconductor structure (such as
CMOS structure) performance.The manufacturing method of the semiconductor structure includes:
Step S11 provides a substrate；
Step S12, forms fin structure over the substrate；
Step S13, the two sides of the fin structure of exposure form germanium-silicon layer over the substrate；
Step S14 forms side wall away from the side of the fin structure in the germanium-silicon layer；
Step S15 forms first grid metal layer away from the side of the germanium-silicon layer in the side wall；
Step S16 forms ferroelectric layer away from the side of the side wall in the first grid metal layer；And
Step S17 forms second grid metal layer away from the side of the first grid metal layer in the ferroelectric layer.
Semiconductor structure and its manufacturing method of the invention are described in detail below with reference to Fig. 2-Figure 11.Wherein Fig. 2
For the flow chart of the manufacturing method of the semiconductor structure in one embodiment of the invention；Fig. 3-Figure 11 is half in one embodiment of the invention
The structural schematic diagram of the manufacturing method of conductor structure in the fabrication process.
Fig. 2 and Fig. 3 are please referred to, in the manufacturing method of semiconductor structure of the invention, specifically, for step S11, institute
The constituent material for stating substrate 100 can use undoped monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI)
Deng.As an example, in the present embodiment, substrate 100 selects single crystal silicon material to constitute.It can also be formed in the substrate 100
There is buried layer (not shown) etc..In addition, can also be formed with N trap for PMOS in the substrate 100 and (not show in figure
Out), and before forming gate structure, one or many low dose of boron injections can be carried out to entire N trap, for adjusting
The threshold voltage vt h of PMOS.
As shown in figure 4, the step S12 is to form fin structure 102 on the substrate 100；Specifically, can be first
A mask layer 101 is formed on the substrate 100, the mask layer, which is located at, will form at the region of fin structure 102, then
It is exposure mask with the mask layer 101, etches the substrate 100, forms a protrusion as fin structure 102, later, in the substrate
The first oxide layer 103, for example, silica are formed on 100, first oxide layer 103 can be depositing operation and be formed, can also
To be that thermal oxidation technology is formed.First oxide layer 103 covers the segment thickness of the fin structure 102, i.e., the described fin
Structure 102 runs through first oxide layer 103, and the upper surface of the fin structure 102 is higher than the upper of first oxide layer 103
Surface.As needed, heavy doping processing can also be carried out to the fin structure 102, certainly, dopant dose does not limit herein
Fixed, those skilled in the art can be according to needing flexible choice.
Then, referring to FIG. 5,102 two sides of the fin structure that step S13 is the exposure on the substrate 100 are formed
SiGe (SiGe) layer 104；This step S13 can be completed using the prior art, such as be carried out using silicon-containing gas and germanic gas
Chemical vapor deposition (CVD) is completed.For example, the width (i.e. as shown in the figure in lateral size, similarly hereinafter) of the germanium-silicon layer 104
It can be 5nm-50nm, preferably to realize that it adjusts the effect of stress.
Step S14 is to form side wall 106 away from the side of the fin structure 102 in the germanium-silicon layer 104；Specifically,
Referring to FIG. 6, being initially formed spacer material layer 1051, the spacer material layer 1051 covers the mask layer 101, germanium-silicon layer
104 and first oxide layer 103；The spacer material layer 1051 is, for example, high-K dielectric layer, and dielectric constant may be greater than
In 10.Spacer material layer 1051 described here is mainly formed at the germanium-silicon layer 104, as shown in fig. 6, far from SiGe
The spacer material layer 1051 in the first oxide layer 103 at layer 104 is simultaneously few.
Then, sacrificial layer 106 is formed, the sacrificial layer 106 covers the spacer material layer 1051；In the embodiment of the present invention
In, the material of the sacrificial layer 106 is, for example, polysilicon, and the sacrificial layer 106 will be removed later, in order to form the first grid
Pole metal layer 108 (as shown in Figure 9).
It is of course also possible to be to execute a step etching process after the formation of spacer material layer 1051, the first oxide layer will be located at
A thin layer removal on 103, re-forms sacrificial layer 106.
Then, referring to FIG. 7, removal is located at sacrificial layer 106 and spacer material layer in first oxide layer 103
1051, and the sacrificial layer 106 for being located at 101 top of mask layer is removed, remaining spacer material layer 1051 covers the mask layer 101
With germanium-silicon layer 104, remaining sacrificial layer 106 is located at the side that the spacer material layer 1051 deviates from the germanium-silicon layer 104, is formed
Structure as shown in Figure 7, this process can be formed via wet etching.Here, due to the spacer material of 106 lower section of sacrificial layer
Layer is relatively thin, and will not generate adverse effect to subsequent technique, therefore and not shown.
Later, referring to FIG. 8, forming the second oxide layer 107 in first oxide layer 103；Second oxide layer
107 material can be consistent with the first oxide layer 103, for example, silica.
After forming the second oxide layer 107, a step platform chemical industry skill is executed, removes the sacrificial layer 106 higher than described
The part of fin structure 102 and spacer material layer 1051 are higher than the part of the fin structure 102, expose the mask layer
101, the remaining spacer material layer 1051 forms side wall 105.
Specifically, for step S15, referring to FIG. 9, being formed in the side wall 105 away from the side of the germanium-silicon layer 104
First grid metal layer 108 can be and first go to be open divided by formation by the sacrificial layer 106, such as can be and carved using wet process
Erosion is completed；Then first grid metal layer 108 is formed in said opening, can be formed using sputtering technology, the first grid
The width of pole metal layer 108 is
Later, as shown in Figure 10, for step S16, in the first grid metal layer 108 away from the side wall 105
Side forms ferroelectric layer 109, can be the segment thickness that second 107 layers of the oxidation is thinned, and can be completed using wet etching,
Then ferroelectric material layer is formed in second oxide layer 107 using atom layer deposition process, further etches ferroelectricity later
Material layer forms the ferroelectric layer 109.Specifically, the width of the ferroelectric layer is 1nm-20nm, the material of the ferroelectric layer 109
It can be bismuth ferrite (BiFeO3) or lithium tantalate (LiTaO3), it is of course also possible to be other ferroelectrics, the present invention is herein not
It is enumerated.
Finally, please referring to Figure 11, step S17 is carried out, deviates from the first grid metal layer 108 in the ferroelectric layer 109
Side form second grid metal layer 110, the width of the second grid metal layer 110 is
So far, semiconductor structure of the invention, which manufactures, completes, please continue to refer to Figure 11, semiconductor structure packet of the invention
It includes:
One substrate 100；
The first oxide layer 103 on the substrate 100；
Run through the fin structure 102 of first oxide layer 103 on the substrate 100；
The germanium-silicon layer 104 of 102 two sides of the fin structure of exposure on the substrate 100, specifically, the SiGe
The width of layer 104 is 5nm-50nm；
Positioned at the germanium-silicon layer 104 away from the side wall 105 of the side of the fin structure 102；
Positioned at the side wall 105 away from the first grid metal layer 108 of the side of the germanium-silicon layer 104, specifically, described
The width of first grid metal layer 108 is
The second oxide layer 107 in first oxide layer 103；
(specifically it is located in second oxide layer 107) first grid metal layer 108 on the substrate 100 to deviate from
The ferroelectric layer 109 of the side of the side wall 105, specifically, the material of the ferroelectric layer 109 be bismuth ferrite or lithium tantalate, it is described
The width of ferroelectric layer is 1nm-20nm；
Positioned at ferroelectric layer 109 away from the second grid metal layer 110 of the side of the first grid metal layer 108, specifically
, the width of the second grid metal layer 110 is
In conclusion in the manufacturing method of semiconductor structure provided by the invention, including a substrate is provided；In the substrate
Upper formation fin structure；The two sides of the fin structure of exposure form germanium-silicon layer over the substrate；It is carried on the back in the germanium-silicon layer
Side from the fin structure forms side wall；First grid metal is formed away from the side of the germanium-silicon layer in the side wall
Layer；Ferroelectric layer is formed away from the side of the side wall in the first grid metal layer；And in the ferroelectric layer away from described
The side of first grid metal layer forms second grid metal layer.Thus obtained semiconductor structure can improve the prior art
The concentration of dopant of middle short channel is big, generates the situation of short channel damage (SCE) to the short channel of semiconductor structure, and can be with
It reduces contact resistance and significantly improves the performance of semiconductor structure to obtain lower supply voltage (Vdd).
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
Mind and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (17)
1. a kind of manufacturing method of semiconductor structure, comprising:
One substrate is provided；
Fin structure is formed over the substrate；
The two sides of the fin structure of exposure form germanium-silicon layer over the substrate；
Side wall is formed away from the side of the fin structure in the germanium-silicon layer；
First grid metal layer is formed away from the side of the germanium-silicon layer in the side wall；
Ferroelectric layer is formed away from the side of the side wall in the first grid metal layer；And
Second grid metal layer is formed away from the side of the first grid metal layer in the ferroelectric layer.
2. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that the width of the germanium-silicon layer is 5nm-
50nm。
3. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that have the first oxidation on the substrate
Layer, the fin structure run through first oxide layer, and the upper surface of the fin structure is higher than the upper of first oxide layer
Surface.
4. the manufacturing method of semiconductor structure as claimed in claim 3, which is characterized in that deviate from the fin in the germanium-silicon layer
The side of formula structure forms the step of side wall and includes:
Mask layer is formed in the fin structure；
Spacer material layer is formed, the spacer material layer covers the mask layer, germanium-silicon layer and first oxide layer；
Sacrificial layer is formed, the sacrificial layer covers the spacer material layer；
Removal is located at sacrificial layer and spacer material layer in first oxide layer, and removes the sacrifice being located above mask layer
Layer, remaining spacer material layer covers the mask layer and germanium-silicon layer, remaining sacrificial layer are located at the spacer material layer and deviate from
The side of the germanium-silicon layer；
The second oxide layer is formed in first oxide layer；
The part that the sacrificial layer is higher than the fin structure higher than the part of the fin structure and spacer material layer is removed, cruelly
Expose the mask layer, the remaining spacer material layer forms side wall.
5. the manufacturing method of semiconductor structure as claimed in claim 4, which is characterized in that deviate from the SiGe in the side wall
Layer side formed first grid metal layer the step of include:
The sacrificial layer is removed to form opening；
First grid metal layer is formed in said opening.
6. the manufacturing method of semiconductor structure as claimed in claim 1 or 5, which is characterized in that the first grid metal layer
Width be
7. the manufacturing method of semiconductor structure as claimed in claim 4, which is characterized in that carried on the back in the first grid metal layer
Side from the side wall forms the step of ferroelectric layer and includes:
The segment thickness of second oxide layer is thinned；
Ferroelectric material layer is formed in second oxide layer using atom layer deposition process；
It etches the ferroelectric material layer and forms the ferroelectric layer.
8. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that the material of the ferroelectric layer is ferrous acid
Bismuth or lithium tantalate.
9. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that the width of the ferroelectric layer is 1nm-
20nm。
10. the manufacturing method of semiconductor structure as described in claim 1, which is characterized in that the second grid metal layer
Width is
11. a kind of semiconductor structure, comprising:
One substrate,
Fin structure on the substrate；
The germanium-silicon layer of the fin structure two sides of exposure on the substrate；
Positioned at the germanium-silicon layer away from the side wall of the side of the fin structure；
Positioned at the side wall away from the first grid metal layer of the side of the germanium-silicon layer；
Positioned at the first grid metal layer away from the ferroelectric layer of the side of the side wall；
Positioned at the ferroelectric layer away from the second grid metal layer of the side of the first grid metal layer.
12. semiconductor structure as claimed in claim 11, which is characterized in that the width of the germanium-silicon layer is 5nm-50nm.
13. semiconductor structure as claimed in claim 11, which is characterized in that there is the first oxide layer on the substrate, it is described
Fin structure runs through first oxide layer, and the upper surface of the fin structure is higher than the upper surface of first oxide layer.
14. semiconductor structure as claimed in claim 11, which is characterized in that the width of the first grid metal layer is
15. semiconductor structure as claimed in claim 11, which is characterized in that the material of the ferroelectric layer is bismuth ferrite or tantalic acid
Lithium.
16. semiconductor structure as claimed in claim 11, which is characterized in that the width of the ferroelectric layer is 1nm-20nm.
17. semiconductor structure as claimed in claim 11, which is characterized in that the width of the second grid metal layer is
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