CN108111174B - LDPC code sending method, receiving method and device - Google Patents

LDPC code sending method, receiving method and device Download PDF

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CN108111174B
CN108111174B CN201611062142.6A CN201611062142A CN108111174B CN 108111174 B CN108111174 B CN 108111174B CN 201611062142 A CN201611062142 A CN 201611062142A CN 108111174 B CN108111174 B CN 108111174B
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ldpc code
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CN108111174A (en
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吴小宁
姜明
赵春明
马亮
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Huawei Technologies Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices

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Abstract

According to the method provided by the embodiment of the application, when an LDPC code prototype graph corresponding to an LDPC code check matrix provided by the embodiment of the application is adopted for coding, an LDPC code with 1/12 code rates is formed, all rows of the LDPC code prototype graph play a role, except a first row, all rows containing a sub-matrix A provide connectivity between nodes, and other rows provide external information, so that the error rate flat layer can be effectively reduced, and the error correction performance of the LDPC code is improved under the conditions of short code length and unchanged coding and decoding complexity of the LDPC code.

Description

LDPC code sending method, receiving method and device
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method and a device for transmitting and receiving a Low Density Parity Check (LDPC) code.
Background
In a communication system, channel coding can ensure reliable transmission of information data to a receiving device against interference in information transmission. Typically, a transmitting device needs to encode information data to obtain coded bits, interleave the coded bits, map the interleaved bits to modulation symbols, and then process and transmit the modulation symbols over a communication channel. And after receiving the modulation symbols, the receiving equipment restores the modulation symbols into information data through decoding.
The LDPC code has the characteristics of excellent error correction performance, high decoding throughput, simple decoding, and the like, and thus becomes a research hotspot in the field of channel encoding and decoding at present.
The design of the LDPC check matrix determines the overall decoding performance of the LDPC code. First, a parity check matrix H of a binary QC-LDPC code with jzxl dimension is defined, which is described as follows:
Figure BDA0001162830850000011
wherein each small square matrix hj,lJ is 0-J, L is a zero matrix of Z × Z orFor convenience, H can be described by a base matrix B (H) of size J × L:
Figure BDA0001162830850000012
wherein, bj,lIs a numerical value or an array. When h is generatedj,lIs a unit shift matrix, bj,lIs defined as hj,lShift parameter (when h)j,lWhen the unit matrix is circularly shifted to the right, bj,lIs greater than 0; when h is generatedj,lWhen it is a unit array, bj,l0). When h is generatedj,lWhen a plurality of unit shift arrays are superposed to form a multiple cyclic shift array, bj,lIs defined as the followingj,lIs used to determine the shift parameter of (1). In particular, when hj,lIs a zero matrix, bj,lMarked as "blank".
In order to obtain the LDPC check matrix, the check matrix may be constructed by a prototype graph, and in particular, a jxl prototype graph can be described as a matrix form as follows:
Figure BDA0001162830850000021
wherein p isj,lIs a numerical value. The method for constructing the base matrix B (H) by the prototype graph P is as follows: when p isj,lWhen 0, skipping the position when filling the shift parameter; when p isj,lWhen the shift parameter is filled, filling a shift parameter when the shift parameter is filled; when p isj,lWhen i is equal to or greater than 2, an array with i shift parameters is filled in when the shift parameters are filled in.
Therefore, the LDPC code sending method provided by the embodiments of the present application can have the advantages of higher error correction performance and the like under the condition that the coding and decoding complexity is not changed.
Disclosure of Invention
The embodiment of the application provides a method and a device for sending and receiving an LDPC code, which are used for sending the LDPC code with higher error correction performance under the condition of unchanged coding and decoding complexity.
In a first aspect, an embodiment of the present application provides a method for sending an LDPC code, including:
acquiring an LDPC code check matrix;
the LDPC code prototype graph corresponding to the LDPC code check matrix is a matrix with M rows and N columns, the LDPC code prototype graph comprises a first part, a second part, a third part and a fourth part, and each part comprises at least one column of elements; the first part of the LDPC code prototype graph comprises a submatrix C, C, Z, Z, C, A, Z, Z, Z, Z, C, B, B, A, Z, Z, Z, Z, Z, Z, Z, Z, Z in sequence from the 1 st row; the second part of the LDPC code prototype graph comprises a submatrix D, Z, C, Z, Z, A, C, C, A, Z, Z, Z, Z, A, C, B, B, A, Z, Z, Z, Z, Z in sequence from the 1 st row; the third part of the LDPC code prototype graph comprises a submatrix E, Z, Z, C, Z, Z, Z, Z, A, C, Z, Z, Z, Z, Z, Z, Z, Z, A, C, B, B, A in sequence from the 1 st row; the fourth part of the LDPC code prototype graph sequentially comprises a submatrix O, I from the 1 st row; A. b, C, D, E and Z square matrix are M rows and M columns, Z square matrix is M rows and M columns of all-0 matrix, O is M rows and N-3M columns of all-0 matrix, I is M-M rows and N-3M columns of unit matrix;
and coding according to the LDPC code check matrix to obtain the LDPC code and sending the LDPC code.
According to the method provided by the embodiment of the application, when the LDPC code prototype graph corresponding to the LDPC code check matrix provided by the embodiment of the application is adopted for coding, the LDPC code with 1/12 code rates is formed, all rows of the LDPC code prototype graph play a role, except the first row, all rows including the submatrix A provide connectivity between nodes, and other rows provide external information, so that the error rate horizon can be effectively reduced, and the error correction performance of the LDPC code is improved under the conditions that the code length of the LDPC code is short and the coding and decoding complexity is unchanged.
Optionally, m is less than 5;
the row weight of each row in the submatrix A is 1, and the column weight of each column in the submatrix A is 1;
the row weight of each row in the sub-matrix B is 2, and the column weight of each column in the sub-matrix B is 2;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the column weight of each column in the submatrix D is 3, and the row weights are uniformly distributed;
the submatrix E is a lower triangular matrix, and the column weight of each column in the submatrix E is less than or equal to 4.
Optionally, m is greater than or equal to 5;
the row weight of each row in the submatrix A is 3, and the column weight of each column in the submatrix A is 3;
the row weight of each row in the sub-matrix B is 3, and the column weight of each column in the sub-matrix B is 3;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the row weight of each row in the submatrix D is 3, and the column weight of each column in the submatrix D is 3;
the submatrix E is a lower triangular matrix, and the column weight of each column is less than or equal to 4.
Optionally, M is an integer multiple of 22, and N is an integer multiple of 24.
In a second aspect, an embodiment of the present application provides an LDPC code transmitting apparatus, including:
the processing unit is used for acquiring an LDPC code check matrix;
the LDPC code prototype graph corresponding to the LDPC code check matrix is a matrix with M rows and N columns, the LDPC code prototype graph comprises a first part, a second part, a third part and a fourth part, and each part comprises at least one column of elements; the first part of the LDPC code prototype graph comprises a submatrix C, C, Z, Z, C, A, Z, Z, Z, Z, C, B, B, A, Z, Z, Z, Z, Z, Z, Z, Z, Z in sequence from the 1 st row; the second part of the LDPC code prototype graph comprises a submatrix D, Z, C, Z, Z, A, C, C, A, Z, Z, Z, Z, A, C, B, B, A, Z, Z, Z, Z, Z in sequence from the 1 st row; the third part of the LDPC code prototype graph comprises a submatrix E, Z, Z, C, Z, Z, Z, Z, A, C, Z, Z, Z, Z, Z, Z, Z, Z, A, C, B, B, A in sequence from the 1 st row; the fourth part of the LDPC code prototype graph sequentially comprises a submatrix O, I from the 1 st row; A. b, C, D, E and Z square matrix are M rows and M columns, Z square matrix is M rows and M columns of all-0 matrix, O is M rows and N-3M columns of all-0 matrix, I is M-M rows and N-3M columns of unit matrix;
the processing unit is used for coding according to the LDPC code check matrix to obtain an LDPC code;
and the transceiving unit is used for transmitting the LDPC code.
Optionally, m is less than 5;
the row weight of each row in the submatrix A is 1, and the column weight of each column in the submatrix A is 1;
the row weight of each row in the sub-matrix B is 2, and the column weight of each column in the sub-matrix B is 2;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the column weight of each column in the submatrix D is 3, and the row weights are uniformly distributed;
the submatrix E is a lower triangular matrix, and the column weight of each column in the submatrix E is less than or equal to 4.
Optionally, m is greater than or equal to 5;
the row weight of each row in the submatrix A is 3, and the column weight of each column in the submatrix A is 3;
the row weight of each row in the sub-matrix B is 3, and the column weight of each column in the sub-matrix B is 3;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the row weight of each row in the submatrix D is 3, and the column weight of each column in the submatrix D is 3;
the submatrix E is a lower triangular matrix, and the column weight of each column is less than or equal to 4.
Optionally, M is an integer multiple of 22, and N is an integer multiple of 24.
In a third aspect, an embodiment of the present application provides an LDPC code transmitting apparatus, including:
the processor is used for acquiring the LDPC code check matrix;
the LDPC code prototype graph corresponding to the LDPC code check matrix is a matrix with M rows and N columns, the LDPC code prototype graph comprises a first part, a second part, a third part and a fourth part, and each part comprises at least one column of elements; the first part of the LDPC code prototype graph comprises a submatrix C, C, Z, Z, C, A, Z, Z, Z, Z, C, B, B, A, Z, Z, Z, Z, Z, Z, Z, Z, Z in sequence from the 1 st row; the second part of the LDPC code prototype graph comprises a submatrix D, Z, C, Z, Z, A, C, C, A, Z, Z, Z, Z, A, C, B, B, A, Z, Z, Z, Z, Z in sequence from the 1 st row; the third part of the LDPC code prototype graph comprises a submatrix E, Z, Z, C, Z, Z, Z, Z, A, C, Z, Z, Z, Z, Z, Z, Z, Z, A, C, B, B, A in sequence from the 1 st row; the fourth part of the LDPC code prototype graph sequentially comprises a submatrix O, I from the 1 st row; A. b, C, D, E and Z square matrix are M rows and M columns, Z square matrix is M rows and M columns of all-0 matrix, O is M rows and N-3M columns of all-0 matrix, I is M-M rows and N-3M columns of unit matrix;
the processor is used for coding according to the LDPC code check matrix to obtain an LDPC code;
a transceiver for transmitting the LDPC code.
Optionally, m is less than 5;
the row weight of each row in the submatrix A is 1, and the column weight of each column in the submatrix A is 1;
the row weight of each row in the sub-matrix B is 2, and the column weight of each column in the sub-matrix B is 2;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the column weight of each column in the submatrix D is 3, and the row weights are uniformly distributed;
the submatrix E is a lower triangular matrix, and the column weight of each column in the submatrix E is less than or equal to 4.
Optionally, m is greater than or equal to 5;
the row weight of each row in the submatrix A is 3, and the column weight of each column in the submatrix A is 3;
the row weight of each row in the sub-matrix B is 3, and the column weight of each column in the sub-matrix B is 3;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the row weight of each row in the submatrix D is 3, and the column weight of each column in the submatrix D is 3;
the submatrix E is a lower triangular matrix, and the column weight of each column is less than or equal to 4.
Optionally, M is an integer multiple of 22, and N is an integer multiple of 24.
In a fourth aspect, an embodiment of the present application provides a computer storage medium for storing computer software instructions for the LDPC code transmitting apparatus provided in the second aspect, which includes a program for executing the LDPC code transmitting apparatus designed in the first aspect.
In a fifth aspect, an embodiment of the present application provides an LDPC code receiving method, including:
receiving an LDPC code;
decoding the LDPC code according to the LDPC code check matrix;
the LDPC code prototype graph corresponding to the LDPC code check matrix is a matrix with M rows and N columns, the LDPC code prototype graph comprises a first part, a second part, a third part and a fourth part, and each part comprises at least one column of elements; the first part of the LDPC code prototype graph comprises a submatrix C, C, Z, Z, C, A, Z, Z, Z, Z, C, B, B, A, Z, Z, Z, Z, Z, Z, Z, Z, Z in sequence from the 1 st row; the second part of the LDPC code prototype graph comprises a submatrix D, Z, C, Z, Z, A, C, C, A, Z, Z, Z, Z, A, C, B, B, A, Z, Z, Z, Z, Z in sequence from the 1 st row; the third part of the LDPC code prototype graph comprises a submatrix E, Z, Z, C, Z, Z, Z, Z, A, C, Z, Z, Z, Z, Z, Z, Z, Z, A, C, B, B, A in sequence from the 1 st row; the fourth part of the LDPC code prototype graph sequentially comprises a submatrix O, I from the 1 st row; A. b, C, D, E and Z square matrix are M rows and M columns, Z square matrix is M rows and M columns of all-0 matrix, O is M rows and N-3M columns of all-0 matrix, and I is M-M rows and N-3M columns of unit matrix.
According to the method provided by the embodiment of the application, when the LDPC code received by the method is coded by using the LDPC code prototype graph corresponding to the LDPC code check matrix provided by the embodiment of the application, the LDPC code with 1/12 code rates is formed, all rows of the LDPC code prototype graph play a role, except the first row, all rows containing the submatrix A provide connectivity between nodes, and other rows provide external information, so that the error rate flat layer can be effectively reduced, and the error correction performance of the LDPC code is improved under the conditions that the code length of the LDPC code is short and the coding and decoding complexity is unchanged.
Optionally, m is less than 5;
the row weight of each row in the submatrix A is 1, and the column weight of each column in the submatrix A is 1;
the row weight of each row in the sub-matrix B is 2, and the column weight of each column in the sub-matrix B is 2;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the column weight of each column in the submatrix D is 3, and the row weights are uniformly distributed;
the submatrix E is a lower triangular matrix, and the column weight of each column in the submatrix E is less than or equal to 4.
Optionally, m is greater than or equal to 5;
the row weight of each row in the submatrix A is 3, and the column weight of each column in the submatrix A is 3;
the row weight of each row in the sub-matrix B is 3, and the column weight of each column in the sub-matrix B is 3;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the row weight of each row in the submatrix D is 3, and the column weight of each column in the submatrix D is 3;
the submatrix E is a lower triangular matrix, and the column weight of each column is less than or equal to 4.
Optionally, M is an integer multiple of 22, and N is an integer multiple of 24.
In a sixth aspect, an embodiment of the present application provides an LDPC code receiving apparatus, including:
a transceiving unit for receiving the LDPC code;
a processing unit, configured to decode an LDPC code according to an LDPC code check matrix;
the LDPC code prototype graph corresponding to the LDPC code check matrix is a matrix with M rows and N columns, the LDPC code prototype graph comprises a first part, a second part, a third part and a fourth part, and each part comprises at least one column of elements; the first part of the LDPC code prototype graph comprises a submatrix C, C, Z, Z, C, A, Z, Z, Z, Z, C, B, B, A, Z, Z, Z, Z, Z, Z, Z, Z, Z in sequence from the 1 st row; the second part of the LDPC code prototype graph comprises a submatrix D, Z, C, Z, Z, A, C, C, A, Z, Z, Z, Z, A, C, B, B, A, Z, Z, Z, Z, Z in sequence from the 1 st row; the third part of the LDPC code prototype graph comprises a submatrix E, Z, Z, C, Z, Z, Z, Z, A, C, Z, Z, Z, Z, Z, Z, Z, Z, A, C, B, B, A in sequence from the 1 st row; the fourth part of the LDPC code prototype graph sequentially comprises a submatrix O, I from the 1 st row; A. b, C, D, E and Z square matrix are M rows and M columns, Z square matrix is M rows and M columns of all-0 matrix, O is M rows and N-3M columns of all-0 matrix, and I is M-M rows and N-3M columns of unit matrix.
Optionally, m is less than 5;
the row weight of each row in the submatrix A is 1, and the column weight of each column in the submatrix A is 1;
the row weight of each row in the sub-matrix B is 2, and the column weight of each column in the sub-matrix B is 2;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the column weight of each column in the submatrix D is 3, and the row weights are uniformly distributed;
the submatrix E is a lower triangular matrix, and the column weight of each column in the submatrix E is less than or equal to 4.
Optionally, m is greater than or equal to 5;
the row weight of each row in the submatrix A is 3, and the column weight of each column in the submatrix A is 3;
the row weight of each row in the sub-matrix B is 3, and the column weight of each column in the sub-matrix B is 3;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the row weight of each row in the submatrix D is 3, and the column weight of each column in the submatrix D is 3;
the submatrix E is a lower triangular matrix, and the column weight of each column is less than or equal to 4.
Optionally, M is an integer multiple of 22, and N is an integer multiple of 24.
In a seventh aspect, an embodiment of the present application provides an LDPC code receiving apparatus, including:
a transceiver for receiving an LDPC code;
a processor for decoding the LDPC code according to an LDPC code check matrix;
the LDPC code prototype graph corresponding to the LDPC code check matrix is a matrix with M rows and N columns, the LDPC code prototype graph comprises a first part, a second part, a third part and a fourth part, and each part comprises at least one column of elements; the first part of the LDPC code prototype graph comprises a submatrix C, C, Z, Z, C, A, Z, Z, Z, Z, C, B, B, A, Z, Z, Z, Z, Z, Z, Z, Z, Z in sequence from the 1 st row; the second part of the LDPC code prototype graph comprises a submatrix D, Z, C, Z, Z, A, C, C, A, Z, Z, Z, Z, A, C, B, B, A, Z, Z, Z, Z, Z in sequence from the 1 st row; the third part of the LDPC code prototype graph comprises a submatrix E, Z, Z, C, Z, Z, Z, Z, A, C, Z, Z, Z, Z, Z, Z, Z, Z, A, C, B, B, A in sequence from the 1 st row; the fourth part of the LDPC code prototype graph sequentially comprises a submatrix O, I from the 1 st row; A. b, C, D, E and Z square matrix are M rows and M columns, Z square matrix is M rows and M columns of all-0 matrix, O is M rows and N-3M columns of all-0 matrix, and I is M-M rows and N-3M columns of unit matrix.
Optionally, m is less than 5;
the row weight of each row in the submatrix A is 1, and the column weight of each column in the submatrix A is 1;
the row weight of each row in the sub-matrix B is 2, and the column weight of each column in the sub-matrix B is 2;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the column weight of each column in the submatrix D is 3, and the row weights are uniformly distributed;
the submatrix E is a lower triangular matrix, and the column weight of each column in the submatrix E is less than or equal to 4.
Optionally, m is greater than or equal to 5;
the row weight of each row in the submatrix A is 3, and the column weight of each column in the submatrix A is 3;
the row weight of each row in the sub-matrix B is 3, and the column weight of each column in the sub-matrix B is 3;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the row weight of each row in the submatrix D is 3, and the column weight of each column in the submatrix D is 3;
the submatrix E is a lower triangular matrix, and the column weight of each column is less than or equal to 4.
Optionally, M is an integer multiple of 22, and N is an integer multiple of 24.
In an eighth aspect, an embodiment of the present application provides a computer storage medium for storing computer software instructions for the LDPC code receiving apparatus provided in the above sixth aspect, which contains a program designed to execute the above fifth aspect.
Drawings
Fig. 1 is a schematic flow chart of a method for sending an LDPC code according to an embodiment of the present application;
FIG. 2 is a prototype diagram provided in accordance with an embodiment of the present application;
FIG. 3 is a prototype diagram provided in accordance with an embodiment of the present application;
fig. 4 is a schematic flow chart of an LDPC code receiving method according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an LDPC code transmitting apparatus according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an LDPC code transmitting apparatus according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of an LDPC code receiving apparatus according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of an LDPC code receiving apparatus according to an embodiment of the present application.
Detailed Description
The embodiment of the application can be applied to various mobile communication systems, such as: global System for Mobile communications (GSM) systems, Code Division Multiple Access (CDMA) systems, Wideband Code Division Multiple Access (WCDMA) systems, General Packet Radio Service (GPRS), Long Term Evolution (Long Term Evolution, LTE) systems, LTE-a (Advanced Long Term Evolution, LTE-a) systems, UMTS (Universal Mobile telecommunications System, UMTS), LTE (evolved Long Term Evolution, LTE) systems, and other Mobile communication systems such as 5G. The embodiment of the application can also be applied to Wireless Local Area Network (WLAN) and other networks.
Hereinafter, some terms in the present application are explained to facilitate understanding by those skilled in the art.
1) A terminal, also called a User Equipment (UE), is a device providing voice and/or data connectivity to a User, for example, a handheld device with a wireless connection function, a vehicle-mounted device, and so on. Common terminals include, for example: the mobile phone includes a mobile phone, a tablet computer, a notebook computer, a palm computer, a Mobile Internet Device (MID), and a wearable device such as a smart watch, a smart bracelet, a pedometer, and the like.
2) The base station may be a common base station (e.g., a NodeB or an eNB), may be a New radio controller (NR controller), may be a Centralized network element (Centralized Unit), may be a New wireless base station, may be a radio remote module, may be a micro base station, may be a relay (relay), may be a Distributed network element (Distributed Unit), may be a Reception Point (TRP) or a Transmission Point (TP), or any other wireless access device, but the embodiment of the present invention is not limited thereto.
In the optimization of the LDPC code prototype graph, general optimization indexes are: a prototypical extrinsic Information Transfer (PEXIT) threshold, a circle distribution, connectivity between nodes. The PEXIT threshold can predict the convergence threshold of the code word under the conditions of no circle and infinite code length, and provides reference for designing the waterfall area of the LDPC code decoding performance curve. The circle distribution and the connectivity between nodes affect the propagation distance and the propagation effectiveness of the information of the iterative decoding algorithm. They generally affect the size of the minimum stop set or the size of the minimum codeword, and thus the bit error rate floor of LDPC code decoding.
When designing short codes, PEXIT thresholds generally have a weaker impact on performance than the circle distribution and connectivity between nodes. In order to transmit the LDPC code with better performance, the LDPC code prototype graph used in the LDPC code transmitted in the embodiment of the present application is designed to find a balance between threshold and circle distribution and connectivity, so as to obtain the LDPC code with better error correction performance.
Therefore, with reference to the foregoing description, as shown in fig. 1, a flow chart of an LDPC code transmission method provided in an embodiment of the present application is shown.
The main body executing the method flow in fig. 1 may be a terminal, a base station, and other sending devices, which is not limited in this embodiment of the present application. Meanwhile, it should be noted that, in the embodiment of the present application, when the sending device is a terminal, the receiving device may be a base station or other devices; when the sending device is a base station, the receiving device may be a terminal or the like. Of course, this is merely an example, and the sending device and the receiving device are not limited to the above description, and are not illustrated one by one here.
Referring to fig. 1, the method includes:
step 101: and acquiring the LDPC code check matrix.
The LDPC code prototype graph corresponding to the LDPC code check matrix is a matrix with M rows and N columns, the LDPC code prototype graph comprises a first part, a second part, a third part and a fourth part, and each part comprises at least one column of elements; the first part of the LDPC code prototype graph comprises a submatrix C, C, Z, Z, C, A, Z, Z, Z, Z, C, B, B, A, Z, Z, Z, Z, Z, Z, Z, Z, Z in sequence from the 1 st row; the second part of the LDPC code prototype graph comprises a submatrix D, Z, C, Z, Z, A, C, C, A, Z, Z, Z, Z, A, C, B, B, A, Z, Z, Z, Z, Z in sequence from the 1 st row; the third part of the LDPC code prototype graph comprises a submatrix E, Z, Z, C, Z, Z, Z, Z, A, C, Z, Z, Z, Z, Z, Z, Z, Z, A, C, B, B, A in sequence from the 1 st row; the fourth part of the LDPC code prototype graph sequentially comprises a submatrix O, I from the 1 st row; A. b, C, D, E and Z square matrix are M rows and M columns, Z square matrix is M rows and M columns of all-0 matrix, O is M rows and N-3M columns of all-0 matrix, I is M-M rows and N-3M columns of unit matrix;
step 102: and coding according to the LDPC code check matrix to obtain the LDPC code and sending the LDPC code.
In step 101, the LDPC code check matrix is obtained by extending an LDPC code prototype diagram corresponding to the LDPC code check matrix. Specifically, each non-0 element in the submatrix A, B, C, D, E in the LDPC code prototype graph may be expanded into a matrix of k rows and k columns, so as to obtain the LDPC code check matrix, where k takes a value according to actual needs. The LDPC code prototype graph may be expanded by using a Progressive Edge Growth (PEG) method, an Approximate shortest loop (ACE) method, quasi-cyclic expansion (quasi-cyclic) method, and the like, and the specific expansion process may refer to descriptions in the prior art and is not described herein again.
The LDPC code prototype graph corresponding to the LDPC code check matrix may have various forms, and specifically, with reference to the foregoing description, as shown in fig. 2, the LDPC code prototype graph provided in the embodiment of the present application is provided.
In the embodiment of the present application, the LDPC code prototype diagram corresponding to the LDPC code check matrix is a matrix with M rows and N columns, and optionally, M is an integer multiple of 22, and N is an integer multiple of 24. For example, the LDPC code prototype diagram is a matrix of 22 rows and 24 columns or a matrix of 44 rows and 48 columns.
Of course, the LDPC code prototype graph may also be a matrix of other sizes, which is not described herein again.
In the embodiment of the application, when m is less than 5, the row weight of each row in the submatrix a is 1, and the column weight of each column in the submatrix a is 1; the row weight of each row in the sub-matrix B is 2, and the column weight of each column in the sub-matrix B is 2; the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the column weight of each column in the submatrix D is 3, and the row weights are preferably uniformly distributed; the submatrix E is a lower triangular matrix, the column weight of each column is less than or equal to 4, the priority is given, and the majority of the column weight is 3.
For example, the sub-matrices a, B, C, D, E may be matrices as follows:
Figure BDA0001162830850000131
or
Figure BDA0001162830850000132
Or
Figure BDA0001162830850000133
Or
Figure BDA0001162830850000134
Figure BDA0001162830850000135
Or
Figure BDA0001162830850000136
Or
Figure BDA0001162830850000137
Or
Figure BDA0001162830850000138
At this time, the LDPC code prototype diagram may be as shown in fig. 3. The LDPC code prototype diagram in fig. 3 is a matrix of 44 rows and 48 columns, and the element values at the blank are 0.
The terms a, B, C, D, and E include, but are not limited to, a 2 × 2 matrix, and may be a 3 × 3, 4 × 4, and n × n matrix, where n is any positive integer. When the matrix is expanded, the weights of the rows and the columns of A, B and C are ensured to be unchanged, and the lower triangular structure of E is ensured.
In the embodiment of the application, when m is greater than or equal to 5, the row weight of each row in the submatrix a is 3, and the column weight of each column in the submatrix a is 3; the row weight of each row in the sub-matrix B is 3, and the column weight of each column in the sub-matrix B is 3; the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the row weight of each row in the submatrix D is 3, and the column weight of each column in the submatrix D is 3; the submatrix E is a lower triangular matrix, and the column weight of each column in the submatrix E is less than or equal to 4.
For example, the sub-matrices a, B, C, D, E may be matrices as follows:
Figure BDA0001162830850000139
or
Figure BDA00011628308500001310
Or
Figure BDA00011628308500001311
Figure BDA00011628308500001312
In step 102, the process of encoding by using the LDPC check matrix may include: and the coding end codes an information sequence to be sent according to the LDPC code check matrix to obtain a first check sequence (namely, a check sequence corresponding to the pre-punched node) and a second check sequence (namely, a check sequence corresponding to the variable nodes except the information node and the pre-punched node), and punches the first check sequence and the second check sequence to obtain the LDPC code, wherein the LDPC code comprises the information sequence and bits left by punching.
Of course, the above is only an example, and other encoding processes may be available, which are not illustrated in any order.
According to the LDPC code prototype graph provided by the embodiment of the application, when all LDPC code prototype graphs are adopted for coding, the LDPC code with 1/12 code rates is formed, all rows of the LDPC code prototype graph play a role, except the first row, all rows comprising the submatrix A provide connectivity between nodes, and other rows provide external information, so that the error rate flat layer can be effectively reduced, and the error correction performance of the LDPC code is improved under the conditions that the code length of the LDPC code is short and the coding and decoding complexity is not changed.
Optionally, half of the full rate 1/12 coded data is punctured to form a 1/6 rate code. At this time, the first 10 rows of the LDPC code prototype graph function. Connectivity is effected only by the sub-matrix a, and circles are generated by the sub-matrix a except for the first row, which can restrict the formation of small circles in rows other than the first row. Further balancing loop length and connectivity. The coding can further punch check bits, only the data coded by the first 1/4 are transmitted to form 1/3 code rate coding, and only the first four rows of the LDPC code prototype graph play a role. The last three rows of the four rows have no connection relation with each other, provide external information for the first row, and indirectly form a whole, so that the error correction performance of the LDPC code is further improved.
Based on the above description, as shown in fig. 4, a flow chart of an LDPC code receiving method provided in the embodiments of the present application is shown.
The main body executing the method flow in fig. 4 may be a receiving device such as a terminal, a base station, and the like, which is not limited in this embodiment of the application. Meanwhile, it should be noted that, in the embodiment of the present application, when the sending device is a terminal, the receiving device may be a base station or other devices; when the sending device is a base station, the receiving device may be a terminal or the like. Of course, this is merely an example, and the sending device and the receiving device are not limited to the above description, and are not illustrated one by one here.
Referring to fig. 4, the method includes:
step 401: an LDPC code is received.
Step 402: and decoding the LDPC code according to the LDPC code check matrix.
The LDPC code prototype graph corresponding to the LDPC code check matrix is a matrix with M rows and N columns, the LDPC code prototype graph comprises a first part, a second part, a third part and a fourth part, and each part comprises at least one column of elements; the first part of the LDPC code prototype graph comprises a submatrix C, C, Z, Z, C, A, Z, Z, Z, Z, C, B, B, A, Z, Z, Z, Z, Z, Z, Z, Z, Z in sequence from the 1 st row; the second part of the LDPC code prototype graph comprises a submatrix D, Z, C, Z, Z, A, C, C, A, Z, Z, Z, Z, A, C, B, B, A, Z, Z, Z, Z, Z in sequence from the 1 st row; the third part of the LDPC code prototype graph comprises a submatrix E, Z, Z, C, Z, Z, Z, Z, A, C, Z, Z, Z, Z, Z, Z, Z, Z, A, C, B, B, A in sequence from the 1 st row; the fourth part of the LDPC code prototype graph sequentially comprises a submatrix O, I from the 1 st row; A. b, C, D, E and Z square matrix are M rows and M columns, Z square matrix is M rows and M columns of all-0 matrix, O is M rows and N-3M columns of all-0 matrix, and I is M-M rows and N-3M columns of unit matrix.
In step 402, reference may be made to steps 101 to 102 for descriptions of the sub-matrices A, B, C, D, E and M, N, m, etc., which are not described herein again.
The LDPC code check matrix is obtained by extending an LDPC code prototype graph corresponding to the LDPC code check matrix, and a specific extension method is not limited in the present application.
Similarly, how to decode the LDPC code according to the LDPC check matrix is specifically determined, which is not limited in the embodiment of the present application and is not described herein again.
Based on the same technical concept, the embodiment of the present application further provides an LDPC code transmitting apparatus, which may perform the above method embodiments.
Fig. 5 is a schematic structural diagram of an LDPC code transmitting apparatus according to an embodiment of the present application.
Referring to fig. 5, the apparatus includes:
a processing unit 501, configured to obtain an LDPC code check matrix;
the LDPC code prototype graph corresponding to the LDPC code check matrix is a matrix with M rows and N columns, the LDPC code prototype graph comprises a first part, a second part, a third part and a fourth part, and each part comprises at least one column of elements; the first part of the LDPC code prototype graph comprises a submatrix C, C, Z, Z, C, A, Z, Z, Z, Z, C, B, B, A, Z, Z, Z, Z, Z, Z, Z, Z, Z in sequence from the 1 st row; the second part of the LDPC code prototype graph comprises a submatrix D, Z, C, Z, Z, A, C, C, A, Z, Z, Z, Z, A, C, B, B, A, Z, Z, Z, Z, Z in sequence from the 1 st row; the third part of the LDPC code prototype graph comprises a submatrix E, Z, Z, C, Z, Z, Z, Z, A, C, Z, Z, Z, Z, Z, Z, Z, Z, A, C, B, B, A in sequence from the 1 st row; the fourth part of the LDPC code prototype graph sequentially comprises a submatrix O, I from the 1 st row; A. b, C, D, E and Z square matrix are M rows and M columns, Z square matrix is M rows and M columns of all-0 matrix, O is M rows and N-3M columns of all-0 matrix, I is M-M rows and N-3M columns of unit matrix;
the processing unit 501 is configured to perform encoding according to the LDPC code check matrix to obtain an LDPC code;
a transceiving unit 502, configured to transmit the LDPC code.
Optionally, m is less than 5;
the row weight of each row in the submatrix A is 1, and the column weight of each column in the submatrix A is 1;
the row weight of each row in the sub-matrix B is 2, and the column weight of each column in the sub-matrix B is 2;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the column weight of each column in the submatrix D is 3, and the row weights are uniformly distributed;
the submatrix E is a lower triangular matrix, and the column weight of each column in the submatrix E is less than or equal to 4.
Optionally, m is greater than or equal to 5;
the row weight of each row in the submatrix A is 3, and the column weight of each column in the submatrix A is 3;
the row weight of each row in the sub-matrix B is 3, and the column weight of each column in the sub-matrix B is 3;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the row weight of each row in the submatrix D is 3, and the column weight of each column in the submatrix D is 3;
the submatrix E is a lower triangular matrix, and the column weight of each column is less than or equal to 4.
Optionally, M is an integer multiple of 22, and N is an integer multiple of 24.
Based on the same technical concept, the embodiment of the present application further provides an LDPC code transmitting apparatus, which may perform the above method embodiments.
As shown in fig. 6, a schematic structural diagram of an LDPC code transmitting apparatus is provided for the embodiments of the present application.
Referring to fig. 6, the apparatus includes:
a processor 601, configured to obtain an LDPC code check matrix;
the LDPC code prototype graph corresponding to the LDPC code check matrix is a matrix with M rows and N columns, the LDPC code prototype graph comprises a first part, a second part, a third part and a fourth part, and each part comprises at least one column of elements; the first part of the LDPC code prototype graph comprises a submatrix C, C, Z, Z, C, A, Z, Z, Z, Z, C, B, B, A, Z, Z, Z, Z, Z, Z, Z, Z, Z in sequence from the 1 st row; the second part of the LDPC code prototype graph comprises a submatrix D, Z, C, Z, Z, A, C, C, A, Z, Z, Z, Z, A, C, B, B, A, Z, Z, Z, Z, Z in sequence from the 1 st row; the third part of the LDPC code prototype graph comprises a submatrix E, Z, Z, C, Z, Z, Z, Z, A, C, Z, Z, Z, Z, Z, Z, Z, Z, A, C, B, B, A in sequence from the 1 st row; the fourth part of the LDPC code prototype graph sequentially comprises a submatrix O, I from the 1 st row; A. b, C, D, E and Z square matrix are M rows and M columns, Z square matrix is M rows and M columns of all-0 matrix, O is M rows and N-3M columns of all-0 matrix, I is M-M rows and N-3M columns of unit matrix;
the processor 601 is configured to perform encoding according to the LDPC code check matrix to obtain an LDPC code;
a transceiver 602 configured to transmit the LDPC code.
Optionally, m is less than 5;
the row weight of each row in the submatrix A is 1, and the column weight of each column in the submatrix A is 1;
the row weight of each row in the sub-matrix B is 2, and the column weight of each column in the sub-matrix B is 2;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the column weight of each column in the submatrix D is 3, and the row weights are uniformly distributed;
the submatrix E is a lower triangular matrix, and the column weight of each column in the submatrix E is less than or equal to 4.
Optionally, m is greater than or equal to 5;
the row weight of each row in the submatrix A is 3, and the column weight of each column in the submatrix A is 3;
the row weight of each row in the sub-matrix B is 3, and the column weight of each column in the sub-matrix B is 3;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the row weight of each row in the submatrix D is 3, and the column weight of each column in the submatrix D is 3;
the submatrix E is a lower triangular matrix, and the column weight of each column is less than or equal to 4.
Optionally, M is an integer multiple of 22, and N is an integer multiple of 24.
Based on the same technical concept, the embodiment of the present application further provides an LDPC code receiving apparatus, which can execute the above method embodiments.
Fig. 7 is a schematic structural diagram of an LDPC code transmitting and receiving apparatus according to an embodiment of the present application.
Referring to fig. 7, the apparatus includes:
a transceiving unit 701 for receiving an LDPC code;
a processing unit 702, configured to decode an LDPC code according to an LDPC code check matrix;
the LDPC code prototype graph corresponding to the LDPC code check matrix is a matrix with M rows and N columns, the LDPC code prototype graph comprises a first part, a second part, a third part and a fourth part, and each part comprises at least one column of elements; the first part of the LDPC code prototype graph comprises a submatrix C, C, Z, Z, C, A, Z, Z, Z, Z, C, B, B, A, Z, Z, Z, Z, Z, Z, Z, Z, Z in sequence from the 1 st row; the second part of the LDPC code prototype graph comprises a submatrix D, Z, C, Z, Z, A, C, C, A, Z, Z, Z, Z, A, C, B, B, A, Z, Z, Z, Z, Z in sequence from the 1 st row; the third part of the LDPC code prototype graph comprises a submatrix E, Z, Z, C, Z, Z, Z, Z, A, C, Z, Z, Z, Z, Z, Z, Z, Z, A, C, B, B, A in sequence from the 1 st row; the fourth part of the LDPC code prototype graph sequentially comprises a submatrix O, I from the 1 st row; A. b, C, D, E and Z square matrix are M rows and M columns, Z square matrix is M rows and M columns of all-0 matrix, O is M rows and N-3M columns of all-0 matrix, and I is M-M rows and N-3M columns of unit matrix.
Optionally, m is less than 5;
the row weight of each row in the submatrix A is 1, and the column weight of each column in the submatrix A is 1;
the row weight of each row in the sub-matrix B is 2, and the column weight of each column in the sub-matrix B is 2;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the column weight of each column in the submatrix D is 3, and the row weights are uniformly distributed;
the submatrix E is a lower triangular matrix, and the column weight of each column in the submatrix E is less than or equal to 4.
Optionally, m is greater than or equal to 5;
the row weight of each row in the submatrix A is 3, and the column weight of each column in the submatrix A is 3;
the row weight of each row in the sub-matrix B is 3, and the column weight of each column in the sub-matrix B is 3;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the row weight of each row in the submatrix D is 3, and the column weight of each column in the submatrix D is 3;
the submatrix E is a lower triangular matrix, and the column weight of each column is less than or equal to 4.
Optionally, M is an integer multiple of 22, and N is an integer multiple of 24.
Based on the same technical concept, the embodiment of the present application further provides an LDPC code receiving apparatus, which can execute the above method embodiments.
Fig. 8 is a schematic structural diagram of an LDPC code transmitting and receiving apparatus according to an embodiment of the present application.
Referring to fig. 8, the apparatus includes:
a transceiver 801 for receiving LDPC codes;
a processor 802 configured to decode an LDPC code according to an LDPC code check matrix;
the LDPC code prototype graph corresponding to the LDPC code check matrix is a matrix with M rows and N columns, the LDPC code prototype graph comprises a first part, a second part, a third part and a fourth part, and each part comprises at least one column of elements; the first part of the LDPC code prototype graph comprises a submatrix C, C, Z, Z, C, A, Z, Z, Z, Z, C, B, B, A, Z, Z, Z, Z, Z, Z, Z, Z, Z in sequence from the 1 st row; the second part of the LDPC code prototype graph comprises a submatrix D, Z, C, Z, Z, A, C, C, A, Z, Z, Z, Z, A, C, B, B, A, Z, Z, Z, Z, Z in sequence from the 1 st row; the third part of the LDPC code prototype graph comprises a submatrix E, Z, Z, C, Z, Z, Z, Z, A, C, Z, Z, Z, Z, Z, Z, Z, Z, A, C, B, B, A in sequence from the 1 st row; the fourth part of the LDPC code prototype graph sequentially comprises a submatrix O, I from the 1 st row; A. b, C, D, E and Z square matrix are M rows and M columns, Z square matrix is M rows and M columns of all-0 matrix, O is M rows and N-3M columns of all-0 matrix, and I is M-M rows and N-3M columns of unit matrix.
Optionally, m is less than 5;
the row weight of each row in the submatrix A is 1, and the column weight of each column in the submatrix A is 1;
the row weight of each row in the sub-matrix B is 2, and the column weight of each column in the sub-matrix B is 2;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the column weight of each column in the submatrix D is 3, and the row weights are uniformly distributed;
the submatrix E is a lower triangular matrix, and the column weight of each column in the submatrix E is less than or equal to 4.
Optionally, m is greater than or equal to 5;
the row weight of each row in the submatrix A is 3, and the column weight of each column in the submatrix A is 3;
the row weight of each row in the sub-matrix B is 3, and the column weight of each column in the sub-matrix B is 3;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
Optionally, the row weight of each row in the submatrix D is 3, and the column weight of each column in the submatrix D is 3;
the submatrix E is a lower triangular matrix, and the column weight of each column is less than or equal to 4.
Optionally, M is an integer multiple of 22, and N is an integer multiple of 24.
In the embodiment of the present application, the transceivers of fig. 6 and 8 may be wired transceivers, wireless transceivers, or a combination thereof. The wired transceiver may be, for example, an ethernet interface. The ethernet interface may be an optical interface, an electrical interface, or a combination thereof. The wireless transceiver may be, for example, a wireless local area network transceiver, a cellular network transceiver, or a combination thereof. The processor may be a Central Processing Unit (CPU), a Network Processor (NP), or a combination of a CPU and an NP. The processor may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof.
A bus interface may also be included in fig. 6 and 8, and may include any number of interconnected buses and bridges, in particular, with one or more processors represented by a processor and various circuits of a memory represented by a memory linked together. The bus interface may also link together various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface. The transceiver provides a means for communicating with various other apparatus over a transmission medium. The processor is responsible for managing the bus architecture and the usual processing, and the memory may store data used by the processor in performing operations.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the scope of the application. Thus, to the extent that such modifications and variations of the present application fall within the scope of the claims of the present application, it is intended that the present application also encompass such modifications and variations.

Claims (14)

1. A method for transmitting a Low Density Parity Check (LDPC) code, comprising:
acquiring an LDPC code check matrix;
the LDPC code prototype graph corresponding to the LDPC code check matrix is a matrix with M rows and N columns, the LDPC code prototype graph comprises a first part, a second part, a third part and a fourth part which are sequentially arranged from left to right, and each part comprises at least one column of elements; the first part of the LDPC code prototype graph comprises a submatrix C, C, Z, Z, C, A, Z, Z, Z, Z, C, B, B, A, Z, Z, Z, Z, Z, Z, Z, Z, Z in sequence from the 1 st row; the second part of the LDPC code prototype graph comprises a submatrix D, Z, C, Z, Z, A, C, C, A, Z, Z, Z, Z, A, C, B, B, A, Z, Z, Z, Z, Z in sequence from the 1 st row; the third part of the LDPC code prototype graph comprises a submatrix E, Z, Z, C, Z, Z, Z, Z, A, C, Z, Z, Z, Z, Z, Z, Z, Z, A, C, B, B, A in sequence from the 1 st row; the fourth part of the LDPC code prototype graph sequentially comprises a submatrix O, I from the 1 st row; A. b, C, D, E and Z square matrix are M rows and M columns, Z square matrix is M rows and M columns of all-0 matrix, O is M rows and N-3M columns of all-0 matrix, I is M-M rows and N-3M columns of unit matrix;
and coding according to the LDPC code check matrix to obtain the LDPC code and sending the LDPC code.
2. The method of claim 1, wherein m is less than 5;
the row weight of each row in the submatrix A is 1, and the column weight of each column in the submatrix A is 1;
the row weight of each row in the sub-matrix B is 2, and the column weight of each column in the sub-matrix B is 2;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
3. The method according to claim 1 or 2,
the column weight of each column in the submatrix D is 3, and the row weights are uniformly distributed;
the submatrix E is a lower triangular matrix, and the column weight of each column in the submatrix E is less than or equal to 4.
4. The method of claim 1, wherein m is greater than or equal to 5;
the row weight of each row in the submatrix A is 3, and the column weight of each column in the submatrix A is 3;
the row weight of each row in the sub-matrix B is 3, and the column weight of each column in the sub-matrix B is 3;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
5. The method according to claim 1 or 4,
the row weight of each row in the submatrix D is 3, and the column weight of each column in the submatrix D is 3;
the submatrix E is a lower triangular matrix, and the column weight of each column is less than or equal to 4.
6. A method according to claim 1 or 2, wherein M is an integer multiple of 22 and N is an integer multiple of 24.
7. A low density parity check LDPC code receiving method, comprising:
receiving an LDPC code;
decoding the LDPC code according to the LDPC code check matrix;
the LDPC code prototype graph corresponding to the LDPC code check matrix is a matrix with M rows and N columns, the LDPC code prototype graph comprises a first part, a second part, a third part and a fourth part, and each part comprises at least one column of elements; the first part of the LDPC code prototype graph comprises a submatrix C, C, Z, Z, C, A, Z, Z, Z, Z, C, B, B, A, Z, Z, Z, Z, Z, Z, Z, Z, Z in sequence from the 1 st row; the second part of the LDPC code prototype graph comprises a submatrix D, Z, C, Z, Z, A, C, C, A, Z, Z, Z, Z, A, C, B, B, A, Z, Z, Z, Z, Z in sequence from the 1 st row; the third part of the LDPC code prototype graph comprises a submatrix E, Z, Z, C, Z, Z, Z, Z, A, C, Z, Z, Z, Z, Z, Z, Z, Z, A, C, B, B, A in sequence from the 1 st row; the fourth part of the LDPC code prototype graph sequentially comprises a submatrix O, I from the 1 st row; A. b, C, D, E and Z square matrix are M rows and M columns, Z square matrix is M rows and M columns of all-0 matrix, O is M rows and N-3M columns of all-0 matrix, and I is M-M rows and N-3M columns of unit matrix.
8. A low density parity check LDPC code transmission apparatus, comprising:
the processing unit is used for acquiring an LDPC code check matrix;
the LDPC code prototype graph corresponding to the LDPC code check matrix is a matrix with M rows and N columns, the LDPC code prototype graph comprises a first part, a second part, a third part and a fourth part which are sequentially arranged from left to right, and each part comprises at least one column of elements; the first part of the LDPC code prototype graph comprises a submatrix C, C, Z, Z, C, A, Z, Z, Z, Z, C, B, B, A, Z, Z, Z, Z, Z, Z, Z, Z, Z in sequence from the 1 st row; the second part of the LDPC code prototype graph comprises a submatrix D, Z, C, Z, Z, A, C, C, A, Z, Z, Z, Z, A, C, B, B, A, Z, Z, Z, Z, Z in sequence from the 1 st row; the third part of the LDPC code prototype graph comprises a submatrix E, Z, Z, C, Z, Z, Z, Z, A, C, Z, Z, Z, Z, Z, Z, Z, Z, A, C, B, B, A in sequence from the 1 st row; the fourth part of the LDPC code prototype graph sequentially comprises a submatrix O, I from the 1 st row; A. b, C, D, E and Z square matrix are M rows and M columns, Z square matrix is M rows and M columns of all-0 matrix, O is M rows and N-3M columns of all-0 matrix, I is M-M rows and N-3M columns of unit matrix;
the processing unit is used for coding according to the LDPC code check matrix to obtain an LDPC code;
and the transceiving unit is used for transmitting the LDPC code.
9. The apparatus of claim 8, wherein m is less than 5;
the row weight of each row in the submatrix A is 1, and the column weight of each column in the submatrix A is 1;
the row weight of each row in the sub-matrix B is 2, and the column weight of each column in the sub-matrix B is 2;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
10. The apparatus according to claim 8 or 9,
the column weight of each column in the submatrix D is 3, and the row weights are uniformly distributed;
the submatrix E is a lower triangular matrix, and the column weight of each column in the submatrix E is less than or equal to 4.
11. The apparatus of claim 8, wherein m is greater than or equal to 5;
the row weight of each row in the submatrix A is 3, and the column weight of each column in the submatrix A is 3;
the row weight of each row in the sub-matrix B is 3, and the column weight of each column in the sub-matrix B is 3;
the row weight of each row in the submatrix C is 3, and the column weight of each column is 3.
12. The apparatus according to claim 8 or 11,
the row weight of each row in the submatrix D is 3, and the column weight of each column in the submatrix D is 3;
the submatrix E is a lower triangular matrix, and the column weight of each column is less than or equal to 4.
13. The apparatus of claim 8 or 9, wherein M is an integer multiple of 22 and N is an integer multiple of 24.
14. A low density parity check LDPC code receiving apparatus, comprising:
a transceiving unit for receiving the LDPC code;
a processing unit, configured to decode an LDPC code according to an LDPC code check matrix;
the LDPC code prototype graph corresponding to the LDPC code check matrix is a matrix with M rows and N columns, the LDPC code prototype graph comprises a first part, a second part, a third part and a fourth part which are sequentially arranged from left to right, and each part comprises at least one column of elements; the first part of the LDPC code prototype graph comprises a submatrix C, C, Z, Z, C, A, Z, Z, Z, Z, C, B, B, A, Z, Z, Z, Z, Z, Z, Z, Z, Z in sequence from the 1 st row; the second part of the LDPC code prototype graph comprises a submatrix D, Z, C, Z, Z, A, C, C, A, Z, Z, Z, Z, A, C, B, B, A, Z, Z, Z, Z, Z in sequence from the 1 st row; the third part of the LDPC code prototype graph comprises a submatrix E, Z, Z, C, Z, Z, Z, Z, A, C, Z, Z, Z, Z, Z, Z, Z, Z, A, C, B, B, A in sequence from the 1 st row; the fourth part of the LDPC code prototype graph sequentially comprises a submatrix O, I from the 1 st row; A. b, C, D, E and Z square matrix are M rows and M columns, Z square matrix is M rows and M columns of all-0 matrix, O is M rows and N-3M columns of all-0 matrix, and I is M-M rows and N-3M columns of unit matrix.
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