CN108108130A - A kind of method and solid state disk for promoting solid state disk read-write performance - Google Patents
A kind of method and solid state disk for promoting solid state disk read-write performance Download PDFInfo
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- CN108108130A CN108108130A CN201711407387.2A CN201711407387A CN108108130A CN 108108130 A CN108108130 A CN 108108130A CN 201711407387 A CN201711407387 A CN 201711407387A CN 108108130 A CN108108130 A CN 108108130A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0674—Disk device
- G06F3/0676—Magnetic disk device
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Abstract
The invention discloses a kind of methods and solid state disk for promoting solid state disk read-write performance, it is characterized in that increase concatenation module in SSD controller and SSD caching management modules, continuous cache blocks are spliced into the data packet of 8K sizes in read command that the concatenation module issues host or the cache blocks of write order, and passing through the information of Packet Descriptor table description splicing, the information that the DMA of the SSD controller is described according to descriptor table controls the data transmission read or write.The number established generation data packet and transmit data, and then reduction time loss are reduced by increasing concatenation module, thus brings the performance for promoting read write command.
Description
Technical field
The present invention relates to solid state disk control technology, more particularly to a kind of method for promoting solid state disk read-write performance and solid
State hard disk.
Background technology
Controller design and firmware (FW) design of SATASSD needs to follow ata interface agreement, and ATA agreements regulation is primary
Data frame information structure (the Data FIS- of command queue NCQ (Native Command Queuing) read write command data transmission
Data Frame Information Structure, abbreviation data packet) also suggestion is 8KB to maximum, because establishing data every time
The transmission of bag needs to consume the regular hour, so the data packet that single command is formed is fewer, caused by establishing data packet transmission
Time loss is fewer.Optimal situation is that each data packet of order is 8KB, data packet of the finishing touch less than 8KB
Except.
Flash translation layer (FTL) FTL (Flash Translation Layer) uses 4KB in the firmware design of current SATA SSD
Mapping mechanism, natural caching management module is also the management and with chained list format management in units of 4KB, so comparison
Simple and practical, if Fig. 1 is conventional cache management schematic diagram, what is safeguarded on logic chained list is the index value of physical cache block, is delayed
It deposits Buffer management modules and plucks next index value from logic chain table header every time, calculate the corresponding 4KB physics of the index value
The address of cache blocks is to applicant, and after applicant is using complete give back, caching management module is inversely calculated according to caching block address
The index value is suspended to chained list afterbody by corresponding index value.Due to ordering the strategy to reorder in firmware design, apply at first
The cache blocks gone not necessarily preferentially transmit data with host, so also not ensuring that the cache blocks that priority requisition is gone out preferentially return
Return caching management module, i.e., it is continuous to be not necessarily physics for the adjacent corresponding physical block address of index value on last logic chained list
, see logic index and the correspondence of physical block in Fig. 1, there are staggered cases.
What the data packet (Data FIS) of read write command was encapsulated using 4KB as unit, if Fig. 2 is the number of conventional 4KB sizes
According to bag data flow graph, the firmware read write command of SSD distributes multiple cache blocks according to 4KB units, these cache blocks are physically not
It is certain continuous, there are fifo queue Data FIS FIFO, Data the FIS descriptor tables of a descriptor table in SSD controller
Have recorded the physical address section of cache blocks, SSD firmwares are the cache blocks physical address of read write command (data in order in order
Transmit in order) Data FIS FIFO are committed to, SSD controller takes out Data FIS from Data FIS FIFO successively
Then descriptor table parses the caching physical address section of Data FIS descriptions, then start the DMA (Direct of controller
Memory Access, a kind of data transfer mode) connection host caches and the caching of SSD carry out data transmission, transfer one
SSD controller further takes out next Data FIS descriptor tables after Data FIS, is again started up DMA and carries out data transmission.So
The Data FIS descriptor tables of one order cutting are more, and the overhead of SSD controller is also more, and performance is poorer.Existing skill
Each Data FIS describe one section of caching of 4KB in art, the last one Data FIS may be less than 4KB.
Since map unit and memory management unit are all 4KB, the number of order data transmission in current firmware strategy
It is also in units of 4KB according to bag, is so designed that fairly simple easy to maintain.But shortcoming is it is also obvious that the quantity of data packet increases
It is more, reduce the transmission rate of front end interface.
The content of the invention
For disadvantages described above, the present invention seeks to how reduce to establish time loss caused by data packet is transmitted.
The present invention proposes the method for promoting solid state disk read-write performance in order to solve problem above, it is characterised in that
SSD controller in SSD caching management modules with increasing concatenation module, the read command or write life that the concatenation module issues host
Continuous cache blocks are spliced into the data packet of 8K sizes in the cache blocks of order, and pass through the letter of Packet Descriptor table description splicing
Breath, the information that the DMA of the SSD controller is described according to descriptor table control the data transmission read or write.
The method of the promotion solid state disk read-write performance, it is characterised in that one is delayed on the concatenation module cache blocks
Information is deposited, including at least the block initial address start_addr of a upper cache blocks, block tail address end_addr and whether effectively
Indicate is_valid；The concatenation module caching receives a new cache blocks, by the block initial address start_ of new cache blocks
Addr judges whether continuously compared with the block tail address end_addr of a upper cache blocks, slow by upper one if continuous
Counterfoil and new cache blocks are spliced, and are spliced into the data packet of 8K sizes, and corresponding updated data package descriptor table data.
The method of the promotion solid state disk read-write performance, it is characterised in that the concatenation module at least safeguards following letter
Breath：Block initial address start_addr, the block tail address end_addr of cache blocks and whether effective marker is_valid；It is submitted to
The caching block address of data packet queue is first fed into the concatenation module, judges whether is_valid has been set to, if do not had
It has been put that, put is_valid, juxtaposition start_addr is the initial address of new cache blocks, and it is new cache blocks to put end_addr
End address simultaneously terminates this splicing；Judge whether end_addr is equal to rising for new cache blocks if is_valid has been put
Beginning address, it is discontinuous if the caching for illustrating to cache before concatenation module not equal to and if newcomer's cache blocks, delaying before
The caching deposited forms the data packet queue that Packet Descriptor table brushes SSD controller, then new cache blocks are cached,
The initial address that start_addr is new cache blocks is put, put end_addr as the end address of new cache blocks and terminates flow；
New cache blocks with the caching cached before are stitched together if the initial address that end_addr is equal to new cache blocks, that is, are put
End_addr is the end address of new cache blocks；Terminate this splicing if spliced caching is not above 8KB, otherwise cut
8KB formation Data FIS descriptor tables are cut out to brush the data packet queue of SSD controller and record remaining cache；If new caching
Block is not that the final stage caching of order then terminates to splice, and remaining caching in concatenation module otherwise is formed Packet Descriptor
Table brushes the data packet queue of SSD controller, removes is_valid and indicates and terminate to splice.
The method of the promotion solid state disk read-write performance, it is characterised in that SSD resets cache management mould during idle time
Block resets caching management module and arranges the corresponding physical cache of the index value of cache blocks adjacent in logic chained list for sequential like
State.
A kind of solid state disk, it is characterised in that increase concatenation module in SSD controller and SSD caching management modules, institute
State the data that continuous cache blocks in the cache blocks of read command that concatenation module issues host or write order are spliced into 8K sizes
Bag, and pass through the information of Packet Descriptor table description splicing, the letter that the DMA of the SSD controller is described according to descriptor table
The data transmission that breath control reads or writes.
The solid state disk, it is characterised in that a cache information on the concatenation module cache blocks, including at least upper
Block initial address start_addr, the block tail address end_addr of one cache blocks and whether effective marker is_valid；It is described
Concatenation module caching receives a new cache blocks, by the block initial address start_addr of new cache blocks and a upper cache blocks
Block tail address end_addr be compared judge whether it is continuous, will a upper cache blocks and the progress of new cache blocks if continuous
Splicing is spliced into the data packet of 8K sizes, and corresponding updated data package descriptor table data.
The solid state disk, it is characterised in that the concatenation module at least safeguards following information：The block starting point of cache blocks
Location start_addr, block tail address end_addr and whether effective marker is_valid；It is submitted to the cache blocks of data packet queue
Address is first fed into the concatenation module, judges whether is_valid has been set to, and is_valid has been put if not put,
Juxtaposition start_addr is the initial address of new cache blocks, puts end_addr as the end address of new cache blocks and terminates this spelling
It connects；Judge whether end_addr is equal to the initial address of new cache blocks if is_valid has been put, if not equal to if
The caching cached before illustrating concatenation module and new cache blocks are discontinuous, then the caching cached before are formed data packet and retouched
The data packet queue that symbol table brushes SSD controller is stated, then new cache blocks are cached, that is, puts start_addr and delays to be new
The initial address of counterfoil puts end_addr as the end address of new cache blocks and terminates flow；If end_addr is equal to new slow
New cache blocks are then stitched together by the initial address of counterfoil with the caching cached before, that is, put the end that end_addr is new cache blocks
Tail address；Terminate this splicing if spliced caching is not above 8KB, be otherwise cut into 8KB formation Data FIS and retouch
Symbol table is stated to brush the data packet queue of SSD controller and record remaining cache；If new cache blocks are not the final stages of order
Caching then terminates to splice, and remaining caching in concatenation module otherwise is formed the number that Packet Descriptor table brushes SSD controller
According to bag queue, remove is_valid and indicate and terminate to splice.
The solid state disk, it is characterised in that SSD resets caching management module during idle time, resets caching management module
The corresponding physical cache of the index value of cache blocks adjacent in logic chained list is arranged as continuous state.
The beneficial effects of the invention are as follows：The number established generation data packet and transmit data is reduced by increasing concatenation module,
And then time loss is reduced, thus bring the performance for promoting read write command.
Description of the drawings
Fig. 1 is conventional cache management schematic diagram；
Fig. 2 is the packet data flow graph of conventional 4KB sizes；
Fig. 3 is data packet splicing flow chart；
Fig. 4 is the data splicing data flow diagram in units of 8K.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without creative efforts
Embodiment belongs to the scope of protection of the invention.
The defects of being designed for current firmware proposes a kind of method for splicing 8KB Data FIS, is specially：Increase in firmware
Add a concatenation module Splice Module, be committed to the caching caching of the data packet queue Data FIS FIFO of read write command
Block address section is first fed into concatenation module, is decided whether to form Data FIS descriptor tables, such as Fig. 4, the module by concatenation module
At least maintain following field：
1.start_addr：The cache blocks initial address of caching.
2.end_addr：The cache blocks end address of caching.
3.is_valid：Indicate whether valid cache.
Process flow after the new cache blocks of concatenation module acquisition is as follows：Judge whether is_valid has put, if do not put
It rises and has then put is_valid, juxtaposition start_addr is the initial address of new cache blocks, puts the end that end_addr is new cache blocks
Simultaneously terminate flow in tail address；Judge whether end_addr is equal to the starting point of new cache blocks if is_valid has been put
Location, the caching cached before concatenation module is illustrated not equal to and if new cache blocks are discontinuous, what is cached before
Caching forms the Data FISFIFO that Data FIS descriptor tables brush SSD controller, then new cache blocks are cached,
The initial address that start_addr is new cache blocks is put, put end_addr as the end address of new cache blocks and terminates flow；
New cache blocks with the caching cached before are stitched together if the initial address that end_addr is equal to new cache blocks, that is, are put
End_addr is the end address of new cache blocks；Terminate flow if spliced caching is not above 8KB, be otherwise cut into
8KB forms Data FIS descriptor tables and brushes the Data FIS FIFO of SSD controller and record remaining cache, i.e. start_
Addr increases 8KB；Terminate flow if new cache blocks are not the final stage cachings of order, it otherwise will be remaining in concatenation module
Caching form the Data FIS FIFO that Data FIS descriptor tables brush SSD controller, remove is_valid and indicate and terminate
Flow.Flow chart is shown in Fig. 3.
By taking the example in Fig. 2 as an example, one is ordered the caching for being assigned with six pieces of 4KB, wherein first piece and second piece does not connect
Continuous, second piece and the 3rd piece continuous, and the 3rd piece and the 4th piece discontinuous, and the four, the 5th, the 6th pieces are continuous, they are being spelled
Processing in connection module is as follows：
Step1：First piece of caching finds that is_valid is invalid, then sets start_addr, end_ into concatenation module
Addr is the whole story address of first piece of caching, and it is effective to put is_valid.
Step2：Second piece of caching finds that is_valid is effective, and end_addr is not equal to second piece into concatenation module
The initial address of caching, then first piece of formation Data FIS descriptor table, then put start_addr, end_addr the
The whole story address of two pieces of cachings.
Step3：3rd piece of caching finds that is_valid is effective, and end_addr is equal to the 3rd piece and delays into concatenation module
The initial address deposited then merges the two or three piece of caching, that is, puts end_addr and be the end address of the 3rd piece of caching, and delay at this time
The caching deposited has expired 8KB, then preceding 8KB is formed Data FIS brushes away, and then remaining cache is 0, then it is invalid to put is_valid.
Step4：4th piece of caching finds that is_valid is invalid, then sets start_addr, end_ into concatenation module
Addr is the whole story address of the 4th piece of caching, and it is effective to put is_valid.
Step5：5th piece of caching finds that is_valid is effective, and end_addr is equal to the 5th piece and delays into concatenation module
The initial address deposited then merges the four or five piece of caching, that is, puts end_addr and be the end address of the 5th piece of caching, and delay at this time
The caching deposited has expired 8KB, then preceding 8KB is formed Data FIS brushes away, and then remaining cache is 0, then it is invalid to put is_valid.
Step6：6th piece of caching finds that is_valid is invalid, then sets start_addr, end_ into concatenation module
Addr be the 6th piece caching whole story address, it be effective to put is_valid, and this for order finishing touch cache, then force by
Caching in caching all forms Data FIS and brushes away.
After increasing concatenation module, the Data FIS FIFO eventually formed are shown in Fig. 4, form 2 less compared with prior art
Data FIS, improve performance to a certain extent.
In addition, the effect of the technology depends on the corresponding object of caching index value adjacent on caching management module logic chained list
Whether reason caching is continuous, if being all continuous, then and the probability that concatenation module is combined into 8KB can reach absolutely, so
In order to which new technology is enable to play maximum effect, SSD needs (inside does not handle host request) replacement (Reset) during the free time slow
Management module is deposited, the corresponding physical cache of caching index value adjacent on logic chained list is all in the caching management module after replacement
Continuously.
The above disclosed interest field for being only an embodiment of the present invention, sheet cannot being limited with this certainly,
One of ordinary skill in the art will appreciate that realize all or part of flow of above-described embodiment, and according to the claims in the present invention institute
The equivalent variations of work still fall within the scope that the present invention is covered.
Claims (8)
- A kind of 1. method for promoting solid state disk read-write performance, it is characterised in that in SSD controller and SSD caching management modules Increase concatenation module, continuous cache blocks splicing in read command that the concatenation module issues host or the cache blocks of write order For the data packet of 8K sizes, and pass through the information of Packet Descriptor table description splicing, the DMA of the SSD controller is according to retouching State the data transmission that the information control of symbol table description reads or writes.
- 2. the method according to claim 1 for promoting solid state disk read-write performance, it is characterised in that the concatenation module is delayed A cache information on counterfoil, block initial address start_addr, block tail address end_ including at least a upper cache blocks Addr and whether effective marker is_valid；The concatenation module caching receives a new cache blocks, by the block of new cache blocks Initial address start_addr judges whether continuously compared with the block tail address end_addr of a upper cache blocks, if even It is continuous then splice a upper cache blocks and new cache blocks, the data packet of 8K sizes is spliced into, and corresponding updated data package is retouched State symbol table data.
- 3. the method according to claim 1 for promoting solid state disk read-write performance, it is characterised in that the concatenation module is extremely Following information is safeguarded less：Block initial address start_addr, the block tail address end_addr of cache blocks and whether effective marker is_ valid；The caching block address for being submitted to data packet queue is first fed into the concatenation module, judges whether is_valid is set to It rises, is_valid has been put if not put, juxtaposition start_addr is the initial address of new cache blocks, and putting end_addr is The end address of new cache blocks simultaneously terminates this splicing；It is new to judge whether end_addr is equal to if is_valid has been put The initial address of cache blocks, the cache blocks cached before concatenation module is illustrated not equal to if do not connect with new cache blocks It is continuous, then the caching cached before is formed the data packet queue that Packet Descriptor table brushes SSD controller, then delayed new Counterfoil caches, that is, puts the initial address that start_addr is new cache blocks, with putting the end that end_addr is new cache blocks Simultaneously terminate flow in location；New cache blocks are spelled with the caching cached before if the initial address that end_addr is equal to new cache blocks It picks up and, that is, put the end address that end_addr is new cache blocks；Terminate this if spliced caching is not above 8KB Otherwise splicing is cut into 8KB formation DataFIS descriptor tables and brushes the data packet queue of SSD controller and record remaining cache； Terminate to splice if new cache blocks are not the final stage cachings of order, remaining caching in concatenation module is otherwise formed into number The data packet queue of SSD controller is brushed according to bag descriptor table, is_valid is removed and indicates and terminate to splice.
- 4. the method according to claim 1 for promoting solid state disk read-write performance, it is characterised in that SSD is reset during idle time Caching management module resets caching management module the corresponding physical cache of the index value of cache blocks adjacent in logic chained list is whole It manages as continuous state.
- 5. a kind of solid state disk, it is characterised in that increase concatenation module in SSD controller and SSD caching management modules, it is described Continuous cache blocks are spliced into the data packet of 8K sizes in read command that concatenation module issues host or the cache blocks of write order, And pass through the information of Packet Descriptor table description splicing, the information control that the DMA of the SSD controller is described according to descriptor table Make the data transmission read or write.
- 6. solid state disk according to claim 5, it is characterised in that a cache information on the concatenation module cache blocks, Including at least the block initial address start_addr of a upper cache blocks, block tail address end_addr and whether effective marker is_ valid；Concatenation module caching receives a new cache blocks, by the block initial address start_addr of new cache blocks with it is upper The block tail address end_addr of one cache blocks, which is compared, to be judged whether continuously, by a upper cache blocks and newly if continuous Cache blocks are spliced, and are spliced into the data packet of 8K sizes, and corresponding updated data package descriptor table data.
- 7. solid state disk according to claim 5, it is characterised in that the concatenation module at least safeguards following information：Block initial address start_addr, the block tail address end_addr of cache blocks and whether effective marker is_valid；It submits Caching block address to data packet queue is first fed into the concatenation module, judges whether is_valid has been set to, if do not had It has been put that, put is_valid, juxtaposition start_addr is the initial address of new cache blocks, puts end_addr as new cache blocks End address and terminate this splicing；Judge whether end_addr is equal to the initial address of new cache blocks if is_valid has been put, if not equal to if The caching cached before illustrating concatenation module and new cache blocks are discontinuous, then the caching cached before are formed data packet and retouched The data packet queue that symbol table brushes SSD controller is stated, then new cache blocks are cached, that is, puts start_addr and delays to be new The initial address of counterfoil puts end_addr as the end address of new cache blocks and terminates flow；If end_addr is equal to new slow New cache blocks are then stitched together by the initial address of counterfoil with the caching cached before, that is, put the end that end_addr is new cache blocks Tail address；Terminate this splicing if spliced caching is not above 8KB, be otherwise cut into 8KB and form DataFIS descriptions Symbol table brushes the data packet queue of SSD controller and records remaining cache；If the final stage that new cache blocks are not orders delays It deposits, terminates to splice, remaining caching in concatenation module is otherwise formed into the data that Packet Descriptor table brushes SSD controller Bag queue removes is_valid and indicates and terminate to splice.
- 8. solid state disk according to claim 1, it is characterised in that SSD resets caching management module during idle time, resets Caching management module arranges the corresponding physical cache of the index value of cache blocks adjacent in logic chained list for continuous state.
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| CN113076062A (en) * | 2021-03-30 | 2021-07-06 | 山东英信计算机技术有限公司 | Method and equipment for prolonging service life of QLCSSD |
| CN113609041A (en) * | 2021-06-20 | 2021-11-05 | 山东云海国创云计算装备产业创新中心有限公司 | Data transmission method and system |
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