CN108107962B

CN108107962B - Image control circuit

Info

Publication number: CN108107962B
Application number: CN201711434182.3A
Authority: CN
Inventors: 杨柳; 马新闻
Original assignee: Beijing Zhaoxin Electronic Technology Co ltd
Current assignee: Beijing Zhaoxin Electronic Technology Co ltd
Priority date: 2017-12-26
Filing date: 2017-12-26
Publication date: 2020-09-15
Anticipated expiration: 2037-12-26
Also published as: CN108107962A

Abstract

An image control circuit comprises a current generating circuit, a voltage generating circuit, an image generating circuit, a detecting circuit and a logic circuit. The current generation circuit generates a reference current according to a selection signal. The voltage generating circuit generates a reference voltage according to the selection signal. The image generating circuit is coupled to a resistor and generates an image current according to the reference current. The detection circuit detects the voltage of the resistor and compares the voltage of the resistor with a reference voltage to generate a detection signal. The logic circuit enables or disables the selection signal according to the detection signal. When the voltage of the resistor is less than the reference voltage, the logic circuit disables the selection signal. When the selection signal is disabled, the current generation circuit increases the reference current and the voltage generation circuit increases the reference voltage.

Description

Image control circuit

Technical Field

The present invention relates to an image control circuit, and more particularly to an image control circuit for providing an analog signal to a screen.

Background

A typical Video digital-to-analog converter (Video DAC) needs to check whether a screen or other display device is connected. The conventional control method provides a normal operating voltage to the video DAC. When the video digital-to-analog converter enters the working state, whether the screen is connected to the converter or not is detected. If the screen exists, the video digital-to-analog converter enters a normal working state. If the screen does not exist, the video digital-to-analog converter finishes working and restarts after a fixed time. However, the video dac has a large power loss during the startup process.

Disclosure of Invention

The invention provides an image control circuit, which comprises a current generating circuit, a voltage generating circuit, a first image generating circuit, a detecting circuit and a logic circuit. The current generation circuit generates a reference current according to a selection signal. The voltage generating circuit generates a reference voltage according to the selection signal. The first image generating circuit is coupled to a first resistor and generates a first image current according to the reference current. The detection circuit detects the voltage of the first resistor and compares the voltage of the first resistor with a reference voltage to generate a detection signal. The logic circuit enables or disables the selection signal according to the detection signal. When the voltage of the first resistor is smaller than the reference voltage, the logic circuit disables the selection signal. When the selection signal is disabled, the current generation circuit increases the reference current and the voltage generation circuit increases the reference voltage.

Drawings

FIG. 1 is a diagram of an image control circuit according to the present invention.

FIG. 2 is another schematic diagram of the image control circuit according to the present invention.

FIG. 3 is a diagram of an image generating circuit according to an embodiment of the present invention.

FIG. 4 is a diagram of an image generating circuit according to an embodiment of the present invention.

FIG. 5 is a diagram of an image generating circuit according to an embodiment of the present invention.

FIG. 6 is a diagram of an embodiment of a current generation circuit.

FIG. 7 is a diagram of a voltage generating circuit according to an embodiment of the present invention.

FIG. 8 is a timing control diagram of the image control circuit according to the present invention.

FIG. 9 is another timing control diagram of the image control circuit according to the present invention.

Detailed Description

In order to make the objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. The present description provides various examples to illustrate the technical features of various embodiments of the present invention. The arrangement of the components in the embodiments is for illustration and not for limiting the invention. In addition, the reference numerals in the embodiments are partially repeated to simplify the description, and do not indicate the relationship between the different embodiments.

FIG. 1 is a diagram of an image control circuit according to the present invention. As shown, the image control circuit 100 generates image currents IR, IG, IB. The screen 150 displays a picture according to the image currents IR, IG, IB. In one embodiment, the image currents IR, IG, IB are used to adjust the values of the three primary colors of the screen 150, i.e., red, green, and blue, so as to adjust the chromaticity, saturation, and brightness of the image displayed on the screen 150. In other embodiments, the Video control circuit 100 is integrated in a Video Graphics Array (VGA) system and functions as a Video digital-to-analog converter (Video DAC). In this example, the image control circuit 100 provides an analog signal to the screen 150.

In the present embodiment, the image control circuit 100 includes a current generating circuit 105, a voltage generating circuit 110,

image generating circuits

115, 120, 125, detecting

circuits

130, 135, 140, and a logic circuit 145. The current generating circuit 105 generates a reference current BIAS according to a selection signal SENSEL. In one embodiment, the current generation circuit 105 converts a reference voltage VBG1 according to the selection signal SENSEL to generate the reference current BIAS. The present invention does not limit the circuit architecture of the current generating circuit 105. As the current generation circuit 105, any circuit capable of generating a current may be used.

The voltage generating circuit 110 generates a reference voltage VREF according to the selection signal SENSEL. In one embodiment, the voltage generating circuit 110 converts a reference voltage VBG2 according to the selection signal SENSEL to generate the reference voltage VREF. The present invention is not limited to the circuit architecture of the voltage generating circuit 110. Any circuit capable of generating a voltage may be used as the voltage generation circuit 110.

The image generating circuit 115 is coupled to a first resistor (not shown), and generates the image current IR according to the reference current BIAS. In the present embodiment, the image generating circuit 115 adjusts the image current IR according to a control signal SCR. The image generating circuit 120 is coupled to a second resistor (not shown), and generates an image current IG according to the reference current BIAS. In the present embodiment, the image generating circuit 120 adjusts the image current IG according to a control signal SCG. The image generating circuit 125 is coupled to a third resistor (not shown), and generates an image current IB according to the reference current BIAS. In the present embodiment, the image generating circuit 125 adjusts the image current IB according to a control signal SCB.

The detection circuit 130 detects the voltage of the first resistor and compares the voltage of the first resistor with the reference voltage VREF to generate a detection signal SENSE _ R. In this embodiment, when the screen 150 is coupled to the image control circuit 100, the current flowing through the first resistor is reduced, so that the voltage of the first resistor is reduced, and therefore, by detecting the voltage of the first resistor, it can be determined whether the screen 150 is coupled to the image control circuit 100.

The detection circuit 135 detects the voltage of the second resistor and compares the voltage of the second resistor with the reference voltage VREF to generate a detection signal SENSE _ G. The detection circuit 140 detects the voltage of the third resistor and compares the voltage of the third resistor with the reference voltage VREF to generate a detection signal SENSE _ B. The detection signals SENSE _ R, SENSE _ G and SENSE _ B are used for determining whether the screen 150 is coupled to the image control circuit 100, and for determining whether there is a failure in the circuits on the screen 150 corresponding to the detection signals when the screen 150 is coupled to the image control circuit 100, and in the lines/pins/interfaces connecting the image control circuit 100 and the screen 150.

The logic circuit 145 enables or disables the selection signal SENSEL according to the detection signals SENSE _ R, SENSE _ G and SENSE _ B. For example, when the voltage of the first resistor is less than the reference voltage VREF, the logic circuit 145 disables the selection signal SENSEL. When the selection signal SENSEL is disabled, the current generation circuit 105 increases the reference current BIAS and the voltage generation circuit 110 increases the reference voltage VREF.

In one embodiment, logic 145 enables select signal SENSEL during an initialization period. At this time, the reference current BIAS output by the current generation circuit 105 has a first level and the reference voltage VREF output by the voltage generation circuit 110 has a third level. However, when the screen 150 is coupled to the image control circuit 100, the voltage of the first resistor is less than the reference voltage VREF. Therefore, the logic circuit 145 disables the selection signal SENSEL. When the selection signal SENSEL is disabled, the reference current BIAS output by the current generation circuit 105 has a second level and the reference voltage VREF output by the voltage generation circuit 110 has a fourth level. According to an embodiment of the present invention, the first level may be half of the second level, or other values smaller than the second level; the third level may be half of the fourth level or some other value less than the fourth comment. Since the current generation circuit 105 and the voltage generation circuit 110 properly adjust the levels of the reference current BIAS and the reference voltage VREF according to the selection signal SENSEL, the power consumption of the current generation circuit 105 and the voltage generation circuit 110 can be reduced, and since the reference current BIAS output from the current generation circuit 105 to the image generation circuit 115, the image generation circuit 120, and the image generation circuit 125 is adjusted, the power consumption of the image generation circuit 115, the image generation circuit 120, and the image generation circuit 125 is also reduced accordingly.

In other embodiments, logic circuit 145 may generate select signal SENSEL based on a single SENSE signal that is asserted, since one or both of SENSE signals SENSE _ R, SENSE _ G and SENSE _ B may not be asserted due to a failure of screen 150 or the lines/pins/interfaces connecting image control circuit 100 and screen 150. In addition, in the present embodiment, the logic circuit 145 further generates control signals SCR, SCG, and SCB for controlling the

image generating circuits

115, 120, and 125. The

image generation circuits

115, 120, and 125 adjust the image currents IR, IG, and IB according to the control signals SCR, SCG, and SCB, respectively.

In one embodiment, during an initialization period, the logic circuit 145 does not output the selection signal SENSEL, and directly generates a control signal PDDAC for activating the current generation circuit 105 and the voltage generation circuit 110 simultaneously. In this case, after the current generating circuit 105 generates the reference current BIAS and the voltage generating circuit 110 generates the reference voltage VREF, the logic circuit 145 generates a control signal PDSENSE to the detecting

circuits

130, 135 and 140. The

detection circuits

130, 135 and 140 detect the voltages of the first, second and third resistors according to the control signal PDSSENSE.

FIG. 2 is another possible schematic diagram of the image control circuit according to the present invention. Fig. 2 is similar to fig. 1, except that the image control circuit 200 further includes a voltage generating circuit 205 and a switch module 210. The voltage generation circuit 205 generates the reference voltages VBG1 and VBG2 according to the control signal PDDAC. The reference voltage VBG1 may be the same or different from the reference voltage VBG 2. When the voltage generation circuit 205 outputs only one reference voltage, the reference voltage VBG1 is the same as the reference voltage VBG 2; when the voltage generation circuit 205 outputs a plurality of reference voltages, the reference voltage VBG1 may be different from the reference voltage VBG2

The switch module 210 includes

switches

215, 220, and 225. The switch 215 is coupled between the current generating circuit 105 and the image generating circuit 115, and transmits the reference current BIAS to the image generating circuit 115 according to the control signal PDR. The switch 220 is coupled between the current generating circuit 105 and the image generating circuit 120, and transmits the reference current BIAS to the image generating circuit 120 according to the control signal PDG. The switch 225 is coupled between the current generating circuit 105 and the image generating circuit 125, and transmits the reference current BIAS to the image generating circuit 125 according to the control signal PDB.

In the present embodiment, the logic circuit 145 first activates the current generating circuit 105, the voltage generating circuit 110 and the voltage generating circuit 205, and then turns on the

switches

215, 220 and 225. The present invention does not limit the starting sequence of the current generation circuit 105, the voltage generation circuit 110, and the voltage generation circuit 205, nor the turn-on sequence of the

switches

215, 220, and 225. In one embodiment, the logic 145 turns on the

switches

215, 220, and 225 simultaneously. In another embodiment, the logic 145 turns on the

switches

215, 220, and 225 one by one. The logic 145 determines whether the screen 150 is coupled to the image control circuit 200 according to the detection signals SENSE _ R, SENSE _ G and SENSE _ B. When the screen 150 is not coupled to the image control circuit 200, the logic circuit 145 turns off the

switches

225, 220, and 215 one by one when none of the detection signals SENSE _ R, SENSE _ G and SENSE _ B is enabled, so as to reduce the influence on the power supply and other circuits. In other embodiments, the logic 145 simultaneously opens the

switches

215, 220, and 225. When the screen 150 is coupled to the video control circuit 200, at least one of the SENSE signals SENSE _ R, SENSE _ G and SENSE _ B is enabled, which indicates that there may be a fault in the circuit on the screen 150 corresponding to the disabled one of the SENSE signals SENSE _ R, SENSE _ G and SENSE _ B, or in the lines/pins/interfaces correspondingly connecting the video control circuit 200 and the screen 150.

Fig. 3 is a diagram of an embodiment of the image generating circuit 115 according to the present invention. As shown, the image generating circuit 115 includes unit circuits UA 1-UAN and a first resistor 305. Since the circuit architectures of the cell circuits UA1 to UAN are the same, only the cell circuit UA1 is taken as an example below. As shown, the unit circuit UA1 includes a transistor QA1, switches SWA1 and SWA 2. The gate of the transistor QA1 receives the reference current BIAS, and the source thereof receives an operating voltage VPP. In the present embodiment, the transistor QA1 is used as a current source to generate a current IA1 according to the reference current BIAS.

The switch SWA1 is coupled between the drain of the transistor QA1 and a ground node GND. The switch SWA2 is coupled between the drain of the transistor QA1 and the first resistor 305. When switch SWA1 is turned on, switch SWA2 is turned off. Therefore, the image current IA1 flows into the ground node GND. When switch SWA2 is turned on, switch SWA1 is turned off.

Therefore, the image current IR is the sum of the currents IA1 through IAN output from the unit circuits UA1 through UAN, and the magnitude of the image current IR can be adjusted by the control switches SWA1 through SWAP. Specifically, taking the switches (such as SWA2, SWA4, SWAN) coupled to the first resistor 305 as an example, when the switches SWA2 and SWA4 are turned on, the image current IR is equal to the sum of the currents IA1 and IA 2. When the switches SWA2, SWA4, and SWAP are turned on, the image current IR is equal to the sum of the currents IA1, IA2, and IAN. In one embodiment, switches SWA 1-SWAP are controlled by logic 145. The logic circuit 145 sends a control signal SCR to control at least one of the switches SWA 1-SWAP. The number of unit circuits is not limited in the present invention. In other embodiments, the image generation circuit 115 has only a single unit circuit.

In an embodiment, when the screen 150 is not coupled to the image control circuit 200, the voltage across the first resistor 305 is equal to a predetermined value. When the screen 150 is coupled to the image control circuit 200, the voltage of the first resistor 305 is less than or equal to the predetermined value because the equivalent resistor 310 of the screen 150 is connected in parallel with the first resistor 305. Therefore, by detecting the voltage at the upper end of the first resistor 305, it is known whether the screen 150 exists. In this embodiment, the first resistor 305 is integrated in the image generating circuit 115, but is not limited to the invention. In other embodiments, the first resistor 305 is disposed outside the image generating circuit 115. In this case, the first resistor 305 may also be integrated into the detection circuit 130.

Fig. 4 is a diagram of an embodiment of an image generating circuit 120 according to the present invention. As shown, the image generating circuit 120 includes unit circuits UB 1-UBN and a second resistor 420. Since the circuit architectures of the cell circuits UB1 to UB UBN are the same, only the cell circuit UB1 will be described below. As shown, the unit circuit UB1 includes a transistor QB1 and switches SWB1 and SWB 2. Transistor QB1 has a gate receiving reference current BIAS and a source receiving operating voltage VPP. In the present embodiment, the transistor QB1 serves as a current source for generating the current IB1 according to the reference current BIAS.

The switch SWB1 is coupled between the drain of the transistor QB1 and the ground node GND. The switch SWB2 is coupled between the drain of the transistor QB1 and the second resistor 420. In the embodiment, the second resistor 420 is integrated in the image generating circuit 120, but the invention is not limited thereto. In other embodiments, the second resistor 420 is disposed outside the image generating circuit 120. When switch SWB1 is turned on, switch SWB2 is turned off. Therefore, the current IB1 flows into the ground node GND. When switch SWB2 is turned on, switch SWB1 is turned off.

Therefore, the image current IG is the sum of the currents IB1 to IBN output from the unit circuits UB1 to UBN, and the magnitude of the image current IG can be adjusted by the control switches SWB1 to SWBP. Specifically, taking the switches (e.g., SWB2, SWB4, SWBN) coupled to the second resistor 420 as an example, when only the switch SWB2 is turned on, the image current IG is equal to the current IB 1. When the switches SWB2 and SWB4 are turned on, the image current IG is equal to the sum of the currents IB1 and IB 2. When the switches SWB2, SWB4, and SWBN are turned on, the image current IG is equal to the sum of the currents IB1, IB2, and IBN. In one embodiment, the logic circuit 145 turns on or off a switch in the image generating circuit 120 via the control signal SCG to adjust the image current IG.

When the screen 150 is not coupled to the image control circuit 200, the voltage of the second resistor 420 is equal to a predetermined value. When the screen 150 is coupled to the image control circuit 200, the resistor 310 is connected in parallel with the second resistor 420, so that the voltage of the second resistor 420 is decreased to be less than the predetermined value.

Fig. 5 is a diagram of an embodiment of the image generating circuit 125 according to the present invention. As shown, the image generating circuit 125 includes unit circuits UC 1-UCN and a third resistor 520. Since the circuit architectures of the unit circuits UC 1-UCN are the same, only the unit circuit UC1 will be described below. As shown, the unit circuit UC1 includes a transistor QC1 and switches SWC1 and SWC 2. Transistor QC1 has a gate receiving reference current BIAS and a source receiving operating voltage VPP. In the present embodiment, the transistor QC1 acts as a current source, which generates the current IC1 according to the reference current BIAS.

The switch SWC1 is coupled between the drain of the transistor QC1 and the ground node GND. The switch SWC2 is coupled between the drain of the transistor QC1 and the third resistor 520. In the embodiment, the third resistor 520 is integrated in the image generating circuit 125, but the invention is not limited thereto. In other embodiments, the third resistor 520 is disposed outside the image generating circuit 125. When switch SWC1 is turned on, switch SWC2 is turned off. Therefore, the current IC1 flows into the ground node GND. When switch SWC2 is turned on, switch SWC1 is turned off.

Therefore, the image current IG is the sum of the currents IC 1-ICN outputted by the unit circuits UC 1-UCN, and the magnitude of the image current IB can be adjusted by the control switches SWC 1-SWCP. Specifically, taking the switches (e.g., SWC2, SWC4, SWCN) coupled to the third resistor 520 as an example, when only the switch SWC2 is turned on, the image current IB is equal to the current IC 1. When the switches SWC2 and SWC4 are turned on, the image current IB is equal to the sum of the currents IC1 and IC 2. In one embodiment, the logic circuit 145 turns on or off a switch in the image generating circuit 125 via the control signal SCB to adjust the image current IB.

When the screen 150 is not coupled to the image control circuit 200, the voltage of the third resistor 520 is equal to a predetermined value. When the screen 150 is coupled to the image control circuit 200, the resistor 310 is connected in parallel to the third resistor 520, so that the voltage of the third resistor 520 is decreased to be less than the predetermined value.

Fig. 6 shows an embodiment of the current generation circuit 105. In the present embodiment, the current generating circuit 105 includes an operational amplifier 605,

transistors

610, 615, a switch 620 and a resistor 625. The inverting input of the operational amplifier 605 receives the reference voltage VBG 1. The transistor 610 has a gate coupled to the output terminal of the operational amplifier 605, a source receiving an operating voltage VPP, and a drain coupled to the non-inverting input terminal of the operational amplifier 605. The transistor 615 has a source receiving the operating voltage VPP and a drain coupled to the non-inverting input of the operational amplifier 605. The switch 620 is coupled between the gates of the

transistors

610 and 615. The resistor 625 is coupled between the drain of the transistor 610 and the ground node GND. When the output of the operational amplifier 605 increases, the current flowing through the transistor 610 becomes smaller, and therefore, the voltage difference of the resistor 625 becomes smaller, so that a smaller reference current BIAS can be generated at the gate of the transistor 610.

In the present embodiment, when the screen 150 is not coupled to the image control circuit 200, the logic circuit 145 enables the selection signal SENSEL to turn on the switch 620. Thereby causing the reference current BIAS to have a first level. When the screen 150 is coupled to the image control circuit 200, the logic circuit 145 disables the selection signal SENSEL to turn off the switch 620. Thereby causing the reference current BIAS to have a second level. In this example, if the

transistors

610 and 615 are configured identically, the first level is half of the second level, and if the

transistors

610 and 615 are configured differently, the first level is less than the second level, and the first level and the second level exhibit other proportional relationships.

The function of the selection signal SENSEL is illustrated in fig. 6, but the number of the transistors is not limited, and according to another embodiment of the present invention, the current generation circuit may include a plurality of parallel transistors, such as the

transistors

610 and 615, and the selection signal SENSEL acts on the switch between the transistors, such as 620, to specifically control the magnitude of the reference current BIAS output from the gate of one of the transistors, such as the transistor 610.

Fig. 7 is a diagram of an embodiment of the voltage generating circuit 110. As shown, the voltage generation circuit 110 includes an operational amplifier 705, a transistor 710, a resistor string 715, and a selector 740. The inverting input of the operational amplifier 705 receives a reference voltage VBG 2. The transistor 710 has a gate coupled to the output terminal of the operational amplifier 705, a source receiving the operating voltage VPP, and a drain coupled to the non-inverting input terminal of the operational amplifier 705. The resistor string 715 is coupled between the drain of the transistor 710 and the ground node GND for generating a plurality of divided voltages DV 1-DV 3. In the embodiment, the resistor string 715 includes

resistors

720, 725, 730, and 735, but the invention is not limited thereto. In other embodiments, the resistor string 715 has more or less resistors.

The selector 740 selects one of the divided voltages DV 1-DV 3 as the reference voltage VREF according to the selection signal SENSEL. In one embodiment, the selector 740 divides the voltage DV3 to be the reference voltage VREF when the selection signal SENSEL is enabled. In this example, when the selection signal SENSEL is disabled, the selector 740 uses the divided voltage DV2 as the reference voltage VREF, and the divided voltage DV2 is necessarily smaller than the original reference voltage VREF, so as to reduce power consumption, and the ratio of reducing power consumption depends on the configuration of the resistors 720 to 735. For example, in an embodiment, the level of the divided voltage DV2 may be configured to be half of the level of the reference voltage VREF, and the level of the divided voltage DV3 may also be configured to be half of the level of the divided voltage DV2, so that half of the power consumption may be reduced without changing the current.

FIG. 8 is a timing control diagram of the image control circuit according to the present invention. For convenience of explanation, the image control circuit 200 of fig. 2 is taken as an example. During an initial period 805, the logic circuit 145 enables the selection signal SENSEL. In the present embodiment, when the selection signal SENSEL is enabled, the selection signal SENSEL is at a high level. Then, the logic circuit 145 sets the control signal PDDAC to a low level to activate the

voltage generating circuits

205 and 110 and the current generating circuit 105. In this example, the current generation circuit 105 generates the reference current BIAS according to the reference voltage VBG1, and the voltage generation circuit 110 generates the reference voltage VREF according to the reference voltage VBG 2. In the present embodiment, since the selection signal SENSEL is enabled, the current generation circuit 105 outputs a smaller reference current, and the voltage generation circuit 110 outputs a smaller reference voltage. Then, the logic circuit 145 sequentially asserts the control signals PDR, PDG, and PDB low to turn on the

switches

215, 220, and 225 one by one. Therefore, the

image generation circuits

115, 120, and 125 operate one by one. In this example, the

image generation circuits

115, 120 and 125 generate the image currents IR, IG and IB respectively according to the reference current BIAS. When the image currents IR, IG and IB respectively flow through the first, second and third resistors, if the screen 150 is not coupled to the image control circuit 200, the voltages of the first, second and third resistors are respectively equal to the first, second and third preset values. However, if the screen 150 is coupled to the image control circuit 200, the voltages of the first, second and third resistors are respectively smaller than the first, second and third preset values.

Therefore, during a detection period 810, the logic circuit 145 sets the control signal PDSENSE low to enable the

detection circuits

130, 135 and 140. The

detection circuits

130, 135 and 140 respectively determine whether the voltages of the first, second and third resistors are lower than the reference voltage VREF, and generate detection signals SENSE _ R, SENSE _ G and SENSE _ B. Since SENSE _ R, SENSE _ G and SENSE _ B are the same, only SENSE _ R is shown in FIG. 8. In the embodiment, since the screen 150 is not coupled to the image control circuit 200, the voltage of the first resistor is not lower than the reference voltage VREF, and therefore the detection signal SENSE _ R is at a low level.

During an operation 815, the logic circuit 145 sets the control signal PDSSENSE to a high level since the screen 150 is not coupled to the image control circuit 200. Therefore, the

detection circuits

130, 135 and 140 stop operating. During this period, the logic circuit 145 sets the control signals PDB, PDG, and PDR to high level one by one. Accordingly, the

switches

225, 220, and 215 are turned off one by one, and the

image generation circuits

125, 120, and 115 stop generating the image currents one by one. In other embodiments, logic 145 closes

switches

225, 220, and 215 simultaneously. Therefore, the

image generation circuits

125, 120, and 115 stop operating at the same time. Finally, the logic circuit 145 sets the control signal PDDAC to a high level. At this time, the current generation circuit 105 and the

voltage generation circuits

205 and 110 stop operating.

FIG. 9 is another timing control diagram of the image control circuit 200 according to the present invention. In an initial period 905, the logic circuit 145 first enables the selection signal SENSEL and then sets the control signal PDDAC to a low level to activate the current generation circuit 105 and the

voltage generation circuits

205 and 110. Accordingly, the current generation circuit 105 generates the reference current BIAS, and the voltage generation circuit 110 generates the reference voltage VREF. At this time, the reference current BIAS has a first level, and the reference voltage VREF has a third level. Then, the logic circuit 145 sets the control signals PDR, PDG, and PDB to low level one by one, so that the

switches

215, 220, and 225 are turned on one by one. Accordingly, the

image generation circuits

115, 120, and 125 generate the image currents IR, IG, and IB one by one. At this time, the logic circuit 145 makes the control signal PDSSE high, indicating that the

detection circuits

130, 135 and 140 are not activated, so the detection signal SENSE _ R is low.

During a detection period 910, the logic circuit 145 sets the control signal PDSENSE low to enable the

detection circuits

130, 135 and 140. At this time, the

detection circuits

130, 135 and 140 start to detect whether the voltages of the first, second and third resistors are lower than the reference voltage VREF. Since the operation principles of the

detection circuits

130, 135 and 140 are similar, the detection circuit 130 is only used as an example. It is assumed that the screen 150 is coupled to the image control circuit 200. Since the voltage of the first resistor is lower than the reference voltage VREF, the detection signal SENSE _ R changes from a low level to a high level.

During an operation 915, the logic circuit 145 disables the selection signal SENSEL because the detection signal SENSE _ R is high. In the present embodiment, the logic circuit 145 sets the selection signal SENSEL to a low level. Therefore, the current generation circuit 105 increases the reference current BIAS, and the voltage generation circuit 110 increases the reference voltage VREF. In this example, the reference current BIAS rises from the first level to a second level, and the reference voltage VREF rises from the third level to a fourth level. In the present embodiment, the first level is half of the second level, and the third level is half of the fourth level. During operation 915, logic circuit 145 sets control signal PDSSENSE high. Therefore, the

detection circuits

130, 135 and 140 stop detecting the voltages of the first, second and third resistors, so that the detection signal SENSE _ R is low.

In one embodiment, logic 145 sets control signal PDSNESE low after a fixed time (i.e., the duration of operation period 915) when control signal PDSSE is high. Therefore, during the detection period 920, the

detection circuits

130, 135 and 140 detect the voltages of the first, second and third resistors again. It is assumed that the screen 150 is no longer coupled to the image control circuit 200. Therefore, the detection signal SENSE _ R is low.

During operation 925, the logic circuit 145 sets the control signal PDSENSE high to stop detecting the voltages of the first, second and third resistors. During this period, since the screen 150 is not coupled to the image control circuit 200, the logic circuit 145 enables the selection signal SENSEL. Therefore, the current generation circuit 105 reduces the reference current BIAS, and the voltage generation circuit 110 reduces the reference voltage VREF. In one embodiment, the reference current BIAS is reduced from the second level to the first level, and the reference voltage VREF is reduced from the fourth level to the third level. Then, the logic circuit 145 sets the control signals PDB, PDG and PDR to high level one by one to turn off the

switches

225, 220 and 215 one by one. Accordingly, the

image generation circuits

125, 120, and 115 stop generating the image currents IB, IG, and IR one by one.

Since the

image generation circuits

125, 120 and 115 stop operating one by one, it will not cause too much current bounce and will not cause electromagnetic interference (EMI) to other circuits. In addition, since the logic circuit 145 controls the current generating circuit 105 and the voltage generating circuit 110 according to the detection results of the detecting

circuits

130, 135 and 140, the reference current BIAS and the reference voltage VREF are reduced when the screen 150 is not coupled to the image control circuit 200, and the reference current BIAS and the reference voltage VREF are increased when the screen 150 is coupled to the image control circuit 200, so that the power consumption of the voltage generating circuit 110 and the current generating circuit 105 can be reduced.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as commonly understood by one of ordinary skill in the art to which this invention belongs. Moreover, unless expressly stated otherwise, the definition of a term in a general dictionary shall be construed as being consistent with its meaning in the context of the relevant art and shall not be construed as an idealized or overly formal definition.

Although the present invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. For example, the systems, devices, or methods disclosed in the embodiments of the present invention may be implemented in hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention is defined by the appended claims.

Claims

1. An image control circuit, comprising:

a current generation circuit for generating a reference current according to the selection signal;

a voltage generating circuit for generating a reference voltage according to the selection signal;

the first image generating circuit is coupled with the first resistor and generates a first image current according to the reference current;

the detection circuit is used for detecting the voltage of the first resistor and comparing the voltage of the first resistor with the reference voltage so as to generate a first detection signal; and

and a logic circuit that enables or disables the selection signal according to the first detection signal, wherein the logic circuit disables the selection signal when the voltage of the first resistor is less than the reference voltage, and the current generation circuit increases the reference current and the voltage generation circuit increases the reference voltage when the selection signal is disabled.

2. The image control circuit of claim 1, further comprising:

the second image generating circuit is coupled with the second resistor and generates a second image current according to the reference current;

the second detection circuit is used for detecting the voltage of the second resistor and comparing the voltage of the second resistor with the reference voltage so as to generate a second detection signal;

when none of the first detection signal and the second detection signal is enabled, indicating that no display device is coupled to the image control circuit; and

when at least one of the first detection signal and the second detection signal is enabled, it indicates that a display device is coupled to the image control circuit, and a circuit on the display device corresponding to the disabled one of the first detection signal and the second detection signal or a line/pin/interface connecting the image control circuit and the display device has a fault.

3. The image control circuit of claim 1, wherein the first image generation circuit comprises:

a first transistor, a gate of which receives the reference current, and a source of which receives an operating voltage;

a first switch coupled between a drain of the first transistor and a ground node; and

a second switch coupled between the drain of the first transistor and the first resistor, wherein the second switch is non-conductive when the first switch is conductive, and the first switch is non-conductive when the second switch is conductive.

4. The image control circuit of claim 3, further comprising:

a second image generating circuit, comprising:

a second transistor having a gate receiving the reference current and a source receiving the operating voltage;

a third switch coupled between the drain of the second transistor and the ground node; and

a fourth switch coupled between the drain of the second transistor and the second resistor, wherein the fourth switch is turned off when the third switch is turned on, and the third switch is turned off when the fourth switch is turned on; and

a third image generating circuit, comprising:

a third transistor whose gate receives the reference current and whose source receives the operating voltage;

a fifth switch coupled between the drain of the third transistor and the ground node; and

a sixth switch coupled between the drain of the third transistor and a third resistor, wherein the sixth switch is turned off when the fifth switch is turned on, and the fifth switch is turned off when the sixth switch is turned on.

5. The image control circuit of claim 4, further comprising:

a seventh switch, coupled between the current generating circuit and the first image generating circuit, for transmitting the reference current to the first transistor;

an eighth switch, coupled between the current generating circuit and the second image generating circuit, for transmitting the reference current to the second transistor; and

a ninth switch, coupled between the current generating circuit and the third image generating circuit, for transmitting the reference current to the third transistor.

6. The image control circuit as claimed in claim 5, wherein during an initial period, the logic circuit first enables the selection signal, then starts the current generation circuit and the voltage generation circuit, and then turns on the seventh, eighth and ninth switches.

7. The image control circuit of claim 5 wherein the logic circuit turns on the seventh, eighth and ninth switches one by one.

8. The image control circuit as claimed in claim 5, wherein the logic circuit turns off the ninth, eighth and seventh switches one by one when the voltage of the first resistor is not less than the reference voltage.

9. The image control circuit as claimed in claim 5, wherein the logic circuit enables the selection signal when the voltage of the first resistor is not less than the reference voltage, the reference current has a first level when the selection signal is enabled, the reference current has a second level when the selection signal is disabled, and the first level is less than the second level.

10. The image control circuit as claimed in claim 5, wherein when the voltage of the first resistor is not less than the reference voltage, the logic circuit first enables the selection signal and then turns off the ninth, eighth and seventh switches one by one.

11. The image control circuit of claim 1, wherein the current generation circuit comprises:

a first operational amplifier having a first inverting input terminal and a first non-inverting input terminal, the first inverting input terminal receiving a first reference voltage;

a fourth transistor, a gate of which is coupled to the output terminal of the first operational amplifier, a source of which receives an operating voltage, and a drain of which is coupled to the first non-inverting input terminal;

a fifth transistor, a source thereof receiving the operating voltage, and a drain thereof coupled to the first non-inverting input terminal; and

a tenth switch coupled between the gate of the fourth transistor and the gate of the fifth transistor.

12. The image control circuit of claim 11 wherein the logic circuit turns on the tenth switch when the voltage of the first resistor is not less than the reference voltage, and turns off the tenth switch when the voltage of the first resistor is less than the reference voltage.

13. The image control circuit of claim 1, wherein the selection signal is enabled when the voltage of the first resistor is not less than the reference voltage, the reference voltage has a third level when the selection signal is enabled, the reference voltage has a fourth level when the selection signal is disabled, and the third level is less than the fourth level.

14. The image control circuit of claim 13, wherein the voltage generation circuit comprises:

a second operational amplifier having a second inverting input terminal and a second non-inverting input terminal, the second inverting input terminal receiving a second reference voltage;

a sixth transistor, having a gate coupled to the output terminal of the second operational amplifier, a source receiving an operating voltage, and a drain coupled to the second non-inverting input terminal;

the resistor string is coupled between the drain electrode of the sixth transistor and a grounding node and used for generating a plurality of partial voltages; and

and a selector for selecting one of the divided voltages as the reference voltage according to the selection signal.

15. The image control circuit of claim 14, wherein the fourth level is less than the second reference voltage.

16. The image control circuit of claim 1 wherein the current generation circuit converts a first reference voltage to generate the reference current, and the voltage generation circuit converts a second reference voltage to generate the reference voltage, the first reference voltage not being equal to the second reference voltage.