CN108092532B - Inverter dead zone compensation method based on PWM trigger terminal voltage sampling - Google Patents

Inverter dead zone compensation method based on PWM trigger terminal voltage sampling Download PDF

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CN108092532B
CN108092532B CN201711494910.XA CN201711494910A CN108092532B CN 108092532 B CN108092532 B CN 108092532B CN 201711494910 A CN201711494910 A CN 201711494910A CN 108092532 B CN108092532 B CN 108092532B
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phase
voltage
terminal voltage
compensation
time
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CN108092532A (en
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王大方
刘刚
汤志皓
蔡金逸
徐泽绪
汪井威
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Harbin Institute of Technology Weihai
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/175—Indicating the instants of passage of current or voltage through a given value, e.g. passage through zero
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter

Abstract

An inverter dead zone compensation method based on PWM trigger terminal voltage sampling relates to an inverter switching strategy and comprises the following steps: PWM Module configuration, configuration PComparison registers of WM1, PWM2, PWM3, PWM4, PWM5, and PWM 6; configuring an ADC module; reading the terminal voltage conversion value at the beginning of a switching period, reordering ADC channels and resetting the sequencer; filtering the three-phase terminal voltage value obtained by sampling; judging the polarity of the three-phase current; calculating the compensation time; according to the formula
Figure DDA0001536221030000011
Calculating a compensation voltage; performing Clarke transformation on the three-phase compensation voltage to obtain compensation voltage under a two-phase static coordinate system; adding the voltage to a target voltage under a two-phase static coordinate system to obtain a compensated target voltage; and taking the target voltage as input, executing a space vector pulse width modulation strategy, and obtaining the three-phase duty ratio of the next switching period.

Description

Inverter dead zone compensation method based on PWM trigger terminal voltage sampling
Technical Field
The invention relates to an inverter switching strategy, in particular to an inverter dead zone compensation method based on PWM trigger terminal voltage sampling, which does not rely on current detection, can realize accurate current polarity judgment and compensation time calculation in a current zero-crossing interval, and has the advantages of low cost and wide application range.
Background
It is known that in the space vector pulse width modulation strategy of the inverter, the dead zone is inserted to prevent the short circuit at the direct current side caused by the direct connection of the switching devices of the upper and lower bridges in the same phase of the inverter, but the distortion of the output voltage and current waveforms of the inverter is also caused, and the harmonic content of the output waveforms is greatly increased. In an alternating current motor driving system adopting constant voltage frequency ratio control, waveform distortion caused by dead zone insertion can increase the fluctuation degree of torque and rotating speed when a motor runs at low speed, and the load carrying capacity is reduced. In an alternating current motor driving system adopting vector control, the stability of rotating speed control and the stability of torque output can be reduced due to the nonlinear characteristic of an inverter caused by dead zone insertion when a motor runs at a low speed, and the accuracy of voltage-dependent flux linkage estimation and parameter identification algorithms can be reduced due to the difference between actual voltage and target voltage caused by the dead zone. With the increasing application of ac motor driving systems, the energy loss and performance loss caused by the output distortion problem of the inverter are receiving increasing attention, and especially in some high-performance occasions, effective compensation of dead zones becomes a necessary means for improving the motor performance.
The existing dead zone compensation method can be divided into: a volt-second balance theory-based method, an error observation method, a current harmonic filtering method and a dead zone elimination method.
The error observation method estimates the total voltage error through an error observer, the method needs accurate motor parameters, is greatly influenced by parameter changes, has higher requirements on experience due to parameter adjustment, and can be applied only to a system with a rotating speed sensor and at least two current sensors.
The current harmonic filtering method calculates a compensation voltage by filtering out 6 th order current harmonics in the dq synchronous rotating coordinate system. Although the current harmonic filtering method does not depend on current polarity detection and motor parameters, the transient characteristics and compensation accuracy are poor, and the current harmonic filtering method can only be applied to a motor control system with a current loop and adopting vector control.
The dead zone elimination method detects the current polarity through an auxiliary hardware circuit, and then only conducts one switching tube in the same phase bridge arm according to the current polarity, so that the dead zone does not need to be inserted. However, this method does not take into account switching time and voltage drop. The dead zone cancellation method requires highly accurate current polarity detection because erroneous current polarity detection results in very severe voltage distortion.
The method based on volt-second balance theory divides the factors causing inverter output distortion into dead zone insertion, switching time and voltage drop, including forward voltage drop and freewheeling diode voltage drop. The method quantifies the influence of each factor on the voltage distortion by calibrating or modeling the switching device off-line to realize on-line compensation. The accurate detection of the current polarity at the zero crossing of the current and the determination of the compensation time are two key points of this method.
The existing current polarity detection method mainly comprises the following steps: (1) the current sensor is directly used for detecting the current polarity, and the defect is that the A/D conversion of the current is seriously influenced by zero drift and noise when the current passes through a zero point; (2) the current is filtered, and the defect is that larger phase delay is caused, so that the current detection in the current zero-crossing interval is inaccurate; (3) the auxiliary hardware circuit is adopted to detect the current polarity, and the defects are that the required hardware circuit is complex, the cost is increased, the reliability is reduced, and the auxiliary hardware circuit is difficult to apply in practice. The existing method for determining the compensation time mainly comprises the following steps: (1) the off-line calibration method has the disadvantages that a large amount of time is consumed, and the method is poor in universality; (2) the auxiliary hardware circuit is adopted to measure the terminal voltage duty ratio on line, and the defect is that the slope of the terminal voltage edge changes when the current crosses zero, the hardware circuit can generate a measurement error as much as 1/4 dead time, and the hardware has high cost and is difficult to apply in practice; (3) the switching device is modeled, and the defect is that the model depends on current detection, so the accuracy of compensation time calculation at the time of a current zero crossing point is still low. Although the method based on volt-second equilibrium principle seems accurate, this method needs to solve the problem of weak current measurement in noisy environments.
Considering dead zones, drive circuit delays, switching times and voltage drops, a detailed voltage distortion analysis is shown in fig. 1. In the figure, the forward current means that a current flows from the inverter to the motor, TdIs the dead time, TtonAnd TtoffIs the propagation delay, T, of the rising and falling edges of the drive signaldonIs a conduction delay, TdoffIs a turn-off delay, TrAnd TfRespectively, an equivalent rise time and an equivalent fall time, Δ T, obtained according to the volt-second equilibrium principleriseAnd Δ TfallTotal terminal voltage rising and falling edge delays, T, respectivelysIs the time interval between the actual turn-off time of the upper (lower) bridge switching tube and the actual turn-on time of the lower (upper) bridge switching tube, UDCIs a DC bus voltage, UDIs a diode drop, UFIs the forward voltage drop, T, of the IGBTPWMIs the switching period, U*Is an instruction voltage, U*In the range of 0 to UDC。
From fig. 1, the expression for the compensation voltage is derived as follows:
Figure GDA0002294267340000021
Tc＝ΔTrise-ΔTfall(2)
in the formula: t iscIs the compensation time, i.e. the error between the ideal terminal voltage duty cycle and the actual terminal voltage duty cycle;
i is a phase current of the phase current,
Figure GDA0002294267340000022
is a redefined command voltage in the range-UDC/2～UDC/2。
Disclosure of Invention
The invention aims to solve the defects of the prior art, overcome the defect that the conventional inverter dead zone compensation method is difficult to realize accurate compensation in the current zero-crossing interval, and provide the inverter dead zone compensation method which does not rely on current detection, can realize accurate current polarity judgment and compensation time calculation in the current zero-crossing interval, has wide application range and low cost and is based on PWM trigger end voltage sampling
The invention solves the defects of the prior art and adopts the technical scheme that:
an inverter dead zone compensation method based on PWM trigger terminal voltage sampling is characterized by comprising the following steps:
(1) the PWM module is configured, a first comparison register of PWM1, PWM2 and PWM3 is configured to generate driving signals of a switching tube of a three-phase bridge arm of the inverter, a first comparison register and a second comparison register of PWM4, PWM5 and PWM6 are configured to trigger sampling of voltage of three-phase terminals, and PWM4, PWM5 and PWM6 are disabled to output;
(2) configuring an ADC module, setting 16 channels of the ADC into a cascade mode, enabling a first signal to be converted and a second signal to be converted from a PWM module, and setting the number of trigger conversion of each trigger source to be 1;
(3) reading the terminal voltage transition value at the beginning of a switching cycle, reordering the ADC channels according to table 1 and resetting the sequencer,
TABLE 1
Figure GDA0002294267340000023
U in Table 1arAnd UafThe method comprises the following steps of sampling voltages near a rising edge and a falling edge of a voltage at an A-phase end respectively; u shapebrAnd UbfThe method comprises the following steps of sampling voltages near a rising edge and a falling edge of a voltage at a phase B end respectively; u shapecrAnd UcfThe method comprises the following steps of sampling voltages near a rising edge and a falling edge of a voltage at a C-phase end respectively;
the voltage sampling time is specifically as follows:
Figure GDA0002294267340000024
wherein: the PWM waveform is divided into a PWM waveform rising edge moment and a PWM waveform falling edge moment; t is toffsetIs a sampling time offset value; t isdIs the dead time; t istonThe delay time of the gate drive circuit to the rising edge; t isdonDelaying the opening of the IGBT; t isfbkIs the delay time of the terminal voltage feedback circuit, which is not negligible in the isolated inverter;
(4) filtering the three-phase terminal voltage value obtained by sampling, wherein the filtering algorithm comprises the following steps:
a. selecting the voltage signal of the A-phase end obtained by sampling as a reference signal, and if the value of the reference signal is changed from high level to low level and the signal keeps low level within the angle of α, resetting the phase angle theta of the reference to α, wherein theta is the phase angle of the voltage signal of the A-phase end;
b. if the edges of the B-phase terminal voltage signal and the C-phase terminal voltage signal do not appear in the allowed phase angle range, the edges are considered as noise;
c. selecting the B-phase terminal voltage signal or the C-phase terminal voltage signal processed in the step B as a reference signal, and if the value of the reference signal changes from high level to low level and the signal keeps low level within the angle of α, resetting the phase angle theta 1 of the reference to α, wherein theta 1 is the phase angle of the B-phase terminal voltage signal or the C-phase terminal voltage signal;
d. if the edge of the A-phase terminal voltage signal does not appear in the allowable phase angle range, the edge is considered as noise;
wherein α is obtained by debugging that α is 1.1-1.3 times of the maximum continuous angle of abnormal low level of A phase end voltage signal in one period, the allowable phase angle range is theoretical angle range plus or minus phase angle allowable error, and the phase angle allowable error is usually 10 °
(5) And judging the polarity of the three-phase current, wherein the current polarity judging method comprises the following steps:
Figure GDA0002294267340000031
i is the phase current, where: i.e. irCurrent polarity at the rising edge of the terminal voltage; i.e. ifIs the current polarity at the falling edge of the terminal voltage; i.e. ieIs the equivalent current polarity within one switching period; u shapeDCIs the dc bus voltage; u shaperThe voltage is sampled near the rising edge of the terminal voltage; u shapefThe terminal voltage is obtained by sampling near the terminal voltage falling edge;
the voltage sampling time is specifically as follows:
Figure GDA0002294267340000032
wherein: PWMn.CMPA refers to the rising edge moment of the PWM waveform, and PWMn.CMPB refers to the falling edge moment of the PWM waveform; t is toffsetIs a sampling time offset value; t isdIs the dead time; t istonThe delay time of the gate drive circuit to the rising edge; t isdonDelaying the opening of the IGBT; t isfbkIs the delay time of the terminal voltage feedback circuit, which is not negligible in the isolated inverter;
(6) calculating the compensation time TcThe calculation method is as follows:
Figure GDA0002294267340000041
Figure GDA0002294267340000042
Figure GDA0002294267340000043
in the formula: t isrAnd TfRespectively, an equivalent rise time and an equivalent fall time, T, obtained according to the volt-second equilibrium principledIs the dead time.
(7) Substituting the current polarity obtained in the step (5) and the compensation time obtained in the step (6) into an expression:
Figure GDA0002294267340000044
the compensation voltage is calculated and the compensation voltage is calculated,
wherein, TcIs the compensation time, i.e. the error between the ideal terminal voltage duty cycle and the actual terminal voltage duty cycle; t isPWMIs the switching period, UDCIs a DC bus voltage, UDIs a diode drop, UFIs the forward voltage drop of the IGBT,
Figure GDA0002294267340000045
is a redefined command voltage in the range-UDC/2～UDC/2；
(8) Performing Clarke transformation on the three-phase compensation voltage obtained by calculation in the step (7) to obtain compensation voltage under a two-phase static coordinate system;
(9) adding the compensation voltage under the two-phase static coordinate system obtained by calculation in the step (8) to the target voltage under the two-phase static coordinate system to obtain a compensated target voltage;
(10) taking the compensated target voltage obtained in the step (9) as input, and executing a space vector pulse width modulation strategy to obtain a three-phase duty ratio of the next switching period;
(11) the voltage sampling time is determined, and the method for determining the sampling time is as follows:
Figure GDA0002294267340000046
wherein: t is toffsetIs a sampling time offset value; t isdIs the dead time; t istonThe delay time of the gate drive circuit to the rising edge; t isdonDelaying the opening of the switching device; t isfbkIs the delay time of the terminal voltage feedback circuit, which is not negligible in the isolated inverter;
and updating the first comparison register and the second comparison register of the PWM4, the PWM5 and the PWM6 according to the determined adoption time so as to sample the three-phase voltage in the next switching period.
The ADC channels in step 3 are sorted in the manner shown in Table 1, where U isarAnd UafThere are two voltage samples near the rising and falling edges of the voltage at the a-phase terminal, respectively. The reason why the ADC channels need to be reordered every switching period is that under space vector pulse width modulation, when the sector where the reference voltage vector is located changes, the sequence of the rising edge and the falling edge of the three-phase terminal voltage changes, so the sequence of the ADC channels triggered by PWM also changes with the sector.
The principle of the square wave filtering algorithm in step 4 is shown in fig. 2, and the steps are as follows:
(1) resetting θ to α if the value of the sampled a-phase terminal voltage signal changes from high level to low level and the signal keeps low level for an angle of α;
(2) if the edges of the B-phase terminal voltage signal and the C-phase terminal voltage signal do not appear in the allowed phase angle range, the edges are considered as noise;
(3) and filtering the voltage signal of the phase A end by taking the voltage signal of the phase B end or the phase C as a reference in the same way.
The current polarity determination method in step 5 is shown in fig. 3, and specifically includes the following steps:
Figure GDA0002294267340000051
in the formula: i.e. irCurrent polarity at the rising edge of the terminal voltage; i.e. ifIs the current polarity at the falling edge of the terminal voltage; i.e. ieIs the equivalent current polarity within one switching period; u shaperThe voltage is sampled near the rising edge of the terminal voltage; u shapefIs a terminal voltage sampled in the vicinity of a terminal voltage falling edge.
The compensation time calculation method in step 6 is as follows:
Figure GDA0002294267340000052
the method does not depend on current detection, carries out inverter dead zone compensation based on PWM trigger terminal voltage sampling, overcomes the problem of weak current detection in a current zero-crossing noise environment in the traditional dead zone compensation method, and realizes accurate dead zone compensation of the current zero-crossing; the method has the advantages of capability of realizing accurate current polarity judgment and compensation time calculation in the current zero-crossing interval, wide application range, low cost and the like.
Drawings
Fig. 1 is a voltage error analysis: wherein (a) i >0 and (b) i < 0.
Fig. 2 is a square wave filtering algorithm of the invention of this patent.
Fig. 3 is a method for detecting and determining current polarity of PWM trigger terminal voltage according to the present invention.
Fig. 4 shows a method for calculating the rise time and fall time of PWM trigger voltage detection according to the invention of this patent.
FIG. 5 is the equivalent rise time T at different currentsrAnd a fall time Tf: where (a) is the equivalent rise time and (b) is the equivalent fall time.
FIG. 6 is data extracted from DSP memory: the method comprises the following steps of (a) obtaining three-phase current, (b) obtaining A-phase compensation time and current, (c) obtaining original A-phase end voltage sampled near the voltage falling edge of the A-phase end under the electrical frequency of 5Hz, (d) obtaining filtered A-phase end voltage sampled near the voltage falling edge of the A-phase end under the electrical frequency of 5Hz, (e) obtaining A-phase current and terminal voltage sampled near the voltage rising edge of the A-phase end, and (f) obtaining the A-phase current and terminal voltage sampled near the voltage falling edge of the A-phase end.
FIG. 7 is a harmonic analysis of phase current and phase current compensated using different current polarity detection methods: wherein (a) is not compensated, (b) is current detection by the current sensor at the beginning of a switching cycle, (c) is current polarity determination by the compensation time, and (d) is terminal voltage detection method.
FIG. 8 is a phase current and its harmonic analysis for fixed compensation and modified fixed compensation: wherein (a) is a fixed compensation and (b) is an improved fixed compensation.
FIG. 9 is a phase current and harmonic analysis for the on-line calculation and the modified on-line calculation: wherein (a) is an online calculation method of the compensation time, and (b) is an improved online calculation method.
FIG. 10 is a phase current and harmonic analysis thereof for the feedback compensation method and the improved feedback compensation method: wherein (a) is a feedback compensation method and (b) is an improved feedback compensation.
Fig. 11 is a current harmonic under different compensation methods.
Detailed Description
The inverter dead zone compensation method based on PWM trigger terminal voltage sampling has the advantages of high accuracy and low cost independent of current detection.
(1) The PWM module is configured, a first comparison register of PWM1, PWM2 and PWM3 is configured to generate driving signals of a switching tube of a three-phase bridge arm of the inverter, a first comparison register and a second comparison register of PWM4, PWM5 and PWM6 are configured to trigger sampling of voltage of three-phase terminals, and PWM4, PWM5 and PWM6 are disabled to output;
(2) configuring an ADC module, setting 16 channels of the ADC into a cascade mode, enabling a first signal to be converted and a second signal to be converted from a PWM module, and setting the number of trigger conversion of each trigger source to be 1;
(3) reading the terminal voltage conversion value at the beginning of a switching period, reordering ADC channels according to the ordering mode (table 1) of the invention, and resetting the sequencer; table 1 is ADC channel ordering.
(4) Filtering the sampled three-phase terminal voltage value according to a square wave filtering algorithm (figure 2) disclosed by the invention;
(5) judging the polarity of the three-phase current according to the current polarity judging method (figure 3) disclosed by the invention;
(6) the compensation time calculation is carried out according to the compensation time calculation method (figure 4) of the invention of the patent;
(7) substituting the current polarity obtained in the step (5) and the compensation time obtained in the step (6) into an expression (1), and calculating a compensation voltage;
(8) performing Clarke transformation on the three-phase compensation voltage obtained by calculation in the step (7) to obtain compensation voltage under a two-phase static coordinate system;
(9) adding the compensation voltage under the two-phase static coordinate system obtained by calculation in the step (8) to the target voltage under the two-phase static coordinate system to obtain a compensated target voltage;
(10) taking the compensated target voltage obtained in the step (9) as input, and executing a space vector pulse width modulation strategy to obtain a three-phase duty ratio of the next switching period;
(11) according to the sampling time determining method disclosed by the patent, the first comparison register and the second comparison register of the PWM4, the PWM5 and the PWM6 are updated for sampling the three-phase voltage in the next switching period.
The ADC channels in step 3 are sorted in the manner shown in Table 1, where U isarAnd UafThere are two voltage samples near the rising and falling edges of the voltage at the a-phase terminal, respectively. The reason why the ADC channels need to be reordered every switching period is that under space vector pulse width modulation, when the sector where the reference voltage vector is located changes, the sequence of the rising edge and the falling edge of the three-phase terminal voltage changes, so the sequence of the ADC channels triggered by PWM also changes with the sector.
The principle of the square wave filtering algorithm in the step 4 is shown in fig. 2, and the filtering algorithm filters the three-phase terminal voltage value obtained by sampling, and comprises the following steps:
a. selecting the voltage signal of the A-phase end obtained by sampling as a reference signal, and if the value of the reference signal is changed from high level to low level and the signal keeps low level within the angle of α, resetting the phase angle theta of the reference to α, wherein theta is the phase angle of the voltage signal of the A-phase end;
b. if the edges of the B-phase terminal voltage signal and the C-phase terminal voltage signal do not appear in the allowed phase angle range, the edges are considered as noise;
c. selecting the B-phase terminal voltage signal or the C-phase terminal voltage signal processed in the step B as a reference signal, and if the value of the reference signal changes from high level to low level and the signal keeps low level within the angle of α, resetting the phase angle theta 1 of the reference to α, wherein theta 1 is the phase angle of the B-phase terminal voltage signal or the C-phase terminal voltage signal;
d. if the edge of the A-phase terminal voltage signal does not appear in the allowable phase angle range, the edge is considered as noise;
α is obtained through debugging, α needs to be slightly larger than the maximum duration angle of the abnormal low level of the a-phase terminal voltage signal in one period, the maximum duration angle of the abnormal low level is related to the noise environment of the device itself, and is measured through experiments, and α in this embodiment is 1.2 times the maximum duration angle of the abnormal low level.
The allowable phase angle range is a theoretical angle range plus or minus a phase angle allowable error; the allowable phase angle range is obtained by: in the first step, the falling edge of the voltage signal at the a-phase end is defined as 0 degree, the theoretical angles corresponding to the falling edges of the voltage signal at the B-phase end and the voltage signal at the C-phase end should be 120 degrees and 240 degrees, respectively, the theoretical angles corresponding to the rising edges of the voltage signal at the B-phase end and the voltage signal at the C-phase end should be 300 degrees and 60 degrees, respectively, the allowable phase angle range is the theoretical angle plus-minus phase angle allowable error, the phase angle allowable error is also related to a specific electromagnetic noise environment, and needs to be obtained through experiments, and the selection needs to follow the following principle: abnormal jumping edges can be filtered, normal jumping edges cannot be filtered, and the abnormal jumping edges are as small as possible; the allowable error of the phase angle is 10 ° in the present embodiment.
The current polarity determination method in step 5 is shown in fig. 3, and specifically includes the following steps:
Figure GDA0002294267340000071
in the formula: i.e. irCurrent polarity at the rising edge of the terminal voltage; i.e. ifIs the current polarity at the falling edge of the terminal voltage; i.e. ieIs the equivalent current polarity within one switching period; u shaperThe voltage is sampled near the rising edge of the terminal voltage; u shapefIs a terminal voltage sampled in the vicinity of a terminal voltage falling edge.
The compensation time calculation method in step 6 is as follows:
Figure GDA0002294267340000072
the sampling time in step 11 is shown in fig. 3, and specifically as follows:
Figure GDA0002294267340000073
wherein: t is toffsetIs a sampling time offset value; t isdIs the dead time; t istonThe delay time of the gate drive circuit to the rising edge; t isdonDelaying the opening of the switching device; t isfbkIs the delay time of the terminal voltage feedback circuit, which is not negligible in the isolated inverter;
the theory of the invention is as follows:
in the calculation of the compensation voltage, TcIs very critical, but TcIt is difficult to obtain directly. Although the existing method utilizes an input capture module of the DSP to realize the feedback of the terminal voltage duty ratio, when the current crosses the zero point, the slope of the terminal voltage changes, the measuring circuit generates measuring errors as much as 1/4 dead time, so that the T under different currents is modeled and analyzedcIs necessary.
Δ T according to FIG. 1 and expression (2)rise,ΔTfallAnd TcThe expression of (a) is derived as follows:
Figure GDA0002294267340000081
at TcIn the component item of (1), the dead time TdIs stationary. Propagation delay TtonAnd TtoffThe variations are very small because the operating conditions of the drive circuits hardly change and, in addition, they can cancel each other out. Although the turn-on delay and the turn-off delay vary with current, they can also cancel each other out because the current change from the rising edge to the falling edge in one switching cycle is small. Therefore, TcThe expression of (c) can be simplified to:
Figure GDA0002294267340000082
equivalent rise time TrAnd a fall time TfCannot cancel each other out because even if the phase currents at the rising and falling edges are the same, they may be far apart. T isrAnd TfIs generated by charging and discharging of the parasitic capacitance of the IGBT and is closely related to the amplitude and the direction of the current, and T is derived according to the charging and discharging model of the parasitic capacitancerAnd Tf。
Current i at rising edgerWhen the polarity is negative, the terminal voltage linearly increases along with the time after the lower bridge switching tube is turned off, and the expression is as follows:
v＝irt/Cp(8)
in the formula: cpIs the total parasitic capacitance of the switching tubes of the upper bridge and the lower bridge of one phase.
In fig. 1, the time between the time when the upper bridge switch tube is actually turned off and the time when the lower bridge switch tube is actually turned on is defined as Ts，TsExpression (c):
Ts＝Td+(Tton-Ttoff)+(Tdon-Tdoff) (9)
Ttonand Ttoff，TdonAnd TdoffThe difference between them is negligible, and therefore,Tsequal to dead time Td. When i isrEqual to the critical current IcWhen the terminal voltage is at TdRise to U exactly within timeDC。IcExpression (c):
Ic＝UDCCp/Td
(10)
when i isrWith positive polarity, the terminal voltage v rises to U in a very short timeDCSince the parasitic capacitance is connected directly to the DC bus after the upper bridge is switched on, at TrThis time period was ignored in the analysis of (1). The trend of the voltage v at the lower end of different currents is given in fig. 5, where the thin dotted line represents the equivalent rising edge. The equivalent process is based on the principle of averaging, that is, the areas of the blue and red regions are the same in fig. 5. Accordingly, the rise time TrThe derivation is as follows:
Figure GDA0002294267340000091
likewise, the fall time T at different currentsfThe derivation is as follows:
v＝UDC-ift/Cp(12)
Figure GDA0002294267340000092
current i at terminal voltage falling edgefWhen the polarity is negative, the parasitic capacitance is short-circuited after the lower bridge switching tube is opened, and the terminal voltage v is reduced to zero in a short time. At TfThis time period is also ignored in the analysis of (1).
From the above analysis, it can be seen that different current polarities and amplitudes correspond to different slope change laws of the terminal voltage edge. According to the analysis, the patent provides the inverter dead zone compensation method based on the PWM trigger end voltage sampling, which is independent of current detection, the problem of weak current detection in a current zero-crossing noise environment in the traditional dead zone compensation method is solved, and accurate dead zone compensation of the current zero-crossing is realized.
The experiments that can prove the effect of the method of the invention are as follows, and the parameters of the experimental platform are shown in tables 2 and 3; table 2 shows the experimental two-level inverter parameters. Table 3 shows the experimental induction machine parameters.
1. Comparison of different current polarity detection methods
In this part of the experiment, the compensation time was obtained by terminal voltage duty cycle feedback. Although the method has some defects in the current zero-crossing interval, when the only variable is the current polarity detection method, the fairness of the comparison experiment is not influenced by the defects of the terminal voltage duty ratio feedback method. In addition to the terminal voltage detection method of the present invention, there are other two current polarity detection methods. The three methods are:
(1) the current is sensed by the current sensor at the beginning of a switching cycle, which is one of the most widely used methods in practice;
(2) and an auxiliary feedback circuit is adopted to obtain the actual terminal voltage duty ratio, and the actual terminal voltage duty ratio is subtracted from the terminal voltage duty ratio before dead zone insertion to obtain the terminal voltage duty ratio error, so that obviously, the phase current and the duty ratio error have the same polarity. The current polarity detection method has the advantages that the accuracy is far higher than that of a current sensor, and the following comparison experiment can prove that;
(3) the invention discloses a PWM trigger terminal voltage detection method.
The first method relies on current sampling, the second method relies on terminal voltage duty cycle feedback, and the method of the present invention relies on terminal voltage sampling. Before the experiment, the quality of signals depended on by the three methods needs to be ensured, and the data extracted from the DSP memory is shown in a figure 6.
As shown in fig. 6(a), the three-phase currents are substantially symmetrical, and the noise is small. Fig. 6(b) demonstrates that the polarity of the current can be judged by the compensation time. Fig. 6(c) and 6(d) demonstrate the effectiveness of the filtering algorithm of the invention of this patent. Fig. 6(e) and 6(f) demonstrate the effectiveness of the terminal voltage detection method of the present invention in determining the polarity of the current. In fact, the current sensor cannot be used as a test standard for the terminal voltage detection method because the terminal voltage detection method has higher current polarity detection accuracy, and the experiment of fig. 7 can prove.
When the dead zone compensation is not performed, the current distortion is very serious, as shown in fig. 7 (a). Fig. 7(b) to 7(d) reveal the differences in the different current polarity detection methods. The method for judging the current polarity through the compensation time and the terminal voltage detection method are obviously superior to the method for directly detecting the current polarity through a current sensor, although the difference between the two methods is small, the terminal voltage detection method does not depend on a duty ratio feedback circuit, and only 6 divider resistors are needed.
2. Improvement to existing compensation method
(1) Lifting of fixed compensation
The fixed compensation method simplifies the expression of the compensation voltage from (1) to:
Figure GDA0002294267340000101
in fixed compensation, the current polarity is detected by a current sensor or an auxiliary detection circuit, the compensation time is fixed as dead time, and the voltage drop is ignored. The fixed compensation method is a method which is applied in practice in many cases.
As can be seen from fig. 8, the terminal voltage detection method of the present invention improves the fixed compensation method obviously, because the detection of the current polarity and the calculation of the compensation time are more accurate after the two are combined. Moreover, the effect of this combination is comparable even to feedback compensation when the electrical frequency exceeds 10Hz, as shown in fig. 11. This shows that at medium and higher electrical frequencies, the current crosses the zero rapidly, the compensation time is almost always equal to the dead time, and the compensation effect depends mainly on the accuracy of the current polarity detection.
(2) Promotion of compensation time on-line calculation method
The effect of the compensation time on-line calculation method is between that of feedback compensation and fixed compensation, an auxiliary hardware circuit is not needed, and the cost is lower than that of feedback compensation. This method calculates the compensation time on-line using expressions similar to (11) and (13), and although the calculation is accurate in theory, the actual effect is somewhat compromised. Despite the difficulty in obtaining accurate parasitic capacitance values, this method relies on current sampling, which is difficult to achieve when the current crosses zero.
As shown in fig. 9, the compensation time on-line calculation method can obtain more accurate compensation time than the fixed compensation. The combination of this method and terminal voltage detection method is more effective than the former combination below an electrical frequency of 10Hz, but the effect is worse after the electrical frequency exceeds 10Hz, as shown in fig. 11, possibly because the parasitic capacitance varies with the operating condition of the switching tube.
(3) Boosting of feedback compensation
The feedback compensation method utilizes the auxiliary circuit and the input capture module of the DSP to realize the real-time feedback of the terminal voltage duty ratio. The principle of the circuit is very simple: the method comprises the steps of firstly dividing the end voltage through two resistors, then comparing the divided end voltage with a fixed voltage of which the amplitude is half of that of the divided end voltage by using a comparator, and finally inputting an output signal of the comparator into an input capture module of a DSP. The circuit produces little error when the slope of the terminal voltage edge is unchanged, but produces measurement errors as much as 1/4 dead time when the slope of the terminal voltage edge is changed.
As shown in fig. 10, by using a high-cost terminal voltage duty ratio feedback circuit, the feedback compensation method is undoubtedly the best one of the three comparison methods. Although the improvement is not obvious compared with the former two combinations, the PWM trigger end voltage detection method further improves the effect of the feedback compensation method.
TABLE 1
Figure GDA0002294267340000102
Figure GDA0002294267340000111
TABLE 2
Figure GDA0002294267340000112
TABLE 3
Figure GDA0002294267340000113

Claims (1)

1. An inverter dead zone compensation method based on PWM trigger terminal voltage sampling is characterized by comprising the following steps:
(1) the PWM module is configured, a first comparison register of PWM1, PWM2 and PWM3 is configured to generate driving signals of a switching tube of a three-phase bridge arm of the inverter, a first comparison register and a second comparison register of PWM4, PWM5 and PWM6 are configured to trigger sampling of voltage of three-phase terminals, and PWM4, PWM5 and PWM6 are disabled to output;
(2) configuring an ADC module, setting 16 channels of the ADC into a cascade mode, enabling a first signal to be converted and a second signal to be converted from a PWM module, and setting the number of trigger conversion of each trigger source to be 1;
(3) reading the terminal voltage transition value at the beginning of a switching cycle, reordering the ADC channels according to table 1 and resetting the sequencer,
TABLE 1
Figure FDA0002294267330000011
U in Table 1arAnd UafThe method comprises the following steps of sampling voltages near a rising edge and a falling edge of a voltage at an A-phase end respectively; u shapebrAnd UbfThe method comprises the following steps of sampling voltages near a rising edge and a falling edge of a voltage at a phase B end respectively; u shapecrAnd UcfThe method comprises the following steps of sampling voltages near a rising edge and a falling edge of a voltage at a C-phase end respectively; the voltage sampling time is specifically as follows:
Figure FDA0002294267330000012
wherein: PWMn.CMPA refers to the rising edge moment of the PWM waveform, and PWMn.CMPB refers to the falling edge moment of the PWM waveform; t is toffsetTo adoptA sample time offset value; t isdIs the dead time; t istonThe delay time of the gate drive circuit to the rising edge; t isdonDelaying the opening of the IGBT; t isfbkIs the delay time of the terminal voltage feedback circuit, which is not negligible in the isolated inverter;
(4) filtering the three-phase terminal voltage value obtained by sampling, wherein the filtering algorithm comprises the following steps:
a. selecting the voltage signal of the A-phase end obtained by sampling as a reference signal, and if the value of the reference signal is changed from high level to low level and the signal keeps low level within the angle of α, resetting the phase angle theta of the reference to α, wherein theta is the phase angle of the voltage signal of the A-phase end;
b. if the edges of the B-phase terminal voltage signal and the C-phase terminal voltage signal do not appear in the allowed phase angle range, the edges are considered as noise;
c. selecting the B-phase terminal voltage signal or the C-phase terminal voltage signal processed in the step B as a reference signal, and if the value of the reference signal changes from high level to low level and the signal keeps low level within the angle of α, resetting the phase angle theta 1 of the reference to α, wherein theta 1 is the phase angle of the B-phase terminal voltage signal or the C-phase terminal voltage signal;
d. if the edge of the A-phase terminal voltage signal does not appear in the allowable phase angle range, the edge is considered as noise;
wherein α is obtained by debugging, α is 1.1-1.3 times of the maximum continuous angle of the abnormal low level of the A-phase end voltage signal in one period, and the allowable phase angle range is a theoretical angle range plus or minus phase angle allowable error;
(5) and judging the polarity of the three-phase current, wherein the current polarity judging method comprises the following steps:
Figure FDA0002294267330000021
Figure FDA0002294267330000022
Figure FDA0002294267330000023
i is the phase current, where: i.e. irCurrent polarity at the rising edge of the terminal voltage; i.e. ifIs the current polarity at the falling edge of the terminal voltage; i.e. ieIs the equivalent current polarity within one switching period; u shapeDCIs the dc bus voltage; u shaperThe voltage is sampled near the rising edge of the terminal voltage; u shapefThe terminal voltage is obtained by sampling near the terminal voltage falling edge; the voltage sampling time is the same as the voltage sampling time in the step (3);
(6) calculating the compensation time TcThe calculation method is as follows:
Figure FDA0002294267330000024
Figure FDA0002294267330000025
Figure FDA0002294267330000026
in the formula: t isrAnd TfRespectively, an equivalent rise time and an equivalent fall time, T, obtained according to the volt-second equilibrium principledIs the dead time;
(7) substituting the current polarity obtained in the step (5) and the compensation time obtained in the step (6) into an expression:
Figure FDA0002294267330000027
the compensation voltage is calculated and the compensation voltage is calculated,
wherein, TcIs the compensation time, i.e. the error between the ideal terminal voltage duty cycle and the actual terminal voltage duty cycle; t isPWMIs the switching period, UDCIs a DC bus voltage, UDIs a diode drop, UFIs the forward voltage drop of the IGBT,
Figure FDA0002294267330000028
is a redefined command voltage in the range-UDC/2～UDC/2；
(8) Performing Clarke transformation on the three-phase compensation voltage obtained by calculation in the step (7) to obtain compensation voltage under a two-phase static coordinate system;
(9) adding the compensation voltage under the two-phase static coordinate system obtained by calculation in the step (8) to the target voltage under the two-phase static coordinate system to obtain a compensated target voltage;
(10) and (4) taking the compensated target voltage obtained in the step (9) as input, and executing a space vector pulse width modulation strategy to obtain the three-phase duty ratio of the next switching period.
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