CN108091625A - High power load chip - Google Patents
High power load chip Download PDFInfo
- Publication number
- CN108091625A CN108091625A CN201711413526.2A CN201711413526A CN108091625A CN 108091625 A CN108091625 A CN 108091625A CN 201711413526 A CN201711413526 A CN 201711413526A CN 108091625 A CN108091625 A CN 108091625A
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- CN
- China
- Prior art keywords
- metal tape
- tape line
- high power
- power load
- metallization via
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Non-Adjustable Resistors (AREA)
Abstract
The invention discloses a kind of high power load chips, it includes dielectric substrate, the first metal tape line, the second metal tape line and the thin film resistive layer being electrically arranged between the first metal tape line and the second metal tape line, dielectric substrate is internally provided with multiple metallization VIAs for being used to connect metal layer and the second metal tape line, the metallization VIA includes metallic region and areas of dielectric, the circumferentially-spaced arrangement of the metallic region and the areas of dielectric along the metallization VIA.The thin film resistive layer of high power load chip of the present invention can be under the premise of high power load chip matching impedance be fixed, ensure its good tolerance power, and dielectric substrate is internally provided with metallization VIA, metallization VIA has spaced apart metallic region and areas of dielectric, reduces buffer action of the equivalent inductance for high-frequency signal.
Description
Technical field
The present invention relates to chip technology field more particularly to a kind of high power load chips.
Background technology
With the development of science and technology with the continuous progress of social scientific and technological level, microwave and millimeter wave circuit is increasingly wider
Generally applied in the work of people and the scientific practice of society；For now, the most selections of microwave and millimeter wave circuit
Reference impedances of 50 Ω as system, therefore cascaded, in test measurement process in the system of multimode, it is required to the end of each module
Mouthful impedance, the characteristic impedance of connector, test cable are 50 Ω, and in multiport device, no port is also required to meet 50 Ω
Matched load carrys out absorption signal, avoids in signal reflex telegram in reply road, influences device performance.
Therefore in HIGH-POWERED MICROWAVES product, if the underpower that 50 Ω loads can bear, it is possible to load can be caused
Or damage of product, have a negative impact to the normal work of microwave and millimeter wave circuit；But in existing high power load chip, if
Want expand its bear power, often change supported chip inside matching impedance, and then be unfavorable for and microwave and millimeter wave electricity
Other modules in road match.
The content of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of based on the high-power of single metal via
Supported chip can ensure its good tolerance power, and reduce under the premise of high power load chip matching impedance is fixed
Influence of the equivalent inductance of metallization VIA to high-frequency signal makes supported chip that can either apply and high frequency environment, can also answer
For low frequency environments.
To achieve the above object, the present invention provides following technical solution：A kind of high power load chip, including medium base
Piece, the upper surface of the dielectric substrate are provided with the first metal tape line, the second metal tape line and rectangular thin film resistive layer,
Thin film resistive layer is arranged between the first metal tape line and the second metal tape line, and respectively with the first metal tape line and the second metal
Band line is electrically connected；The lower surface of the dielectric substrate is provided with metal layer, and dielectric substrate is internally provided with multiple for connecting gold
Belong to the metallization VIA of layer and the second metal tape line, the metallization VIA includes metallic region and areas of dielectric, the metal
The circumferentially-spaced arrangement of region and the areas of dielectric along the metallization VIA.
As a kind of preferred embodiment of the present invention, the metallic region and the areas of dielectric are to meet metallization
The sheet rectangle of the radian of via.
As a kind of preferred embodiment of the present invention, the vertical institute of axis of the metallic region and the areas of dielectric
State the upper and lower surface of dielectric substrate.
As a kind of preferred embodiment of the present invention, it is additionally provided on the second metal tape line and matches somebody with somebody with metallization VIA
The aperture of conjunction, the aperture on the second metal tape line are connected with the metallization VIA.
As a kind of preferred embodiment of the present invention, aperture and the metallization VIA on the second metal tape line
Number is identical and corresponds.
As a kind of preferred embodiment of the present invention, aperture and the metallization VIA on the second metal tape line
Diameter is equal.
As a kind of preferred embodiment of the present invention, the number of the metallization VIA is 1.
As a kind of preferred embodiment of the present invention, the high power load chip further includes access interface, described
Access interface is connected with the first metal tape line.
As a kind of preferred embodiment of the present invention, there are first between the first metal tape line and thin film resistive layer
Overlapping region, and the first metal tape line is electrically connected with thin film resistive layer by the realization of the first overlapping region.
As a kind of preferred embodiment of the present invention, there are second between the second metal tape line and thin film resistive layer
Overlapping region, and the second metal tape line is electrically connected with thin film resistive layer by the realization of the first overlapping region.
Compared with prior art, beneficial effects of the present invention are as follows：The thin film resistive layer of high power load chip of the present invention
It can ensure its good tolerance power under the premise of high power load chip matching impedance is fixed, and inside dielectric substrate
Metallization VIA is provided with, metallization VIA has spaced apart metallic region and areas of dielectric, reduces equivalent inductance pair
In the buffer action of high-frequency signal.
Description of the drawings
Fig. 1 is the dimensional structure diagram of high power load chip of the present invention；
Fig. 2 is the top view of high power load chip of the present invention；
Fig. 3 is the thin film resistive layer of high power load chip of the present invention and the company of the first metal tape line and the second metal tape line
Connect schematic diagram；
Fig. 4 is the sectional view of high power load chip of the present invention.
In figure, 1- dielectric substrates, 2- the first metal tape lines, 3- thin film resistive layers, 4- the second metal tape lines, 5- metallized
Hole, 6- apertures, the first overlapping regions of 7-, the second overlapping regions of 8-, 51- metallic regions, 52- areas of dielectric.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work
Embodiment belongs to the scope of protection of the invention.
As shown in Figs. 1-2, a kind of high power load chip based on single metal via, it is described including dielectric substrate 1
The upper surface of dielectric substrate 1 be provided with the first metal tape line 2, the second metal tape line 4 and rectangular thin film resistive layer 3, it is thin
Film resistive layer 3 is arranged between the first metal tape line 2 and the second metal tape line 4, and respectively with the first metal tape line 2 and the second gold medal
Belong to band line 4 to be electrically connected；The lower surface of the dielectric substrate 1 is provided with metal layer (conductive metal layer, such as copper, and metal layer covers
The entire lower surface of lid dielectric substrate 1), dielectric substrate 1 is internally provided with single for connecting metal layer and the second metal tape line 4
Metallization VIA 5.
An aperture 6 coordinated with metallization VIA 5 is also set up on the second metal tape line 4, on the second metal tape line 4
Aperture 6 connected with the metallization VIA 5.
Aperture 6 on the second metal tape line 4 is identical with described 5 numbers of metallization VIA and corresponds.
Aperture 6 on the second metal tape line 4 is equal with 5 diameter of metallization VIA.
The number of the metallization VIA 5 is alternatively multiple.
The high power load chip further includes access interface, and the access interface is connected with the first metal tape line 2.
As shown in figure 3, there are the first overlapping region 7 between the first metal tape line 2 and thin film resistive layer 3, and first
Metal tape line 2 is electrically connected with thin film resistive layer 3 by the realization of the first overlapping region 7.
There are the second overlapping region 8 between the second metal tape line 4 and thin film resistive layer 3, and the second metal tape line 2 with
Thin film resistive layer 3 is realized by the first overlapping region 8 and is electrically connected.
In embodiments herein, dielectric substrate 1 is made of AlN (aluminium nitride) medium, the first metal tape line 2 and second
The mode that high temperature evaporation may be employed in metal tape line 4 is attached to the upper surface of dielectric substrate 1, can also use the side of high temperature sputtering
Formula is attached to the upper surface of dielectric substrate 1；Thin film resistive layer can use the alloy pulps such as NiCr upper coated in dielectric substrate 1
Surface, and there are overlapping regions with the first metal tape line 2 and the second metal tape line 4；(in some embodiments, thin film resistive layer
Can also be attached to the upper surface of dielectric substrate 1 by the way of vapor deposition, and with the first metal tape line 2 and the second metal tape line 4
There are overlapping regions)；Due to the presence of overlapping region, local shedding can be avoided to generate an influence to supported chip work, carried
The reliability of high entire wideband high-power supported chip.
In normal work, the metal layer ground connection of 1 lower surface of dielectric substrate, the first metal tape line 2 is connected by access interface
Required target location is connected to, electric current passes sequentially through the first metal tape line 2, thin film resistive layer 3, the second metal tape line 4, metallization
Via 5 flows into the ground metal layer of 1 lower surface of dielectric substrate；
It is known that the power P of resistance R consumption passes through square directly proportional, i.e. 2 R of P=I of current effective value I with it.
Such as 50 Ω resistance by virtual value be 0.5A electric currents, the power of consumption is 50*0.52=12.5W, if passing through virtual value
For 0.4A electric currents, the power of consumption is 50*0.4 2=8W；
And the resistance value R=Rs* (L/W) of film resistor, Rs are sheet resistance, for same thin film resistive layer, to fix
Value, therefore film resistor resistance value is only related with its length-width ratio (L/W), it is unrelated with its absolute dimension size, and the area of film resistor
Bigger, the electric current that can be born is bigger, and tolerance power also increases therewith；So the structure based on the application, we only need
Ensure that 3 length-width ratio of thin film resistive layer is fixed, you can ensure that the resistance value of film resistor is fixed, so that wideband high-power loads core
The matching impedance of piece is fixed；Different sizes is designed for film resistor according to different situations simultaneously, you can so that high-power negative
The tolerance power for carrying chip is met the requirements.
In the present embodiment, the metallization VIA 5 be single metal via, the inner wall of the metallization VIA 5
Several metallic regions 51 and areas of dielectric 52 are specifically positioned apart from, between the metallic region 51 and the areas of dielectric 52
Every arrangement.
The metallic region 51 and the areas of dielectric 52 are the sheet rectangle for the radian for meeting metallization VIA 5.
And the upper and lower surface of the vertical dielectric substrate 1 of the axis of the metallic region 51 and the areas of dielectric 52.
The areas of dielectric 52 is consistent with the material of the dielectric substrate 1, is formed without additional process, can be in formation metal
Self-assembling formation during region 51.
During the work time, if only setting a metallization VIA 5, the metal between the second metal tape line 4 and metal layer
Equivalent inductance can be formed by changing via 5, so as to be had an impact to the ground connection of high-frequency signal, be unfavorable for the normal work of supported chip；
And in the application, the metallization VIA 5 inside dielectric substrate is arranged at intervals multiple metallic regions 51, and the metallic region 51 is used for
Metal layer and the second metal tape line 4 are connected, although metallization VIA 5 can still be formed in metal layer and the second metal tape line 4
Inductance is imitated, but since multiple metallic regions 51 connect metal layer and the second metal tape line 4 simultaneously, is equivalent to equivalent inductance parallel connection,
Inductance value between the two is reduced, so as to reduce buffer action of the equivalent inductance for high-frequency signal so that high-frequency signal
It can be still grounded by the supported chip of the application；So that supported chip can either apply and high frequency environment, can also apply
In low frequency environments.And the decrease of equivalent inductance, single metal via 5 can be both realized only by single metal via 5
The area for the second metal tape line 4 that corresponding aperture 6 occupies is smaller, can reduce the loss of the area to the second metal tape line 4,
It and then can be breakdown so as to be not easy so that load to avoid the capacity for reducing the equivalent capacity between the second metal tape line 4 and ground
Use of the chip under high frequency environment is more stablized.
Finally it should be noted that：The foregoing is only a preferred embodiment of the present invention, is not intended to limit the invention,
Although the present invention is described in detail with reference to the foregoing embodiments, for those skilled in the art, still may be used
To modify to the technical solution recorded in foregoing embodiments or carry out equivalent substitution to which part technical characteristic.
Within the spirit and principles of the invention, any modifications, equivalent replacements and improvements are made should be included in the present invention's
Within protection domain.
Claims (10)
1. a kind of high power load chip, including dielectric substrate (1), the upper surface of the dielectric substrate (1) is provided with
One metal tape line (2), the second metal tape line (4) and rectangular thin film resistive layer (3), thin film resistive layer (3) are arranged at first
Between metal tape line (2) and the second metal tape line (4), and it is electrically connected respectively with the first metal tape line (2) and the second metal tape line (4)
It connects；The lower surface of the dielectric substrate (1) is provided with metal layer, and dielectric substrate (1) is internally provided with multiple for connecting metal
The metallization VIA (5) of layer and the second metal tape line (4), it is characterised in that：The metallization VIA (5) includes metallic region
(51) and areas of dielectric (52), the week of the metallic region (51) and the areas of dielectric (52) along the metallization VIA (5)
To being intervally arranged.
2. high power load chip according to claim 1, it is characterised in that：The metallic region (51) and the medium
Region (52) is the sheet rectangle for the radian for meeting metallization VIA (5).
3. high power load chip according to claim 2, it is characterised in that：The metallic region (51) and the medium
The upper and lower surface of the vertical dielectric substrate (1) of the axis in region (52).
4. high power load chip according to claim 3, it is characterised in that：It is also set on the second metal tape line (4)
The aperture (6) with metallization VIA (5) cooperation is equipped with, aperture (6) and the metallization VIA on the second metal tape line (4)
(5) connect.
5. high power load chip according to claim 4, it is characterised in that：It is small on the second metal tape line (4)
Hole (6) is identical with the metallization VIA (5) number and corresponds.
6. high power load chip according to claim 5, it is characterised in that：It is small on the second metal tape line (4)
Hole (6) is equal with the metallization VIA (5) diameter.
7. high power load chip according to claim 6, it is characterised in that：The number of the metallization VIA (5) is
1。
8. high power load chip according to claim 1, it is characterised in that：The high power load chip further includes
Access interface, the access interface are connected with the first metal tape line (2).
9. high power load chip according to claim 1, it is characterised in that：The first metal tape line (2) and film
There are the first overlapping region (7) between resistive layer (3), and the first metal tape line (2) and thin film resistive layer (3) are overlapping by first
Realize electrical connection in region (7).
10. high power load chip according to claim 1, it is characterised in that：The second metal tape line (4) and film
There are the second overlapping region (8) between resistive layer (3), and the second metal tape line (2) and thin film resistive layer (3) are overlapping by first
Realize electrical connection in region (8).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711413526.2A CN108091625A (en) | 2017-12-24 | 2017-12-24 | High power load chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711413526.2A CN108091625A (en) | 2017-12-24 | 2017-12-24 | High power load chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108091625A true CN108091625A (en) | 2018-05-29 |
Family
ID=62177737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711413526.2A Pending CN108091625A (en) | 2017-12-24 | 2017-12-24 | High power load chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108091625A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002064256A (en) * | 2000-08-22 | 2002-02-28 | Ngk Spark Plug Co Ltd | Wiring board |
| CN206413253U (en) * | 2017-02-09 | 2017-08-15 | 成都泰格微电子研究所有限责任公司 | A kind of wideband high-power supported chip |
| CN206451801U (en) * | 2017-02-09 | 2017-08-29 | 成都泰格微电子研究所有限责任公司 | A kind of wideband high-power supported chip of high frequency |
| CN206451699U (en) * | 2017-02-09 | 2017-08-29 | 成都泰格微电子研究所有限责任公司 | A kind of high power load chip based on multiple metallization vias |
-
2017
- 2017-12-24 CN CN201711413526.2A patent/CN108091625A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002064256A (en) * | 2000-08-22 | 2002-02-28 | Ngk Spark Plug Co Ltd | Wiring board |
| CN206413253U (en) * | 2017-02-09 | 2017-08-15 | 成都泰格微电子研究所有限责任公司 | A kind of wideband high-power supported chip |
| CN206451801U (en) * | 2017-02-09 | 2017-08-29 | 成都泰格微电子研究所有限责任公司 | A kind of wideband high-power supported chip of high frequency |
| CN206451699U (en) * | 2017-02-09 | 2017-08-29 | 成都泰格微电子研究所有限责任公司 | A kind of high power load chip based on multiple metallization vias |
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Application publication date: 20180529 |
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