CN108091363B - Bit line address selection circuit and nonvolatile memory comprising same - Google Patents
Bit line address selection circuit and nonvolatile memory comprising same Download PDFInfo
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- CN108091363B CN108091363B CN201611040792.0A CN201611040792A CN108091363B CN 108091363 B CN108091363 B CN 108091363B CN 201611040792 A CN201611040792 A CN 201611040792A CN 108091363 B CN108091363 B CN 108091363B
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Abstract
The invention provides a bit line address selection circuit and a nonvolatile memory comprising the same, wherein the bit line address selection circuit comprises a comparison amplifier, a first group of bit line address selectors and a second group of bit line address selectors, the first group of bit line address selectors are connected with a first memory bank of the nonvolatile memory, the second group of bit line address selectors are connected with a second memory bank of the nonvolatile memory, each group of bit line address selectors respectively comprises two bit line address selectors, the input end of one of the two bit line address selectors is connected with the non-inverting input end of the comparison amplifier, and the input end of the other of the two bit line address selectors is connected with the inverting input end of the comparison amplifier. The bit line address selection circuit cancels the selection stage of a Bank and preferably selects the circuit; and the time for selecting the Bank stage is saved, and the bit line precharging speed is obviously improved.
Description
Technical Field
The invention relates to the field of memories, in particular to a bit line address selection circuit and a nonvolatile memory comprising the same.
Background
High speed Flash is now becoming the direction of consumer demand. Data read time of a non-volatile memory (NVM) such as Flash is generally composed of four parts: address decoding, bit line pre-charging, cell (bit cell) current signal amplification, data comparison and output. The proportion of the time for address decoding and data comparison and output to the whole reading time is small, the time for amplifying the cell current signal is greatly influenced by the process, and the space for optimization is limited. Therefore, in the data reading time of the high-speed Flash, it is important to optimize the bit line precharging speed.
In the design of the high-speed Flash at present, a design method of a double Bank (memory Bank) is generally adopted, when the address of one Bank is read, the other Bank is used as a reference memory Bank, and the design method is a design method for effectively offsetting noise interference.
In this dual Bank based design, YMUX (bit line address selector) is a multi-level design, requiring one level dedicated to select which Bank is active, and the more levels of YMUX, the slower the bit line precharge speed. Generally, the time taken for precharging the bit lines is about 1/3-1/2 of the total data reading time.
Therefore, in order to solve the above problems, it is necessary to provide a novel bit line address selection circuit and a nonvolatile memory including the same, so as to improve the data reading speed.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to overcome the problems existing at present, the invention provides a bit line address selection circuit for a nonvolatile memory with dual banks, comprising a comparison amplifier, and further comprising at least a first group of bit line address selectors and at least a second group of bit line address selectors, the first group of bit line address selectors being connected with a first bank of the nonvolatile memory, the second group of bit line address selectors being connected with a second bank of the nonvolatile memory,
each group of bit line address selectors respectively comprises two bit line address selectors, the input end of one of the two bit line address selectors is connected with the non-inverting input end of the comparison amplifier, and the input end of the other of the two bit line address selectors is connected with the inverting input end of the comparison amplifier.
Further, the first set of bit line address selectors includes a first bit line address selector and a second bit line address selector, the second set of bit line address selectors includes a third bit line address selector and a fourth bit line address selector,
wherein the first bit line address selector and the fourth bit line address selector are connected to a non-inverting input terminal of the comparison amplifier, the second bit line address selector and the third bit line address selector are connected to an inverting input terminal of the comparison amplifier,
the first bit line address selector and the third bit line address selector are connected with a first enabling signal, and the second bit line address selector and the fourth bit line address selector are connected with a second enabling signal.
Further, one of the first enable signal and the second enable signal is asserted.
Further, when the first enable signal is active, the second bank is inactive while the first bank is active; when the second enable signal is active, the first memory bank is inactive while the second memory bank is active.
Further, the bit line address selection circuit further comprises a bit line precharge module, wherein the first bit line address selector, the second bit line address selector, the third bit line address selector and the fourth bit line address selector are all connected to the bit line precharge module.
Further, the non-inverting input terminal of the comparison amplifier is connected to the reference current signal.
Further, the bit line address selection circuit further comprises a buffer, and an input end of the buffer is connected to an output end of the comparison amplifier.
In one embodiment of the present invention, the first bit line address selector includes a first PMOS transistor, the second bit line address selector includes a second PMOS transistor, the third bit line address selector includes a third PMOS transistor, and the fourth bit line address selector includes a fourth PMOS transistor, wherein:
the source electrode of the first PMOS tube is connected with the non-inverting input end of the comparison amplifier, the source electrode of the second PMOS tube is connected with the inverting input end of the comparison amplifier, the grid electrodes of the first PMOS tube and the second PMOS tube are respectively connected with the first enabling signal and the second enabling signal, and the drain electrodes are both connected with the first storage body;
the source electrode of the third PMOS tube is connected with the inverting input end of the comparison amplifier, the source electrode of the fourth PMOS tube is connected with the non-inverting input end of the comparison amplifier, the grid electrodes of the third PMOS tube and the fourth PMOS tube are respectively connected with the first enabling signal and the second enabling signal, and the drain electrodes are connected with the second storage body.
Furthermore, the source electrodes of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor are all connected to the bit line precharge module.
According to another aspect of the present invention, there is also provided a nonvolatile memory having dual banks, which includes the bit line address selection circuit as one of the above.
The bit line address selection circuit cancels the selection level of a Bank in a bit line address selector YMUX, and completes the function of the prior two-level serial connection by a bit line address decoding selection level, and preferably selects the circuit; and the time for selecting the Bank stage is saved, and the bit line precharging speed is obviously improved.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIG. 1 shows a schematic circuit diagram of a bit line address selection circuit for a present non-volatile memory;
FIG. 2 is a schematic diagram showing the operation of the bit line address selection circuit of FIG. 1 when Bank A is active;
FIG. 3 is a schematic diagram showing the operation of the bit line address selection circuit of FIG. 1 when Bank B is active;
FIG. 4 shows a schematic circuit diagram of a bit line address selection circuit for a non-volatile memory according to one embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating the operation of the bit line address selection circuit of FIG. 4 when Bank A is active; and
fig. 6 is a schematic diagram illustrating the operation of the bit line address selection circuit of fig. 4 when Bank B is active.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
For a better understanding of the present invention, a brief description of the multi-level design of the conventional bit line address selector YMUX is provided below in conjunction with fig. 1.
Fig. 1 shows a schematic circuit configuration diagram of a bit line address selection circuit for a current nonvolatile memory, in which a bit line address selector YMUX is of a multi-stage design including one stage dedicated to select which Bank of a double Bank (memory Bank) is active and at least one stage for selecting a bit line. In fig. 1, it is only schematically shown that the bit line address selector YMUX includes a stage I for selecting which Bank in the double Bank is active, and a stage II for selecting the bit line.
Specifically, the stage I includes four PMOS transistors, M11, M12, M13 and M14, wherein the sources of M11, M12, M13 and M14 are connected to a bitline precharge module, and the input terminal of the bitline precharge module inputs a precharge signal (shown as PCHEN in fig. 1); the sources of M11 and M13 are connected to the non-inverting input of the comparison amplifier SA, the sources of M12 and M14 are connected to the inverting input of the comparison amplifier SA, the non-inverting input of the comparison amplifier SA is connected to a reference current (shown as Iref in fig. 1); the gates of M11 and M14 are connected to the enable signal Enb _ A of Bank A, and the gates of M12 and M13 are connected to the enable signal Enb _ B of Bank B.
Stage II includes two PMOS transistors, M15 and M16 respectively. The drains of M11 and M12 are connected to the source of M15, the drains of M13 and M14 are connected to the source of M16, the gates of M15 and M16 are connected to the bit line select enable signal Enb _ addr, the drain of M15 is connected to Bank A, and the drain of M16 is connected to Bank B.
Fig. 2 shows a schematic diagram of the operation of the bit line address selection circuit of fig. 1 when Bank a is active. As shown in fig. 2, when the enable signal Enb _ a is at a low level (e.g., ground), the enable signal Enb _ B is at a high level (e.g., 1.8V), and the bit line select enable signal Enb _ addr is at a low level (e.g., ground), M11, M14, M15, and M16 are turned on, M12 and M13 are turned off, and Bank a is active.
Fig. 3 shows a schematic diagram of the operation of the bit line address selection circuit of fig. 1 when Bank B is active. As shown in fig. 3, when the enable signal Enb _ a is at a high level (e.g., 1.8V), the enable signal Enb _ B is at a low level (e.g., ground voltage), and the bit line select enable signal Enb _ addr is at a low level (e.g., ground voltage), M12, M13, M15, and M16 are turned on, M11 and M14 are turned off, and Bank B is enabled.
That is, when the bit line select enable signal Enb _ addr is at a low level, Bank a is valid if the enable signal of Bank a is at a low level and the enable signal of Bank B is at a high level; bank B is active if the enable signal to Bank B is low and the enable signal to Bank a is high.
Therefore, as the source voltage of the PMOS transistor is at least higher than the turn-on voltage Vtpmos, the PMOS transistor is turned on, so that the bit line can be effectively precharged only after the bit line address selector YMUX is turned on in the process of precharging the bit line, thereby restricting the speed of precharging the bit line.
In order to solve the above problem, the present invention provides a bit line address selection circuit for a non-volatile memory, comprising a comparison amplifier, and further comprising a first group of bit line address selectors and a second group of bit line address selectors, wherein the first group of bit line address selectors are connected to a first bank of the non-volatile memory, the second group of bit line address selectors are connected to a second bank of the non-volatile memory, each group of bit line address selectors respectively comprises two bit line address selectors, an input terminal of one of the two bit line address selectors is connected to a non-inverting input terminal of the comparison amplifier, and an input terminal of the other of the two bit line address selectors is connected to an inverting input terminal of the comparison amplifier.
Specifically, the first group of bit line address selectors includes a first bit line address selector and a second bit line address selector, the second group of bit line address selectors includes a third bit line address selector and a fourth bit line address selector,
wherein the first bit line address selector and the fourth bit line address selector are connected with the non-inverting input terminal of the comparison amplifier, the second bit line address selector and the third bit line address selector are connected with the inverting input terminal of the comparison amplifier,
the first bit line address selector and the third bit line address selector are connected with a first enabling signal, and the second bit line address selector and the fourth bit line address selector are connected with a second enabling signal.
Further, the first set of bit line address selectors includes a first bit line address selector and a second bit line address selector, the second set of bit line address selectors includes a third bit line address selector and a fourth bit line address selector,
wherein the first bit line address selector and the fourth bit line address selector are connected to a non-inverting input terminal of the comparison amplifier, the second bit line address selector and the third bit line address selector are connected to an inverting input terminal of the comparison amplifier,
the first bit line address selector and the third bit line address selector are connected with a first enabling signal, and the second bit line address selector and the fourth bit line address selector are connected with a second enabling signal.
In the above bit line address selection circuit, one of the first enable signal and the second enable signal is asserted. And when the first enable signal is active, the first memory bank is active, and the second memory bank is inactive; when the second enable signal is active, the first memory bank is inactive while the second memory bank is active.
The bit line address selection circuit of the invention cancels the selection level of Bank in the traditional YMUX, only reserves at least one address decoding selection level MUX (data selector) of the bit line, simplifies the level number of the YMUX and improves the bit line pre-charging speed.
Fig. 4 shows a schematic circuit diagram of a bit line address selection circuit for a non-volatile memory having two banks (banks) according to one embodiment of the present invention. In this embodiment, the bit line address selector in the bit line address selection circuit is shown as a PMOS transistor, but it should be understood that the bit line address selector as a transmission gate may be implemented by various elements, such as a PMOS transistor, an NMOS transistor, a CMOS transistor, and the like. When the bit line address selector is implemented using different elements, the active level of the enable signal is different accordingly. For example, when a PMOS transistor is used, the enable signal is active at a low level; when an NMOS transistor is used, the enable signal is active at a high level. The embodiments of the present invention are exemplary only, and are not intended to be limiting but rather are intended to encompass the broadest scope of the concept according to the present invention.
As shown in FIG. 4, taking PMOS transistors as the bit line address selector, the bit line address selection circuit 400 includes a comparison amplifier 410, a bit line precharge module 420 and four PMOS transistors M41, M42, M43 and M44. Wherein, the source of M41 is connected to the non-inverting input terminal of the comparison amplifier 410 (the input signal thereof is shown as SAP in fig. 4), the gate is connected to the enable signal Enb _ a of Bank a, the source of M42 is connected to the inverting input terminal of the comparison amplifier 410 (the input signal thereof is shown as SAN in fig. 4), and the gates are connected to the enable signal Enb _ B of Bank B, and the drains of M41 and M42 are connected to Bank a; the source of M43 is connected to the inverting input terminal of the comparison amplifier 410, the gate is connected to the enable signal Enb _ A of Bank A, the source of M44 is connected to the non-inverting input terminal of the comparison amplifier 410, and the drains of the enable signals Enb _ B of Bank B, M43 and M44 are connected to Bank B.
Further, the sources of M41, M42, M43, and M44 are all connected to the bit line precharge module 420, the non-inverting input and the inverting input of the comparison amplifier 410 are also connected to the bit line precharge module 420, the input of the bit line precharge module 420 is connected to the precharge control signal (shown as PCHEN in fig. 4), and the non-inverting input of the comparison amplifier 410 is connected to the reference current (shown as Iref in fig. 4).
In one embodiment, the bit line address selection circuit 400 further comprises a buffer 430, an input of the buffer 430 is connected to the output of the comparison amplifier 410 for receiving the amplified current signal from the comparison amplifier 410, and an output of the buffer 430 is connected to other circuits of the non-volatile memory for outputting signals to the other circuits.
FIG. 5 is a schematic diagram illustrating the operation of the bit line address selection circuit of FIG. 4 when Bank A is active. As shown in fig. 5, when the enable signal Enb _ a of Bank a is low (e.g., ground voltage) and the enable signal Enb _ B of Bank B is high (e.g., 1.8V), M41 and M43 are turned on, M42 and M44 are turned off, Bank a is enabled, and Bank B is disabled.
Fig. 6 is a schematic diagram illustrating the operation of the bit line address selection circuit of fig. 4 when Bank B is active. As shown in fig. 6, when the enable signal Enb _ B of Bank B is low (e.g., ground voltage) and the enable signal Enb _ a of Bank a is high (e.g., 1.8V), M42 and M44 are turned on, M41 and M43 are turned off, Bank B is enabled, and Bank a is disabled.
Therefore, when the input signals SAP and SAN are applied to the source of the PMOS transistor, the bit line address selection circuit of the invention cancels the selection stage of the Bank in the bit line address selector YMUX, and the input signals directly act on the bit line address decoding selection stage MUX, thereby saving the action time from the beginning of applying the signals to the Bank selection stage.
Wherein each Bank contains two bit line address selectors YMUX, which are in parallel, one of which is connected to the non-inverting input of the comparison amplifier 410 and the other of which is connected to the inverting input of the comparison amplifier 410 (e.g., Bank a contains M41 and M42, M41 is connected to the non-inverting input of the comparison amplifier 410, M42 is connected to the inverting input of the comparison amplifier 410; Bank B contains M43 and M44, M44 is connected to the non-inverting input of the comparison amplifier 410, M43 is connected to the inverting input of the comparison amplifier 410), only one of which is active at a time. When Bank is selected, one of its two YMUXs for connection to the non-inverting input of the comparison amplifier is active, the other is off; when Bank is not selected, one of its two YMUXs for connection to the inverting input of the compare amplifier is active and the other is off, thereby achieving that only one is active at a time.
The invention has the beneficial effects that:
compared with the traditional bit line address selection circuit, the bit line address selection circuit cancels the selection level of a Bank in the bit line address selector YMUX, and the bit line address decoding selection level completes the original function of completing two-level series connection, thus the circuit is optimized; and the time for selecting the Bank stage is saved, and the bit line precharging speed is obviously improved.
According to another embodiment of the present invention, a nonvolatile memory is provided, which includes an address decoding circuit, a bit current signal amplifying circuit, a data comparing and outputting circuit, and a bit line precharging circuit. The bit line precharge circuit includes the bit line precharge circuit in the above embodiment, and the specific structure thereof is referred to the above embodiment and is not described herein again.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A bit line address selection circuit for a non-volatile memory having at least two banks, comprising a comparison amplifier, characterized in that it further comprises at least a first set of bit line address selectors directly connected to a first bank of the non-volatile memory and at least a second set of bit line address selectors directly connected to a second bank of the non-volatile memory,
each group of bit line address selectors respectively comprises two bit line address selectors, the input end of one of the two bit line address selectors is connected with the non-inverting input end of the comparison amplifier, and the input end of the other of the two bit line address selectors is connected with the inverting input end of the comparison amplifier.
2. The bit line address selection circuit of claim 1, wherein the first set of bit line address selectors comprises a first bit line address selector and a second bit line address selector, the second set of bit line address selectors comprises a third bit line address selector and a fourth bit line address selector,
wherein the first bit line address selector and the fourth bit line address selector are connected to a non-inverting input terminal of the comparison amplifier, the second bit line address selector and the third bit line address selector are connected to an inverting input terminal of the comparison amplifier,
the first bit line address selector and the third bit line address selector are connected with a first enabling signal, and the second bit line address selector and the fourth bit line address selector are connected with a second enabling signal.
3. The bit line address selection circuit of claim 2, wherein one of the first enable signal and the second enable signal is asserted.
4. The bit line address selection circuit of claim 3, wherein the second bank is inactive while the first bank is active when the first enable signal is active; when the second enable signal is active, the first memory bank is inactive while the second memory bank is active.
5. The bit line address selection circuit of claim 2, further comprising a bit line precharge module, wherein the first, second, third and fourth bit line address selectors are coupled to the bit line precharge module.
6. The bit line address selection circuit of claim 1, wherein a non-inverting input of the comparison amplifier is connected to a reference current signal.
7. The bit line address selection circuit of claim 1, further comprising a buffer having an input coupled to the output of the compare amplifier.
8. The bit line address selection circuit of claim 5, wherein the first bit line address selector comprises a first PMOS transistor, the second bit line address selector comprises a second PMOS transistor, the third bit line address selector comprises a third PMOS transistor, and the fourth bit line address selector comprises a fourth PMOS transistor, wherein:
the source electrode of the first PMOS tube is connected with the non-inverting input end of the comparison amplifier, the source electrode of the second PMOS tube is connected with the inverting input end of the comparison amplifier, the grid electrodes of the first PMOS tube and the second PMOS tube are respectively connected with the first enabling signal and the second enabling signal, and the drain electrodes are both connected with the first storage body;
the source electrode of the third PMOS tube is connected with the inverting input end of the comparison amplifier, the source electrode of the fourth PMOS tube is connected with the non-inverting input end of the comparison amplifier, the grid electrodes of the third PMOS tube and the fourth PMOS tube are respectively connected with the first enabling signal and the second enabling signal, and the drain electrodes are connected with the second storage body.
9. The bit line address selection circuit of claim 8, wherein the sources of the first, second, third and fourth PMOS transistors are all connected to the bit line precharge module.
10. A non-volatile memory having at least two memory banks, comprising a bit line address selection circuit as claimed in any one of claims 1 to 9.
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