CN108075967B

CN108075967B - Link selection method and device

Info

Publication number: CN108075967B
Application number: CN201610991674.1A
Authority: CN
Inventors: 杨丰
Original assignee: Chengdu Huawei Technology Co Ltd
Current assignee: Chengdu Huawei Technology Co Ltd
Priority date: 2016-11-10
Filing date: 2016-11-10
Publication date: 2021-04-09
Anticipated expiration: 2036-11-10
Also published as: CN108075967A

Abstract

The invention discloses a link selection method, which is applied to a storage area network, wherein the storage area network comprises a Host and a storage array, N links are arranged between the Host and the storage array, and the method comprises the following steps: acquiring a bit error rate and optical power corresponding to N links, wherein the bit error rate and the optical power corresponding to any link I in the N links are carried in a first I/O request response returned to the Host by calculating the bit error rate and the optical power corresponding to the link I after the storage array receives the first I/O request issued by the Host on the link I; determining a priority balance value corresponding to the N links according to the bit error rate and the optical power corresponding to the N links; dividing the N links into priority equivalence classes according to the priority balance values corresponding to the N links; and selecting one link from the priority equivalence class with the highest priority equivalence class to send a second I/O request. The invention also provides a link selection device. The embodiment of the invention can improve the reliability of the link, thereby meeting the QoS requirement.

Description

Link selection method and device

Technical Field

The present invention relates to the field of electronic technologies, and in particular, to a link selection method and apparatus.

Background

In a Storage Area Network (SAN), a plurality of hosts, switches, and Storage arrays are generally included, and the plurality of hosts are connected to the Storage arrays through the switches. The health of the link between devices directly affects the reliability of the upper layer traffic. Link abnormity (such as too high bit error rate, too low optical power, etc.) can cause large I/O delay or long I/O return-to-zero time, which both seriously affect the reliability of service and even cause service interruption.

However, in the current host I/O routing algorithm, an error code is returned depending on I/O to perform I/O switching. Because the host cannot sense in time and can only return error code processing through I/O, Service interruption may be caused, and further link reliability is affected, and it is difficult to meet Quality of Service (QoS) requirements.

Disclosure of Invention

The embodiment of the invention provides a link selection method and a link selection device, which aim to improve the reliability of a link and further meet the QoS requirement.

In a first aspect, an embodiment of the present invention provides a link selection method, which is applied to a storage area network, where the storage area network includes a Host and a storage array, where the Host and the storage array include N links, the N links in an initial state are in a same priority equivalence class, and N is an integer greater than 1, and the method includes:

the Host acquires the error rate and the optical power corresponding to the N links, wherein the error rate and the optical power corresponding to any link I in the N links are carried in a first I/O request response returned to the Host, and the error rate and the optical power corresponding to the link I are calculated after the storage array receives the first I/O request issued by the Host on the link I; determining a priority balance value corresponding to the N links according to the bit error rate and the optical power corresponding to the N links; dividing a priority equivalence class for the N links according to the priority balance value corresponding to the N links; and selecting the link with the highest priority equivalence class to issue a second I/O request, thereby achieving the purpose of isolating the abnormal link in time and meeting the requirements of the reliability and the quality of service of the service.

In some possible embodiments, the specific implementation manner of determining, by the Host, the priority trade-off value corresponding to the N links according to the bit error rate and the optical power corresponding to the N links is as follows: the Host determines a first influence factor corresponding to the N links according to the bit error rate corresponding to the N links; determining a second influence factor corresponding to the N links according to the optical power corresponding to the N links; and determining a priority balancing value corresponding to the N links according to the first influence factor and the second influence factor corresponding to the N links.

In some possible embodiments, the specific implementation manner of determining, by the Host, the first impact factor corresponding to the N links according to the bit error rate corresponding to the N links is as follows: the Host determines a first influence factor corresponding to the N links according to the bit error rate corresponding to the N links and a first formula; wherein the first formula is: x is α × bit _ err _ rate, where α is a weight value, bit _ err _ rate is a bit error rate, and x is a first influence factor.

In some possible embodiments, the specific implementation manner of determining, by the Host, the second impact factor corresponding to the N links according to the optical power corresponding to the N links is as follows: the Host determines a second influence factor corresponding to the N links according to the optical power corresponding to the N links and a second formula; wherein the second formula is: and y is alpha, optical _ power, wherein alpha is a weight value, optical _ power is optical power, and y is a second influence factor.

In some possible embodiments, the specific implementation manner of determining, by the Host, the priority tradeoff value corresponding to the N links according to the first impact factor and the second impact factor corresponding to the N links is as follows: the Host determines a priority balancing value corresponding to the N links according to the first influence factor, the second influence factor and a third formula corresponding to the N links; wherein the third formula is: and path _ pro _ weight ═ β ((1/x) + (1/y)), where path _ pro _ weight is a link priority weighting value and β is a weighting value.

In some possible embodiments, the specific implementation manner of the Host dividing the priority equivalence class for the N links according to the priority balance value corresponding to the N links is as follows: and the Host divides the priority equivalence classes for the N links according to the priority balance values and the equivalence class thresholds corresponding to the N links, wherein the difference of the priority balance values of any two links in the same priority equivalence class is less than or equal to the equivalence class threshold.

In a second aspect, an embodiment of the present invention provides a link selecting apparatus, including means for performing the method in the first aspect.

In a third aspect, the present invention provides a link selection apparatus, where the link selection apparatus includes a processor, and the processor is configured to support the link selection apparatus to execute a corresponding function in the link selection method provided in the first aspect. The link selection device may also include a memory, coupled to the processor, that stores program instructions and data necessary for the link selection device. The link selection apparatus may further include a communication interface for the link selection apparatus to communicate with other devices or a communication network.

In a fourth aspect, the present invention provides a computer storage medium for storing computer software instructions for a link selection apparatus provided in the third aspect, which includes a program designed to execute the above aspects.

These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic diagram of a communication system according to an embodiment of the present invention;

fig. 2 is a schematic flow chart of a link selection method according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a bit error rate statistics and feedback according to an embodiment of the present invention;

fig. 4 is a schematic diagram of an optical power statistics and feedback according to an embodiment of the present invention;

fig. 5 is a schematic diagram illustrating a link priority class division according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a link selecting apparatus according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a link selecting apparatus according to an embodiment of the present invention.

Detailed Description

In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The following are detailed below.

The terms "first," "second," "third," and "fourth," etc. in the description and claims of the invention and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

Hereinafter, some terms in the present application are explained to facilitate understanding by those skilled in the art.

1) The link selection device according to the embodiment of the present invention is a Host (Host), where the Host refers to a terminal device that can access other machines in a network, and the Host may be a computer, a server, a workstation, or the like.

2) Storage array (Storage) refers to a collection of disks or tapes from one or more commonly accessible Storage subsystems, collectively managed by control software.

3) A Switch (Switch) is a device that performs an information exchange function in a communication system according to the need of information transmission at both ends of the communication.

4) The bit error rate is the percentage of the number of error bits to the total number of bits in data transmission, and is an index for measuring the data transmission accuracy in a specified time.

5) Optical power is the work performed by light in units of time, and is often expressed in units of milliwatts (mw) and decibel milliwatts (dbm).

6) "plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

Embodiments of the present application are described below with reference to the drawings.

Referring to fig. 1, fig. 1 is a schematic diagram of a communication system according to an embodiment of the present invention. The communication system shown in fig. 1 includes a plurality of hosts (Host), a plurality of switches (Switch), and a Storage array (Storage), wherein there are N links between one Host and one Storage array due to the presence of the switches in the middle, and the N links in the initial state are generally in the same priority equivalence class, where N is an integer greater than 1. The following description is given by taking a Host to a storage array as an example, wherein the Host acquires the bit error rate and the optical power corresponding to N links of the Host, and the bit error rate and the optical power corresponding to any link I in the N links are carried in a first I/O request response returned to the Host, which is calculated by the storage array after the storage array receives a first I/O request issued by the Host on the link I; determining a priority balance value corresponding to the N links by the Host according to the bit error rate and the optical power corresponding to the N links; the Host divides the priority equivalence classes for the N links according to the priority balance values corresponding to the N links; and finally, selecting the link with the highest priority equivalence class by the Host to send a second I/O request. Therefore, in a Storage Area Network (SAN), when multiple hosts access the same Storage array at the same time, by the scheme, abnormal links with too high error rate or too low optical power can be isolated in time, so that the problems of large service I/O delay and long I/O zeroing time are solved, the reliability requirement can be met, and the QoS can be fully ensured.

Referring to fig. 2, fig. 2 is a schematic flow chart of a link selection method provided by an embodiment of the present invention, and is applied to a storage area network, where the storage area network includes a Host and a storage array, where the Host and the storage array include N links, the N links in an initial state are in the same priority equivalence class, and N is an integer greater than 1, and the method includes the following steps:

s201, the Host obtains the error rate and the optical power corresponding to the N links, wherein the error rate and the optical power corresponding to any link I in the N links are carried in a first I/O request response returned to the Host, and the error rate and the optical power corresponding to the link I are calculated after the storage array receives the first I/O request issued by the Host on the link I.

S202, the Host determines a priority balance value corresponding to the N links according to the bit error rate and the optical power corresponding to the N links.

And S203, the Host divides the priority equivalence classes for the N links according to the priority balance values corresponding to the N links.

And S204, the Host selects the link with the highest priority equivalence class to send a second I/O request.

It should be noted that there may be multiple links in the highest priority equivalence class, and the step of selecting the link with the highest priority equivalence class to issue the second I/O request may select any one link in the highest priority equivalence class to issue the second I/O request, or select the link with the highest priority in the highest priority equivalence class to issue the second I/O request, which is not limited in the present invention.

For example, assuming that N is 3, the links from the Host to the storage array include a link 1, a link 2 and a link 3, where the 3 links in the initial state are in the same priority equivalence class, and since the priorities of the 3 links are the same, the Host initially issues I/O requests to the storage array in the 3 links, after the storage array receives the I/O requests, the storage array calculates the bit error rate and optical power corresponding to the current link, and carries the calculated bit error rate and optical power corresponding to the current link in the I/O request response returned to the Host, after receiving the I/O request response returned by the storage array, the Host determines the priority balance value corresponding to the 3 links according to the bit error rate and optical power corresponding to the 3 links, and then divides the priority equivalence class for the 3 links according to the priority balance value corresponding to the 3 links, then, the link with the highest priority equivalence class is selected from the 3 links to send another I/O request (for example, the priority equivalence class of the link 3 is higher than the priority equivalence classes of the link 2 and the link 1), and then, the Host continuously updates the priority equivalence classes of the 3 links and the abnormal link with overhigh time isolation error rate or overhigh light power, thereby avoiding the problems of large service I/O delay and long I/O zeroing time, meeting the reliability requirement and fully ensuring the QoS.

It should be noted that, after the link with the highest priority equivalence class is selected to issue the second I/O request, since only the I/O request is issued in the link with the highest priority equivalence class, the bit error rate and the optical power continuously fed back by the storage array are only of the link with the highest priority equivalence class, at this time, the Host evaluates the quality of the N links based on the bit error rate and the optical power corresponding to the N links, and the bit error rate and the optical power corresponding to the N-1 links except the link with the highest priority equivalence class in the N links are the bit error rate and the optical power before use, that is, the priority balance value calculated before the priority balance value corresponding to the N-1 link.

For example, as shown in fig. 3 and fig. 4, fig. 3 is a schematic diagram of an error rate statistics and feedback provided by the embodiment of the present invention, and fig. 4 is a schematic diagram of an optical power statistics and feedback provided by the embodiment of the present invention, wherein in fig. 3 and fig. 4, the Number of controllers of the storage array is the same as the Number of bus adapters (HBAs) of the Host, and different hosts are divided by Logical Unit Numbers (LUNs). Vdrop refers to the disk array space of the Host for representing the different devices of Host. In fig. 3, the bit error rate is continuously counted by a bit error rate counting Module (BER Statistics Module, BSM) for the bit error rate of all links of the Host, the time of the continuous counting is represented by I _ T Session, then the storage array sends the counted bit error rate to the Host in I/O through links PATH1 and PATH2, and then the Host reads the bit error rate from the I/O. In fig. 4, the bit error rate is continuously counted by an Optical Power Statistics Module (OPSM) for the Optical Power of all links of the Host, the time of the continuous counting is represented by I _ T Session, then the storage array puts the counted Optical Power in I/O to the Host through the links PATH1 and PATH2, and then the Host reads the Optical Power from the I/O.

The I/O issued by the Host to the storage array may be a service I/O, or a private I/O issued when reporting the LUN, and the like.

Optionally, in step S202, the specific implementation of determining, by the Host according to the bit error rate and the optical power corresponding to the N links, the priority trade-off value corresponding to the N links is as follows: the Host determines a first influence factor corresponding to the N links according to the bit error rate corresponding to the N links; determining a second influence factor corresponding to the N links according to the optical power corresponding to the N links; and determining a priority balancing value corresponding to the N links according to the first influence factor and the second influence factor corresponding to the N links.

Optionally, the specific implementation manner of determining, by the Host, the first impact factor corresponding to the N links according to the bit error rate corresponding to the N links is as follows: the Host determines a first influence factor corresponding to the N links according to the bit error rate corresponding to the N links and a first formula; wherein the first formula is: x is α × bit _ err _ rate, where α is a weight value, bit _ err _ rate is a bit error rate, and x is a first influence factor.

Optionally, the specific implementation manner of determining, by the Host, the second impact factor corresponding to the N links according to the optical power corresponding to the N links is as follows: the Host determines a second influence factor corresponding to the N links according to the optical power corresponding to the N links and a second formula; wherein the second formula is: and y is alpha, optical _ power, wherein alpha is a weight value, optical _ power is optical power, and y is a second influence factor.

Optionally, the specific implementation manner of determining, by the Host, the priority trade-off value corresponding to the N links according to the first influence factor and the second influence factor corresponding to the N links is as follows: the Host determines a priority balancing value corresponding to the N links according to the first influence factor, the second influence factor and a third formula corresponding to the N links, wherein the third formula is as follows: and path _ pro _ weight ═ β ((1/x) + (1/y)), where path _ pro _ weight is a link priority weighting value and β is a weighting value.

Optionally, the specific implementation manner of the Host dividing the priority equivalence classes for the N links according to the priority balancing values corresponding to the N links is as follows: and the Host divides the priority equivalence classes for the N links according to the priority balance values and the equivalence class thresholds corresponding to the N links, wherein the difference of the priority balance values of any two links in the same priority equivalence class is less than or equal to the equivalence class threshold.

The weight value α may be, for example, 0.5, 1, 2, 3, 4, 7 or other values.

The weight value β may be, for example, 0.5, 1, 2, 3, 4, 7 or other values.

The equivalence class threshold may be, for example, 0.5, 1, 2, 3, 4, 7, or other values.

For example, assume that the equivalence class threshold is 4, Host has 10 links, and 10 links have: link 1, link 2, link 3, link 4, link 5, link 6, link 7, link 8, link 9, link 10, the 10 corresponding link priority trade-off values are: 1. 3, 5, 6, 8, 10, 11, 12, 15, 16, then the priority classes corresponding to these 10 links are: priority equivalence class 1, priority equivalence class 2, priority equivalence class 3, priority equivalence class 4.

It should be noted that priority equivalence class 1 > priority equivalence class 2 > priority equivalence class 3 > priority equivalence class 4.

It can be seen that the priority equivalence class 1 has 3 links, and the Host may select any one of the 3 links to issue the second I/O request, or the Host selects the link with the smallest priority tradeoff value from the 3 links to issue the second I/O request, such as link 1, which is not limited in the present invention.

An embodiment of the present invention further provides a link selecting apparatus 600, as shown in fig. 6, which is applied to a storage area network, where the storage area network includes a Host and a storage array, where the Host and the storage array include N links, the N links in an initial state are in the same priority equivalence class, and N is an integer greater than 1, and includes:

a processing module 601, configured to obtain a bit error rate and an optical power corresponding to the N links, where the bit error rate and the optical power corresponding to any one link I in the N links are carried in a first I/O request response returned to the Host, and the bit error rate and the optical power corresponding to the link I are calculated after the storage array receives the first I/O request issued by the Host on the link I; determining a priority balance value corresponding to the N links according to the bit error rate and the optical power corresponding to the N links; determining a priority balance value corresponding to the N links according to the bit error rate and the optical power corresponding to the N links; and selecting the link with the highest priority equivalence class to send a second I/O request.

Optionally, the processing module 601 is specifically configured to:

determining a first influence factor corresponding to the N links according to the error rate corresponding to the N links;

determining a second influence factor corresponding to the N links according to the optical power corresponding to the N links;

and determining a priority balancing value corresponding to the N links according to the first influence factor and the second influence factor corresponding to the N links.

Optionally, the processing module 601 is specifically configured to:

determining a first influence factor corresponding to the N links according to the bit error rate corresponding to the N links and a first formula;

wherein the first formula is: x is α × bit _ err _ rate, where α is a weight value, bit _ err _ rate is a bit error rate, and x is a first influence factor.

Optionally, the processing module 601 is specifically configured to:

determining a second influence factor corresponding to the N links according to the optical power corresponding to the N links and a second formula;

wherein the second formula is: and y is alpha, optical _ power, wherein alpha is a weight value, optical _ power is optical power, and y is a second influence factor.

Optionally, the processing module 601 is specifically configured to:

determining a priority balancing value corresponding to the N links according to the first influence factor, the second influence factor and a third formula corresponding to the N links;

wherein the third formula is: and path _ pro _ weight ═ β ((1/x) + (1/y)), where path _ pro _ weight is a link priority weighting value and β is a weighting value.

Optionally, the processing module 601 is specifically configured to:

and dividing priority equivalence classes for the N links according to the priority balance values corresponding to the N links and equivalence class thresholds, wherein the difference value of the priority balance values of any two links in the same priority equivalence class is less than or equal to the equivalence class threshold.

It should be noted that the above modules (the processing module 601) are used for executing the relevant steps of the above method.

In the present embodiment, the link selecting apparatus 600 is presented in the form of a module. A "module" herein may refer to an application-specific integrated circuit (ASIC), a processor and memory that execute one or more software or firmware programs, an integrated logic circuit, and/or other devices that may provide the described functionality. Further, the above processing module 601 may be implemented by the processor 701 of the link selecting apparatus shown in fig. 7.

As shown in fig. 7, the link selecting apparatus 700 may be implemented in the structure of fig. 7, and the link selecting apparatus 700 includes at least one processor 701, at least one memory 702 and at least one communication interface 703. The processor 701, the memory 702 and the communication interface 703 are connected by the communication bus to complete communication therebetween.

The processor 701 may be a general purpose Central Processing Unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of programs according to the above schemes.

Communication interface 703 is used for communicating with other devices or communication Networks, such as ethernet, Radio Access Network (RAN), Wireless Local Area Networks (WLAN), etc.

The Memory 702 may be, but is not limited to, a Read-Only Memory (ROM) or other type of static storage device that can store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that can store information and instructions, an Electrically Erasable Programmable Read-Only Memory (EEPROM), a Compact Disc Read-Only Memory (CD-ROM) or other optical Disc storage, optical Disc storage (including Compact Disc, laser Disc, optical Disc, digital versatile Disc, blu-ray Disc, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. The memory may be self-contained and coupled to the processor via a bus. The memory may also be integral to the processor.

The memory 702 is used for storing application program codes for executing the above schemes, and the processor 701 controls the execution. The processor 701 is configured to execute application program code stored in the memory 702.

The code stored in the memory 702 may perform the above-mentioned link selection method performed by the terminal device provided above, for example, the link selection method is applied to a storage area network, where the storage area network includes a Host and a storage array, where the Host and the storage array include N links, and the N links in an initial state are in the same priority equivalence class, where N is an integer greater than 1; acquiring a bit error rate and an optical power corresponding to the N links, wherein the bit error rate and the optical power corresponding to any link I in the N links are carried in a first I/O request response returned to the Host, and are calculated after the storage array receives a first I/O request issued by the Host on the link I; determining a priority balance value corresponding to the N links according to the bit error rate and the optical power corresponding to the N links; dividing a priority equivalence class for the N links according to the priority balance value corresponding to the N links; and selecting the link with the highest priority equivalence class to send a second I/O request.

An embodiment of the present invention further provides a computer storage medium, where the computer storage medium may store a program, and when the program is executed, the program includes some or all of the steps of any one of the link selection methods described in the above method embodiments.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required by the invention.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.

The above embodiments of the present invention are described in detail, and the principle and the implementation of the present invention are explained by applying specific embodiments, and the above description of the embodiments is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in view of the above, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A link selection method is applied to a storage area network, the storage area network comprises a Host and a storage array, N links are included between the Host and the storage array, the N links in an initial state are in the same priority equivalence class, N is an integer greater than 1, and the method comprises the following steps:

the Host acquires the bit error rate and the optical power corresponding to the N links, wherein the bit error rate and the optical power corresponding to any link I in the N links are carried in a first I/O request response returned to the Host by the storage array after the storage array receives a first I/O request issued by the Host on the link I;

the Host determines a priority balance value corresponding to the N links according to the bit error rate and the optical power corresponding to the N links;

the Host divides a priority equivalence class for the N links according to the priority balance value corresponding to the N links;

the Host selects a link with the highest priority equivalence class to send a second I/O request;

the step of dividing the priority equivalence classes for the N links according to the priority balance values corresponding to the N links comprises the following steps: and the Host divides the priority equivalence classes for the N links according to the priority balance values and the equivalence class thresholds corresponding to the N links, wherein the difference of the priority balance values of any two links in the same priority equivalence class is less than or equal to the equivalence class threshold.

2. The method of claim 1, wherein the determining the priority tradeoff value for the N links according to the bit error rate and the optical power for the N links comprises:

3. The method according to claim 2, wherein the determining the first impact factor for the N links according to the bit error rate for the N links comprises:

4. The method according to claim 2, wherein the determining the second impact factors corresponding to the N links according to the optical powers corresponding to the N links includes:

5. The method of claim 2, wherein the determining the priority tradeoff value for the N-link according to the first impact factor and the second impact factor for the N-link comprises:

6. The method according to any one of claims 1-5, wherein said classifying the N links into priority equivalence classes according to the priority tradeoff values corresponding to the N links comprises:

7. A link selection device is applied to a storage area network, the storage area network comprises a Host and a storage array, N links are included between the Host and the storage array, the N links in an initial state are in the same priority equivalence class, N is an integer greater than 1, and the link selection device comprises:

the processing module is used for acquiring the bit error rate and the optical power corresponding to the N links, wherein the bit error rate and the optical power corresponding to any link I in the N links are carried in a first I/O request response returned to the Host by the storage array after the storage array receives a first I/O request issued by the Host on the link I; determining a priority balance value corresponding to the N links according to the bit error rate and the optical power corresponding to the N links; determining a priority balance value corresponding to the N links according to the bit error rate and the optical power corresponding to the N links; selecting a link with the highest priority equivalence class to send a second I/O request;

8. The apparatus of claim 7, wherein the processing module is specifically configured to:

9. The apparatus of claim 7, wherein the processing module is specifically configured to:

10. The apparatus of claim 7, wherein the processing module is specifically configured to:

11. The apparatus of claim 8, wherein the processing module is specifically configured to:

12. The apparatus according to any one of claims 7 to 11, wherein the processing module is specifically configured to:

13. A link selection device is applied to a storage area network, the storage area network includes a Host and a storage array, the Host and the storage array include N links, the N links in an initial state are in a same priority equivalence class, N is an integer greater than 1, the link selection device includes a processor, wherein:

the processor is configured to obtain a bit error rate and an optical power corresponding to the N links, where the bit error rate and the optical power corresponding to any one link I in the N links are carried in a first I/O request response returned to the Host, where the first I/O request response is calculated by the storage array after the storage array receives a first I/O request issued by the Host on the link I; determining a priority balance value corresponding to the N links according to the bit error rate and the optical power corresponding to the N links; dividing a priority equivalence class for the N links according to the priority balance value corresponding to the N links; selecting a link with the highest priority equivalence class to send a second I/O request;

14. The apparatus of claim 13, wherein the processor determines the priority tradeoff value for the N links according to the bit error rate and the optical power for the N links by:

15. The apparatus according to claim 14, wherein the specific implementation manner of the processor determining the first impact factor for the N links according to the bit error rate for the N links includes:

16. The apparatus of claim 14, wherein the specific implementation manner of the processor determining the second impact factors corresponding to the N links according to the optical powers corresponding to the N links is as follows:

17. The apparatus of claim 14, wherein the processor determines the priority tradeoff value for the N links according to the first and second impact factors for the N links by:

18. The apparatus according to any of claims 13-17, wherein the processor assigns the priority equivalence classes to the N links according to the priority tradeoff values corresponding to the N links by: