CN108074614B - Method and device for improving NOR type FLASH stability - Google Patents
Method and device for improving NOR type FLASH stability Download PDFInfo
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Abstract
The invention provides a method and a device for improving the stability of NOR type FLASH. The method comprises the following steps: acquiring the address of a fault storage unit; determining a selected storage unit; judging the positions of the selected storage unit and the fault storage unit; if the fault storage unit and the selected storage unit are located on the same column bit line; programming the failed memory cell. The method and the device for improving the stability of the NOR type FLASH provided by the invention improve the stability of the NOR type FLASH.
Description
Technical Field
The invention relates to the technical field of semiconductor memories, in particular to a method and a device for improving NOR type FLASH stability
Background
Flash Memory (Flash Memory) is one kind of Memory, but has the advantages of both RAM and ROM, and is a Memory which can be electrically erased and written in a system, and information is not lost after power failure, and meanwhile, the high integration level and the low cost of the Flash Memory make the Flash Memory become the mainstream of the market. The FLASH chip is composed of thousands of internal storage units (cells), each unit stores one or more bits (bit), has the characteristics of low power consumption, large capacity, high erasing speed, whole piece or sub-sector programming and erasing of the system and the like, and can complete the operation of the chip by an internal embedded algorithm, thereby being widely applied to various embedded systems. As a kind of non-volatile memory, FLASH is generally used in a system to store program codes, constant tables, and some user data that needs to be saved after the system is powered down. FLASH technology is also divided into different development directions according to different application scenarios, wherein NOR type FLASH is good at storing codes. NOR type FLASH is a common storage chip, and data cannot be lost when power is lost. The NOR type FLASH supporting program is directly executed in the FLASH chip. Therefore, in the embedded system, the NOR type FLASH is well suited as a storage medium for the boot program.
Stability is the ability of a product to perform a specified function under specified conditions and for a specified time. For NOR-type FLASH, generally, data retention, endurance, interference resistance, etc. are important parameters for evaluating the reliability of FLASH memory, where data retention refers to the ability of data stored in FLASH memory to be effectively read without distortion or loss after a period of time. In NOR-type FLASH, the threshold voltage of a memory cell in NOR-type FLASH changes with time. Or the threshold voltage of the storage unit in the NOR FLASH is too small, and the problem that when the NOR FLASH array works normally, the normal storage unit is influenced by the fault storage unit, so that the storage unit is read wrongly exists.
In the prior art, the method is adopted to shield the fault storage units when the NOR type FLASH works normally, but the fault storage units still exist physically, and the shielding can not effectively eliminate the interference of the fault storage units on the working of the FLASH chip.
Disclosure of Invention
In view of this, the present invention provides a method and an apparatus for improving the stability of NOR-type FLASH, so as to improve the stability of NOR-type FLASH.
In a first aspect, an embodiment of the present invention provides a method for improving NOR-type FLASH stability, where the method includes:
acquiring the address of a fault storage unit;
determining a selected storage unit;
judging the positions of the selected storage unit and the fault storage unit;
if the fault storage unit and the selected storage unit are located on the same column bit line;
programming the failed memory cell.
Optionally, the memory cell is an intersection of a word line row and a bit line column.
Optionally, programming the failed memory cell comprises,
and adding the word line voltage of the fault storage unit to 8V-10V, and adding the bit line voltage to 3V-5V.
Optionally, programming the failed memory cell comprises:
reading the programmed threshold voltage of the fault storage unit in real time;
and stopping programming operation on the fault storage unit when the threshold voltage of the fault storage unit is larger than or equal to the word line voltage of the unselected storage unit.
In a second aspect, an embodiment of the present invention provides an apparatus for improving NOR-type FLASH stability, where the apparatus includes:
word lines and bit lines for forming a memory cell array;
the fault storage unit recording module is used for acquiring the unit address of the fault storage unit;
the word line gating module is used for gating the word line corresponding to the selected storage unit; the bit line gating module is used for gating the bit line corresponding to the selected storage unit;
the storage unit position judging module is used for judging the positions of the selected storage unit and the fault storage unit and is connected with the fault storage unit recording module;
and the programming module is connected with the fault storage unit recording module and used for programming the fault storage unit when the fault storage unit and the selected storage unit are positioned on the same column bit line.
Optionally, the memory cell is a cross point of a word line and a bit line, and the word line is connected to the memory cell through the word line gating module; the bit line is connected with the storage unit through the bit line gating module.
Optionally, the word line gating module is configured to gate a word line corresponding to the selected memory cell, and add 8V to 10V to the word line voltage of the failed memory cell; and the bit line gating module is used for gating the bit line corresponding to the selected storage unit, and adding 3-5V to the bit line voltage of the fault storage unit.
Optionally, the apparatus further comprises: the sensitive amplifier is connected with the bit line gating module and used for reading the threshold voltage programmed by the fault storage unit in real time according to the received electric signal;
and the program stopping module is used for stopping programming the fault storage unit when the threshold voltage of the fault storage unit is greater than or equal to the word line voltage of the unselected storage unit.
The invention provides a method and a device for improving NOR type FLASH stability, which are characterized in that a selected storage unit is determined by obtaining the address of a fault storage unit, the positions of the selected storage unit and the fault storage unit are judged, and if the fault storage unit and the selected storage unit are positioned on the same column bit line, the fault storage unit is programmed. The interference of the fault storage unit to the selected storage unit is avoided, and the stability of the NOR type FLASH is improved.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, which is to be read in connection with the accompanying drawings.
Fig. 1 is a flowchart of a method for improving the stability of NOR-type FLASH according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a memory cell array structure corresponding to a single SA of an enhanced NOR FLASH according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for improving the stability of NOR-type FLASH according to a second embodiment of the present invention;
FIG. 4 is a Gaussian distribution curve of a method for improving the stability of NOR-type FLASH according to the second embodiment of the present invention;
FIG. 5 is a schematic structural diagram of an apparatus for improving the stability of a NOR-type FLASH according to a third embodiment of the present invention;
fig. 6 is a schematic structural diagram of an apparatus for improving NOR-type FLASH stability according to a fourth embodiment of the present invention.
Detailed Description
The technical scheme of the invention is further explained by the specific implementation mode in combination with the attached drawings. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a flowchart of a method for improving the stability of a NOR-type FLASH according to an embodiment of the present invention. Fig. 2 is a schematic diagram of an array structure corresponding to a single SA of an enhanced NOR FLASH according to an embodiment of the present invention.
Fig. 1 is a flowchart of a method for improving the stability of a NOR-type FLASH according to an embodiment of the present invention.
The invention provides a method for improving NOR type FLASH stability, which comprises the following steps:
The defective memory cell mentioned in this embodiment refers to a memory cell with a threshold voltage that is too low due to the reason of the manufacturing process of the memory cell or long-term programming and erasing operations. In this embodiment, the related art records the failed memory cell and its address in advance through the detection means.
The selected memory cell is uniquely identified by the word line and the bit line.
And step 130, judging the positions of the selected storage unit and the fault storage unit.
And judging the position relation between the selected storage unit and the fault storage unit. Optionally, the memory cell is an intersection of a word line row and a bit line column. Therefore, the location of the memory cell can be determined by determining the word line row and bit line column in which the memory cell is located.
And 140, if the fault storage unit and the selected storage unit are positioned on the same column bit line.
When the failed memory cell and the selected memory cell are located on the same column bit line, the following steps are performed.
Illustratively, referring to fig. 2, fig. 2 is a schematic diagram of an array structure corresponding to a single Sense Amplifier (SA) of NOR type FLASH, wherein SBL is connected to SA and selected to a Global Bit Line (GBL) <1:0> by a gate signal YA <1:0>, and GBL <1:0> is connected to a word line (BL) <7:4> and BL <3:0> by a high voltage gate switch (YDIV) <3:0 >. Wherein GBL <0> is electrically connected to a word line (BL) <0> through a high-voltage gate switch (YDIV) <0> electrically connected to GBL <0 >; GBL <0> is electrically connected to a word line (BL) <1> through a high-voltage gate switch (YDIV) <1> electrically connected to GBL <0 >; GBL <0> is electrically connected to a word line (BL) <2> through a high-voltage gate switch (YDIV) <2> electrically connected to GBL <0 >; GBL <0> is electrically connected to a word line (BL) <3> through a high-voltage gate switch (YDIV) <3> electrically connected to GBL <0 >. GBL <1> is electrically connected to a word line (BL) <4> through a high-voltage gate switch (YDIV) <0> electrically connected to GBL <1 >; GBL <1> is electrically connected to a word line (BL) <5> through a high-voltage gate switch (YDIV) <1> electrically connected to GBL <1 >; GBL <1> is electrically connected to a word line (BL) <6> through a high-voltage gate switch (YDIV) <2> electrically connected to GBL <1 >; GBL <1> is electrically connected to a word line (BL) <7> through a high-voltage gate switch (YDIV) <3> electrically connected to GBL <1 >.
NOR-type FLASH distinguishes whether a selected memory cell is programmed or erased by a current on GBL (Icell 0) and a current of a reference memory cell (Iref). The principle of the read operation of the NOR FLASH is as follows: a read voltage (Vr) is applied to the word line of the selected memory cell A, where Vr is between the threshold voltages of the erased and programmed memory cells, and 0V may be applied to the word lines of the unselected memory cells, as an example. If the selected memory cell A is in an erased state, a large current flows to the ground line through the selected memory cell because Vr is greater than the threshold voltage of the selected memory cell A. Therefore, SA can detect whether the selected memory cell is storing 1 or 0 according to the magnitude of the current on the bit line, and corresponding to the selected memory cell A in FIG. 2, when the selected memory cell A is read, i.e., Icell0> Iref, SA will output 1, indicating that the memory cell A is an erased memory cell. If Icell0< Iref, then SA will output a 0 indicating that the memory cell is a programmed cell.
It should be noted that the threshold voltage of the failed memory cell is not necessarily less than 0V, and the threshold voltage is not controllable. When the failed memory cell and the selected memory cell are in the same column of bit lines, the failed memory cell is an unselected memory cell, so that in this case, when the threshold voltage is less than or equal to the word line voltage added by the unselected memory cell, the failed memory cell can cause a read error of the selected memory cell.
Since the threshold voltage of the failed memory cell is not controllable, and the magnitude relationship between the threshold voltage of the failed memory cell and the word line voltage applied to the unselected memory cell is uncertain, the threshold voltage of the failed memory cell is not limited when the failed memory cell is programmed.
It should be noted that, in the method for improving the stability of NOR-type FLASH memory provided in this embodiment, a program operation is performed on a faulty memory cell before an erase operation, and since the erase time is long (ms level), the length of the program time for the faulty memory cell does not affect the subsequent erase operation. The operation of reading the memory cell and the operation of programming are short, and generally the faulty memory cell is not programmed before the normal reading and programming operations.
Since the failed cell B is located on the same column of bit lines as the selected cell A, if the threshold voltage of the failed cell B is lower than the word line voltage applied to the unselected cells and the word line voltage applied to the unselected cells is the word line voltage applied to the unselected cells, so that the failed cell B cannot be turned off, an extra current (IcellB 1) is formed on the bit line, so that a large current appears on the bit line when the programmed cell is detected, resulting in SA being the sum of the current (IcellA 1) of the selected cell A and IcellB1 for comparison with Iref, which results in a misjudgment. That is, icelb 1 will merge with IcellA1 into GBL <0> forming current Icell0, resulting in a mismatch of Icell0 and IcellA 1. If IcellA1< Iref, i.e., cell a is a programmed cell, but icelb 1 is large enough to result in Icell0> Iref, then SA will determine the selected cell a to be an erased cell, causing an error in the reading of the selected cell a.
Therefore, a program operation is required for the failed memory cell B, and the program operation is performed by injecting electrons into the floating gate to raise the threshold voltage of the failed memory cell B.
Optionally, during programming, the word line voltage of the failed memory cell is added to 8V-10V, and the bit line voltage is added to 3V-5V. The principle of programming the defective memory cell to avoid the interference of the defective memory cell to the selected memory cell of the same column of bit lines is mainly as follows: because the fault memory cell and the selected memory cell are on the same column bit line, when the word line voltage is applied to the selected memory cell, the word line voltage applied to the unselected memory cell is applied to the word line of the fault memory cell, and the voltage value is greater than the threshold voltage of the fault memory cell, so that the leakage phenomenon can occur, the reading error of the selected memory cell can be caused, and the subsequent erasing or programming operation of the selected memory cell can be influenced. The threshold voltage of the defective memory cell is increased by programming. As the threshold voltage of the programmed fault storage units is increased, the fault storage units can be shut down better, the influence of the fault storage units on the performance of a chip can be reduced, and the stability of the NOR type FLASH is improved.
The invention provides a method for improving NOR type FLASH stability, which comprises the steps of determining a selected storage unit by obtaining the address of a fault storage unit, judging the positions of the selected storage unit and the fault storage unit, and programming the fault storage unit if the fault storage unit and the selected storage unit are positioned on the same column bit line. The interference of the fault storage unit to the selected storage unit is avoided, and the stability of the NOR type FLASH is improved.
Example two
Fig. 3 is a flowchart of a method for improving NOR-type FLASH stability according to a second embodiment of the present invention. Fig. 4 shows a gaussian distribution curve of a method for improving the stability of NOR-type FLASH according to the second embodiment of the present invention.
On the basis of the foregoing embodiments, the programming the defective memory cell according to the embodiments of the present invention includes: reading the programmed threshold voltage of the fault storage unit in real time; and stopping programming operation on the fault storage unit when the threshold voltage of the fault storage unit is larger than or equal to the word line voltage of the unselected storage unit.
The corresponding method steps are as follows:
And step 230, judging the positions of the selected storage unit and the fault storage unit.
And 240, if the fault storage unit and the selected storage unit are positioned on the same column bit line.
The word line voltage of the unselected memory cell is generally 0V. This embodiment will be described by taking the word line voltage 0V of the unselected memory cell as an example.
Taking FIG. 2 as an example, the failed memory cell B and the selected memory cell A are located on the same column bit line. The first programming of the defective memory cell B includes: reading the programmed threshold voltage of the fault storage unit B in real time; when the threshold voltage of the defective memory cell B is equal to or greater than the word line voltage of the non-selected memory cell, for example, 0V, referring to the gaussian distribution diagram of the program voltage of fig. 4, the program operation for the defective memory cell B is stopped. When a fault storage unit is programmed, reading current of the fault storage unit B through a sense amplifier SA in real time, comparing the read current with reference current to obtain information of threshold voltage of the fault storage unit B, and stopping programming operation on the fault storage unit when the threshold voltage of the fault storage unit is larger than or equal to 0V. The reading process of the memory cell is the prior art and is not described herein again.
When the selected memory cell A is operated, firstly programming the fault memory cell B, FIG. 4 is a schematic diagram of Gaussian distribution of threshold voltages after the fault memory cell is programmed, Vr in the diagram is the voltage added by a word line selected in a reading operation, the area of dotted lines V1-0 is the threshold voltage distribution of the fault memory cell B before programming, solid lines V2-V3 are the threshold distribution of the fault memory cell B after programming, and the threshold voltage is increased after programming. When reading operation is carried out on the selected memory cell A, the word line voltage of the failed memory cell B is 0V, the bit line voltage of the failed memory cell B is the same as that of the selected memory cell A, and the threshold voltage of the failed memory cell B is changed from being less than 0V to being more than 0V after programming. Therefore, when reading the memory cell a, the defective memory cell B is turned off when the threshold voltage is higher than 0V, and the influence of the defective memory cell B on the bitline current can be reduced. Taking fig. 2 as an example, when the threshold voltage of the failed memory cell B is greater than 0V, and then the memory cell a is selected by reading the corresponding word line WLn and bit line BL <1>, the gate signals YA <0> and YDIV <1> need to be set to high level, so that the selected memory cell a is connected through BL <1>, GBL <0>, SBL and SA. When reading the memory cell a, the threshold voltage of the failed memory cell B after programming is greater than 0V, see fig. 4, the read voltage Vr is greater than 0V, the failed memory cell B is turned off, no extra current (icelb 1) is formed on the bit line, and SA is used to compare Iref to the sum of the current of the selected memory cell a (IcellA 1) and IcellA1, which does not result in a mismatch of Icell0 and IcellA1 because IcellA1 is very small. If IcellA1< Iref, i.e. cell a is a programmed cell, icelb 1 is small and Icell0< Iref, then SA will determine the selected cell a as a programmed cell, so that the cell can be read normally. Where WLn +1 and WLn 1 are other word lines than word line WLn.
The embodiment of the invention provides a method for improving the stability of NOR type FLASH, which is characterized in that the threshold voltage after the fault storage unit is compiled is read in real time; and when the threshold voltage of the fault storage unit is greater than or equal to the word line voltage of the unselected storage unit, stopping programming operation on the fault storage unit, avoiding the interference of the fault storage unit on the selected storage unit, and improving the stability of the NOR type FLASH.
It should be noted that, for example, after the program operation on the failed memory cell reaches the requirement, any desired operation of subsequent reading, writing and erasing is performed. Therefore, the normal working process of the selected storage unit cannot be influenced by the fault storage unit.
EXAMPLE III
Fig. 5 is a schematic structural diagram of an apparatus for improving NOR-type FLASH stability according to a third embodiment of the present invention.
The embodiment of the invention provides a device for stabilizing NOR type FLASH, which comprises:
word lines and bit lines for forming the memory cell array 510;
a failure storage unit recording module 520, configured to obtain an address of a failure storage unit;
a word line gating module 530 for gating the word line corresponding to the selected memory cell; the bit line gating module 540 is used for gating the bit line corresponding to the selected memory cell;
a storage unit position determining module 550, configured to determine positions of the selected storage unit and the failed storage unit, and connect to the failed storage unit recording module;
and the programming module 560 is connected to the defective memory cell recording module, and is configured to program the defective memory cell when the defective memory cell and the selected memory cell are located on the same column bit line.
The invention provides a device for improving NOR type FLASH stability, which is characterized in that a selected storage unit is determined by obtaining the address of a fault storage unit, the positions of the selected storage unit and the fault storage unit are judged, and if the fault storage unit and the selected storage unit are positioned on the same column bit line, the fault storage unit is programmed. The interference of the fault storage unit to the selected storage unit is avoided, and the stability of the NOR type FLASH is improved.
Example four
Fig. 6 is a schematic structural diagram of an apparatus for improving NOR-type FLASH stability according to a fourth embodiment of the present invention.
Referring to fig. 6, on the basis of the above embodiments, the embodiments of the present invention provide a NOR-type FLASH stability device. The memory unit is a cross point of a word line and a bit line, and the word line is connected with the memory unit through the word line gating module; the bit line is connected with the storage unit through the bit line gating module.
Optionally, the word line gating module is configured to gate a word line corresponding to the selected memory cell, and add 8V to 10V to the word line voltage of the failed memory cell; the bit line gating module is used for gating the bit line corresponding to the selected storage unit, and adding 3-5V to the bit line voltage of the fault storage unit.
Optionally, the device for NOR-type FLASH stability provided in the embodiment of the present invention further includes: the sensitive amplifier 660 is connected with the bit line gating module and used for reading the programmed threshold voltage of the fault storage unit in real time according to the received electric signal;
the program stopping module 670 is configured to stop programming the failed memory cell when the threshold voltage of the failed memory cell is greater than or equal to the word line voltage of the unselected memory cell.
The embodiment of the invention provides a device for improving the stability of NOR type FLASH, which is characterized in that the threshold voltage of a fault storage unit after being compiled is read in real time through a sense amplifier; and when the threshold voltage of the fault storage unit is greater than or equal to the word line voltage of the unselected storage unit, stopping programming operation on the fault storage unit, avoiding the interference of the fault storage unit on the selected storage unit, and improving the stability of the NOR type FLASH.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (6)
1. A method for improving NOR type FLASH stability is characterized by comprising the following steps:
acquiring the address of a fault storage unit;
determining a selected storage unit;
judging the positions of the selected storage unit and the fault storage unit;
if the fault storage unit and the selected storage unit are located on the same column bit line;
programming the failed memory cell;
programming the failed memory cell comprises:
reading the programmed threshold voltage of the fault storage unit in real time;
and stopping programming operation on the fault storage unit when the threshold voltage of the fault storage unit is larger than or equal to the word line voltage of the unselected storage unit.
2. The method of claim 1, wherein:
the memory cells are intersections of word line rows and bit line columns.
3. The method of claim 2,
the programming of the defective memory cell includes,
and adding the word line voltage of the fault storage unit to 8V-10V, and adding the bit line voltage to 3V-5V.
4. An apparatus for improving NOR-type FLASH stability, comprising:
word lines and bit lines for forming a memory cell array;
the fault storage unit recording module is used for acquiring the unit address of the fault storage unit;
the word line gating module is used for gating the word line corresponding to the selected storage unit; the bit line gating module is used for gating the bit line corresponding to the selected storage unit;
the storage unit position judging module is used for judging the positions of the selected storage unit and the fault storage unit and is connected with the fault storage unit recording module;
the programming module is connected with the fault storage unit recording module and used for programming the fault storage unit when the fault storage unit and the selected storage unit are positioned on the same column bit line;
the sensitive amplifier is connected with the bit line gating module and used for reading the threshold voltage programmed by the fault storage unit in real time according to the received electric signal;
and the program stopping module is used for stopping programming the fault storage unit when the threshold voltage of the fault storage unit is greater than or equal to the word line voltage of the unselected storage unit.
5. The apparatus of claim 4, wherein:
the memory unit is a cross point of a word line and a bit line, and the word line is connected with the memory unit through the word line gating module; the bit line is connected with the storage unit through the bit line gating module.
6. The apparatus of claim 5, comprising:
the word line gating module is used for gating the word line corresponding to the selected storage unit, and 8V-10V is added to the word line voltage of the fault storage unit; and the bit line gating module is used for gating the bit line corresponding to the selected storage unit, and adding 3-5V to the bit line voltage of the fault storage unit.
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