CN108073155A

CN108073155A - The method being monitored for the timer to integrated circuit

Info

Publication number: CN108073155A
Application number: CN201711137321.6A
Authority: CN
Inventors: F.I.S.平佐恩; Y.朝维特
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2016-11-17
Filing date: 2017-11-16
Publication date: 2018-05-25
Also published as: DE102016222618A1

Abstract

The present invention relates to one kind to be used for integrated circuit（100）Timer（101）The method being monitored, wherein by the integrated circuit（100）Signal of communication comprising clock signal is received by synchronous communication channel, wherein the clock signal is used for the timer to the inside（101）It is monitored.

Description

The method being monitored for the timer to integrated circuit

Technical field

The method and one kind being monitored the present invention relates to a kind of timer of the inside for integrated circuit are used for Implement the integrated circuit of the method.

Background technology

Integrated circuit, especially application-specific integrated circuit（English：application-specific integrated Circuit, ASIC）There can be internal timer（So-called clock）, the timer of the inside is for the ASIC's Internal logic circuit.The timer of this inside may failure so that the ASIC sinks into the state of no response.If The state machine of inside in ASIC is held stationary against for this reason in a kind of state, then this is likely to have undesirable Effect.

There may be multiple timers, the timer in crucial system for safety mutually to monitor.It deposits therefore In substantial amounts of method, from simple phase comparator up to the PLL circuit with multiple oscillators.

9246667 B2 of US illustrate a kind of integrated circuit, which has shaking for the inside as system clock Swing device.Data flow comprising synchronizing signal can be received by series connection.

2012/110365 A1 of US illustrate a kind of method for being used to carry out USB device time adjustment.One can be used Kind counter, the counter is by the clock cycle of internal oscillator compared with reference signal.If the counter Numerical value deviates desired value, then can improve or reduce the frequency of the oscillator.

The content of the invention

According to the present invention, feature, a kind of inside being used for integrated circuit with independent patent claim is proposed The method that is monitored of timer and a kind of for implementing the integrated circuit of the method.Favourable designing scheme is subordinate The theme of claim and description below.

The present invention proposes, in integrated circuits, such as passes through synchronous communication channel in ASIC or microcontroller Carry out receiving time signal, for thus the timer of the inside to be monitored or checked.This also allows mutual monitoring.

The present invention introduces the solution that a kind of simple and steady, for the inside to integrated circuit timer is monitored Scheme, and the timer of multiple inside is not required in the circuit therefore.The solution is very cheap, it is easy to implement and Natively existing signal is only used only.

Different procotols is used in the data transmission such as in automatic technology or vehicle technology, is typically Fieldbus or movement bus, for by various components, especially control unit and field device, as such as electric control machine Structure, driving adjuster, E/A equipment etc. are joined to one another.These procotols can be divided into be passed with synchronous data It is defeated（Such as Sercos 2, Servos III, EtherCAT Profinet IRT）Procotol and with asynchronous number According to transmission（Such as CAN, Profinet RT, Ethernet/IP, Profibus）Procotol.

In the synchronization of synchronize or clock cycle（=in real time）During data transmission, the clock cycle, namely with It is regular to be spaced to carry out various information（So-called " telegram " or data packet）Transmission.User's synchronously can be by means of For example the clock signal that can be transmitted by the conducting wire of itself carries out.

Bus modern, that two kinds of transmission modes are united and are preferably suitable for the present invention is microsecond bus （Micro-Second-Bus：MSB）.This microsecond bus can realize microcontroller and such as analog line driver-sub-assembly Between effective communication, the analog line driver-sub-assembly controls actuator, such as valve, relay or motor And diagnosis.The MSB has synchronous channel（Downstream）With asynchronous channel（Upstream）.The synchronous channel ratio is as can enough 20 MHz carry out pulse excitation.

It is preferred that the time interval of equal length is generated in the integrated circuit from clock signal.In each time interval Inside is to the clock cycle of the timer of the inside（Takte）It is counted and is compared itself and internal desired value Compared with.If the counting is too high, then it means that the frequency of the timer of the inside is too high.And if the counting It is too low, then it means that the frequency of the timer of the inside is too low.In this way, can realize a kind of special Simple assessment method.

When the count value and the desired value may differ by more than the tolerance threshold allowed, failure letter is preferably generated Number, the failure that the possibility for pointing out the timer of the integrated circuit ahead of time faces.

There is internal timer by the integrated circuit of the present invention and be configured for implementing in the present inventive method.

The other advantage and designing scheme of the present invention is drawn from specification and drawings.

Description of the drawings

The present invention is schematically depicted in the drawings by means of a kind of embodiment and is described with reference to the accompanying drawings.Its In：

Fig. 1 schematically shows a kind of preferred embodiment of the integrated circuit by the present invention.

Specific embodiment

A kind of preferred embodiment by the integrated circuit of the present invention is schematically shown in Fig. 1 and in totality On it is represented with 100.The integrated circuit 100 is such as configured to ASIC and with internal timer（“Clock”） 101st, arithmetic logic unit（“ALU”）102 and communication interface 103.The element being previously mentioned is each other among communication connection.It is logical Letter interface 103 is configured to synchronous communication system, microsecond bus（MSB）And equipped with affiliated data conductor connection 200, institute State data conductor connection has the conducting wire 201 of clock signal individual, for synchronous communication herein.

By the conducting wire 201, by the integrated circuit 100 come receive to make the communication interface 103 with it is same The clock signal of the communication system synchronization of step, and now in the range of a kind of preferred embodiment of the present invention described The inside of integrated circuit 100 is continued on for being monitored the timer 101.

For this purpose, a kind of preferred embodiment according to the invention, the ALU 102 such as roots from the clock signal According to the side edge in the clock signal（Flanken）To form the time interval of identical duration.In addition, the ALU determines to be used for The desired value of the clock cycle of certain amount, clock cycle of the number should by the timer 101 time interval it Inside export.For this purpose, such as it can notify the rated frequency of the timer 101 and the clock signal to the ALU 102 Rated frequency.

Now, the ALU 102 is during operation is monitored（Especially continuously）To during time interval by described Clock cycle caused by timer 101 is counted and by it compared with the desired value.

If the clock cycle count value is more than the desired value, then it means that the timer 101 works It is too fast；And if the clock cycle count value is less than the desired value, then it means that the timer 101 works It is too slow.It can set in both cases（Also it is different if necessary）Tolerance, so that small deviation will not cause failure Triggering.

It is preferred to generate fault-signal and such as pass through institute but if the deviation is in outside the tolerance allowed It states communication system 200 or is output it in a manner of arbitrary others.

Claims

1. for integrated circuit（100）Timer（101）The method being monitored,

Wherein by the integrated circuit（100）Signal of communication comprising clock signal is received by synchronous communication channel,

The clock signal is wherein used for the timer to the inside（101）It is monitored.

2. by method described in claim 1, wherein by the integrated circuit（100）From the clock signal between generation time Every and per time interval to the timer（101）Clock cycle counted.

3. the method as described in claim 2, wherein by the integrated circuit（100）Determine to be used for timing described in per time interval Device（101）Clock cycle desired value, and by the clock cycle counted compared with the desired value.

4. the method as described in claim 3, wherein when the clock cycle counted deviateing the desired value by described integrated Circuit（100）Generate fault-signal.

5. the method as any one of claim 2 to 4, wherein by the integrated circuit（100）From the clock signal The middle time interval for generating equal length.

6. the method as any one of preceding claims, wherein the conducting wire that the clock signal passes through itself（201）Come It receives.

7. the method as any one of preceding claims, wherein the signal of communication is microsecond bus signals.

8. with internal timer（101）With synchronous communication interface（103）Integrated circuit（100）, the integrated circuit It is configured for implementing the method as any one of preceding claims.

9. the integrated circuit as described in claim 8（100）, wherein the communication interface（103）It is microsecond bus interface.