CN108062936A - Driving circuit and driving method - Google Patents
Driving circuit and driving method Download PDFInfo
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- CN108062936A CN108062936A CN201711297746.3A CN201711297746A CN108062936A CN 108062936 A CN108062936 A CN 108062936A CN 201711297746 A CN201711297746 A CN 201711297746A CN 108062936 A CN108062936 A CN 108062936A
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- voltage
- electrically connected
- mos transistor
- operational amplifier
- driving circuit
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
Abstract
The present invention discloses a kind of driving circuit and driving method, and the driving circuit includes a current sense unit, a signal amplification unit, an analog-digital converter, time schedule controller and a level shifter.Utilize the design of the current sense unit; and coordinate the signal amplification unit, time schedule controller and level shifter to adjust the size of the guard time, the time delay and overcurrent protection; leakage current thus can be detected; to determine the current protection protection setting of the level shifter; and degree of aging difference and the time difference of aging for each machine; different protected modes is set out, reduces malfunction in use.
Description
Technical field
The invention relates to a kind of driving circuit and driving methods, and it is non-display to be arranged on panel in particular to one kind
The driving circuit and driving method in region.
Background technology
General grid array integrated circuits (Gate-driver on Array, GOA) technology can be moved using TFT to realize
The circuit function of bit register, shift register is integrated on image element array substrates.GOA can be with pixel substrate same
It is completed under making technology, so as to simplify the production procedure of whole display device.In addition, GOA technologies (Gate Driver on
Array) i.e. array substrate row actuation techniques are original array process with liquid crystal display panel by the driving of horizontal scanning line
Circuit production makes it to substitute external integrated circuit plate ((Integrated Circuit, IC) on the substrate around viewing area
To complete the driving of horizontal scanning line.GOA technologies can reduce welding (bonding) process of external IC, and have an opportunity promotion production capacity
And product cost is reduced, and liquid crystal display panel can be made to be more suitable for the display product for making narrow frame or Rimless.
However, (Thin film transistor liquid crystal display, TFT-LCD) is passing through at present
After aging, difference and drift due to processing procedure, internal TFT elements are easy to aging, IV Curve are caused to drift about, no
Drift amount under conditions of is different.Especially for GOA machines, after aging, panel drives internal TFT-LCD
Dynamic level shifter (Level Shifter IC) is difficult to bleed off internal charge when shutdown, opens again afterwards
GOA circuits are easily lead to when machine to leak electricity at work, and high current is caused to occur or even trigger overcurrent protection (Over
Current Protection,OCP)。
Therefore, it is necessary to a kind of driving circuit and driving method of improvement are provided, to solve asking present in the prior art
Topic.
The content of the invention
In view of this, it is an object of the invention to provide a kind of driving circuit and driving method, current sense unit is utilized
Leakage current is detected, then judges the size of leakage current by time schedule controller, to determine the OCP protection settings of level shifter,
The degree of aging difference of each machine and the time difference of aging can be thus directed to, sets out different Level
Shifter protected modes reduce malfunction in use.
To reach the object defined above of the present invention, one embodiment of the invention provides a kind of driving circuit, the driving circuit bag
Containing a current sense unit, a signal amplification unit, an analog-digital converter, time schedule controller and a level shifter；Wherein
The current sense unit is electrically connected scan line and a data cable；The signal amplification unit is electrically connected the electric current and detects
Survey unit；The analog-digital converter is electrically connected the signal amplification unit, for by a voltage conversion into a data value；It is described
Time schedule controller is electrically connected the signal amplification unit, for judging one by receiving the data value of the analog-digital converter
The size of leakage current, union go out a respective value of the data value；The level shifter is electrically connected the timing control
Device for passing through the respective value for receiving the data value, and generates a guard time and a time delay.
In one embodiment of this invention, the current sense unit has one first MOS transistor, one the 2nd MOS crystalline substances
Body pipe, a capacitance and a sampling resistor, wherein first MOS transistor has：One grid is electrically connected the scan line；
One drain electrode, is electrically connected the data cable；And a source electrode, it is electrically connected a drain electrode of second MOS transistor；Described second
MOS transistor has：One grid is electrically connected a raster data model low-voltage；One source electrode is grounded by the sampling resistor；And
The drain electrode passes through one public electrode wire of capacitance connection.
In one embodiment of this invention, the signal amplification unit has one first operational amplifier and one second computing
Amplifier, an input terminal of first operational amplifier are electrically connected the source electrode of second MOS transistor, second fortune
The input terminal for calculating amplifier is electrically connected an output terminal of first operational amplifier, an input of the analog-digital converter
End is electrically connected an output terminal of the second operational amplifier.
In one embodiment of this invention, first MOS transistor and the second MOS transistor are the enhanced MOS of N-channel
Transistor.
In one embodiment of this invention, first operational amplifier is a voltage follower.
In one embodiment of this invention, the second operational amplifier is a voltage amplifier.
To reach the object defined above of the present invention, one embodiment of the invention provides a kind of driving method, the driving method bag
Containing step：One capacitance charge step when the scan line of each frame is scanned, fills a capacitance of a current sense unit
Electricity and formed a charging voltage；One current sense step after the scan line scanning of each frame is terminated, turns off a current sense
One first MOS transistor of unit makes a grid of one second MOS transistor of the current sense unit be electrically connected a grid
Pole drives low-voltage, and a source electrode of second MOS transistor forms a first voltage；One voltage amplification step utilizes
The first voltage is converted to a second voltage by one first operational amplifier of one signal amplification unit, followed by the letter
The second voltage is converted to a tertiary voltage by one second operational amplifier of number amplifying unit；One analog-to-digital conversion step, profit
The tertiary voltage is converted into a data value with an analog-digital converter；One calculation step reads institute by time schedule controller
Data value is stated to judge the size of a leakage current, the respective value that union goes out the data value is write in a level shifter；
And a set-up procedure, a guard time and the time delay of the level shifter are adjusted using the respective value.
In one embodiment of this invention, in the voltage amplification step, first operational amplifier is a voltage
Follower.
In one embodiment of this invention, in the voltage amplification step, the second operational amplifier is a voltage
Amplifier.
In one embodiment of this invention, in the capacitance charge step, the source electrode of first MOS transistor is electrical
One adjustment luminance voltage end of connection, the charging voltage are the 1/14 of an adjustment luminance voltage at the adjustment luminance voltage end.
As described above, present invention driver circuit is mainly the MOS transistor and the 2nd MOS using the current sense unit
The design of transistor obtains the first voltage between the resistance after the capacitance charges, and then judges the leakage current
Size and converse the drift of detecting real-time i-v curve, current required guarantor is then judged according to its offset
Shield degree and protection boundary, then write the non-volatile memory device into the level shifter by the respective value again
In, for controlling for example：The time of start and how many a frames are without detecting, while when can be used for adjusting the protection
Between, the size of the time delay and overcurrent protection, it is thus possible to leakage current is detected, to determine the OCP of level shifter
Protection setting, and degree of aging difference and the time difference of aging for each machine, set out different Level
Shifter protected modes reduce malfunction in use.
Description of the drawings
Fig. 1 and 2 is a schematic diagram of a preferred embodiment of driving circuit according to the present invention.
Fig. 3 is a flow chart of a preferred embodiment of driving method according to the present invention.
Specific embodiment
The explanation of following embodiment is with reference to additional schema, to illustrate the particular implementation that the present invention can be used to implementation
Example.Furthermore the direction term that is previously mentioned of the present invention, for example, above and below, top, bottom, front, rear, left and right, inside and outside, side, surrounding, in
Centre, it is horizontal, laterally, vertically, longitudinally, axial direction, radial direction, top layer or lowest level etc., be only the direction with reference to annexed drawings.Cause
This, the direction term used is to illustrate and understand the present invention rather than to limit the present invention.
It refer to shown in Fig. 1 and 2, be a preferred embodiment of present invention driver circuit, wherein the driving circuit is set
In a GOA (Gate Driver On Array) circuit mechanism, and positioned at a liquid crystal panel a non-display area (not
It illustrates).The driving circuit includes a current sense unit 100, a signal amplification unit 101, an analog-digital converter 7, a period of time
8 and one level shifter 9 of sequence controller.The present invention by be detailed below the above-mentioned each component of each embodiment detail structure,
Assembled relation and its operation principles.
Shown in continuous reference Fig. 1 and 2, the current sense unit 100 is electrically connected scan line GATE and a data cable
DATA.And the current sense unit 100 has one first MOS transistor 2, one second MOS transistor 3, a capacitance C and one
Sampling resistor R, wherein first MOS transistor 2 has a grid 21, a source electrode 22 and a drain electrode 23, the first MOS crystalline substances
The grid 21 of body pipe 2 is electrically connected the scan line GATE, and the source electrode 22 of first MOS transistor 2 is electrically connected an adjustment
Luminance voltage end GAMMA, the drain electrode 23 of first MOS transistor 2 are electrically connected the data cable DATA.2nd MOS
There is transistor 3 grid 31, a source electrode 32 and a drain electrode 33, the grid 31 of second MOS transistor 3 to be electrically connected a grid
Pole drives low-voltage VGL, and the source electrode 32 of second MOS transistor 3 is electrically connected the sampling resistor R, and the sampling
Resistance R is grounded, the one first voltage V1 of formation of source electrode 32 of second MOS transistor 3, i.e., the voltage difference of described sampling resistor R,
The drain electrode 33 of second MOS transistor 3 is electrically connected the adjustment luminance voltage end GAMMA and first MOS transistor 2
Source electrode 22, and pass through the one public electrode wire VCOM of capacitance C connections.In the present embodiment, first MOS transistor
2 and second MOS transistor 3 be enhanced MOS transistor (the Metal-Oxide-Semiconductor Field- of N-channel
Effect Transistor,MOSFET).The capacitance C is electrically connected the adjustment luminance voltage end GAMMA and common electric voltage
Hold VCOM.
Shown in continuous reference Fig. 1 and 2, the signal amplification unit 101 has one first operational amplifier 5 and one second computing
Amplifier 6, first operational amplifier 5 are electrically connected the source electrode 32 of second MOS transistor 3, to receive described
One voltage V1, and export a second voltage V2.In addition, described in the input terminal electric connection of the second operational amplifier 6
One output terminal of the first operational amplifier 5, wherein the second operational amplifier 6 is electrically connected first operational amplifier 5,
To receive the second voltage V2, and export a tertiary voltage V3.In the present embodiment, first operational amplifier 5
For a voltage follower, the second operational amplifier 6 is a voltage amplifier.
Shown in continuous reference Fig. 1 and 2, the one of the analog-digital converter 7 (Analog-to-digital converter, ADC)
Input terminal is electrically connected an output terminal of the second operational amplifier 6.In the present embodiment, the analog-digital converter 7 by with
It puts to receive the tertiary voltage V3, and exports a data value.
Shown in continuous reference Fig. 1 and 2, described in time schedule controller 8 (Timing Controller, the TCON) electric connection
Analog-digital converter 7；The level shifter 9 (Level Shifter IC) is electrically connected the time schedule controller 8；It is wherein described
For time schedule controller 8 for reading the data value to judge the size of a leakage current, union goes out a correspondence of the data value
It is worth and writes in the level shifter 9, to adjust a guard time of the level shifter 9 and a time delay, at this
In embodiment, the time schedule controller 8 is configured to read a value, and then being tabled look-up according to value confirms standing state, such as：
Value is read as 0,000 0100, it was demonstrated that numerical value is a reference value, such as 4, is then tabled look-up, when to confirm numerical value be reference value 4
Current value, and then start adjust overcurrent protection (Over Current Protection, OCP) strategy.
According to above-mentioned structure, when the scan line of each frame proceeds by scanning, charge to the capacitance C and form one
Charging voltage；After the scan line scanning of each frame is terminated, first MOS transistor 2 is turned off, makes the 2nd MOS brilliant
The grid 31 of body pipe 3 is electrically connected the raster data model low-voltage VGL, and the source electrode 32 of second MOS transistor 3 is formed
The first voltage V1；The first voltage V1 is converted into the second voltage followed by first operational amplifier 5
The second voltage V2 is converted to the tertiary voltage V3 by V2 followed by the second operational amplifier 6；Followed by institute
It states analog-digital converter 7 and the tertiary voltage V3 is converted into the data value, that is to say, that the analog-digital converter 7 is by described in
The analog-signal transitions of tertiary voltage V3 are the digital signal of the data value；It is finally read by the time schedule controller 8 described
Data value judges the size of a leakage current, and union goes out a respective value of the data value, and write the level shift
In device 9.
As described above, present invention driver circuit is mainly the MOS transistor 2 and the using the current sense unit 100
The design of two MOS transistors 3 obtains the first voltage V1 between the sampling resistor R after the capacitance C charges, and then
Judge the size of the leakage current and converse the drift of detecting real-time i-v curve (IV Curve), then according to it partially
Shifting amount judges current required degree of protection and protection boundary, then again writes the respective value to the level and moves
In the device 9 of position in non-volatile memory device (NVM), for controlling for example：The time of start and how many a frames without detecting,
It can be used for adjusting the guard time, the time delay and overcurrent protection (Over Current simultaneously
Protection, OCP) size, it is excessive during start shooting next time would not to run into leakage current, and IC chip is caused to be protected
The problem of.
Refer to Fig. 3 and coordinate shown in Fig. 1 and 2, is flow chart according to the preferred embodiment of driving method of the present invention,
Described in driving method include a capacitance charge step S201, a current sense step S202, a voltage amplification step S203, one
Analog-to-digital conversion step S204, a calculation step S205 and a set-up procedure S206.
Continue with reference to Fig. 3 and coordinate shown in Fig. 1 and 2, in the capacitance charge step S201, when the scan line of each frame
When GATE proceeds by scanning, it can charge to a capacitance C of a current sense unit 100 and form a charging voltage；In this reality
It applies in example, the charging voltage is the 1/14 of an adjustment luminance voltage of an adjustment luminance voltage end GAMMA.
Continue with reference to Fig. 3 and coordinate shown in Fig. 1 and 2, in the current sense step S202, when the scanning for terminating each frame
After line scanning, one first MOS transistor 2 of cut-off current detecting unit 100 makes one the 2nd MOS of current sense unit 100
One grid 31 of transistor 3 is electrically connected a raster data model low-voltage VGL, and 32 shape of source electrode of second MOS transistor 3
Into a first voltage V1.
Continue with reference to Fig. 3 and coordinate shown in Fig. 1 and 2, in the voltage amplification step S203, utilize a signal amplification unit
The first voltage V1 is converted to a second voltage V2 by 101 one first operational amplifier 5, is amplified followed by a signal single
The second voltage V2 is converted to a tertiary voltage V3 by one second operational amplifier 6 of member 101.In the present embodiment, it is described
First operational amplifier 5 is a voltage follower, and the second operational amplifier 6 is a voltage amplifier.
Continue with reference to Fig. 3 and coordinate shown in Fig. 1 and 2, in the analog-to-digital conversion step S204, utilize an analog-digital converter 7
The tertiary voltage V3 is converted into a data value, that is to say, that the analog-digital converter 7 is by the simulation of the tertiary voltage V3
Signal is changed into the digital signal of the data value.
Continue with reference to Fig. 3 and coordinate shown in Fig. 1 and 2, in the calculation step S205, institute is read by time schedule controller 8
Data value is stated to judge the size of a leakage current, union goes out a respective value of the data value, and writes a level shift
In device 9.
Continue with reference to Fig. 3 and coordinate shown in Fig. 1 and 2, in the set-up procedure S206, using the respective value to adjust
State the guard time caused by level shifter 9 and a time delay.
As described above, present invention driver circuit is mainly the MOS transistor 2 and the using the current sense unit 100
The design of two MOS transistors 3 obtains the first voltage V1 between the sampling resistor R after the capacitance C charges, and then
Judge the size of the leakage current and converse the drift of detecting real-time i-v curve (IV Curve), then according to it partially
Shifting amount judges current required degree of protection and protection boundary, then again writes the respective value to the level and moves
In the device 9 of position in non-volatile memory device (NVM), for controlling for example：The time of start and how many a frames without detecting,
It can be used for adjusting the guard time, the time delay and overcurrent protection (Over Current simultaneously
Protection, OCP) size, it is thus possible to leakage current is detected, to determine the OCP protection settings of level shifter, thus energy
The time of degree of aging difference and aging enough for each machine is different, sets out different Level Shifter and protects
Shield mode reduces malfunction in use.
The present invention is described by above-mentioned related embodiment, however above-described embodiment is only the example for implementing the present invention.
It must be noted that, it has been disclosed that embodiment be not limiting as the scope of the present invention.On the contrary, it is contained in the spirit of claims
And scope modification and impartial setting be included in the scope of the present invention.
Claims (10)
1. a kind of driving circuit, it is characterised in that：The driving circuit includes：
One current sense unit is electrically connected scan line and a data cable；
One signal amplification unit is electrically connected the current sense unit；
One analog-digital converter is electrically connected the signal amplification unit, for by a voltage conversion into a data value；
Time schedule controller is electrically connected the signal amplification unit, for passing through the data value for receiving the analog-digital converter
Judge the size of a leakage current, union goes out a respective value of the data value；
One level shifter is electrically connected the time schedule controller, for passing through the respective value for receiving the data value, and generates
One guard time and a time delay.
2. driving circuit as described in claim 1, it is characterised in that：The current sense unit has one the oneth MOS crystal
Pipe, one second MOS transistor, a capacitance and a sampling resistor, wherein first MOS transistor has：One grid, electrically connects
Connect the scan line；One drain electrode, is electrically connected the data cable；And a source electrode, it is electrically connected the one of second MOS transistor
Drain electrode；Second MOS transistor has：One grid is electrically connected a raster data model low-voltage；One source electrode is adopted by described
Sample resistance eutral grounding；And the drain electrode passes through one public electrode wire of capacitance connection.
3. driving circuit as claimed in claim 2, it is characterised in that：The signal amplification unit has one first operation amplifier
Device and a second operational amplifier, an input terminal of first operational amplifier are electrically connected second MOS transistor
Source electrode, an input terminal of the second operational amplifier are electrically connected an output terminal of first operational amplifier, the mould
One input terminal of number converter is electrically connected an output terminal of the second operational amplifier.
4. driving circuit as claimed in claim 2, it is characterised in that：First MOS transistor and the second MOS transistor are
N-channel reinforcing MOS transistor.
5. driving circuit as claimed in claim 3, it is characterised in that：First operational amplifier is a voltage follower.
6. driving circuit as claimed in claim 3, it is characterised in that：The second operational amplifier is a voltage amplifier.
7. a kind of driving method, it is characterised in that：The driving method includes step：
One capacitance charge step when the scan line of each frame is scanned, charges to a capacitance of a current sense unit
And form a charging voltage；
One current sense step after the scan line scanning of each frame is terminated, turns off one the oneth MOS of a current sense unit
Transistor makes a grid of one second MOS transistor of the current sense unit be electrically connected a raster data model low-voltage, and
And a source electrode of second MOS transistor forms a first voltage；
The first voltage is converted to one by one voltage amplification step using one first operational amplifier of a signal amplification unit
The second voltage is converted to one the 3rd by second voltage followed by a second operational amplifier of the signal amplification unit
Voltage；
The tertiary voltage is converted into a data value by one analog-to-digital conversion step using an analog-digital converter；
One calculation step reads the data value to judge the size of a leakage current by time schedule controller, and union goes out institute
The respective value for stating data value is write in a level shifter；And
One set-up procedure adjusts a guard time and the time delay of the level shifter using the respective value.
8. driving method as claimed in claim 7, it is characterised in that：In the voltage amplification step, first computing
Amplifier is a voltage follower.
9. driving method as claimed in claim 7, it is characterised in that：In the voltage amplification step, second computing
Amplifier is a voltage amplifier.
10. driving method as claimed in claim 7, it is characterised in that：In the capacitance charge step, the first MOS
The source electrode of transistor is electrically connected an adjustment luminance voltage end, and the charging voltage is the adjustment for adjusting luminance voltage end
The 1/14 of luminance voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711297746.3A CN108062936B (en) | 2017-12-08 | 2017-12-08 | Drive circuit and drive method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711297746.3A CN108062936B (en) | 2017-12-08 | 2017-12-08 | Drive circuit and drive method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108062936A true CN108062936A (en) | 2018-05-22 |
| CN108062936B CN108062936B (en) | 2020-06-16 |
Family
ID=62135472
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711297746.3A Active CN108062936B (en) | 2017-12-08 | 2017-12-08 | Drive circuit and drive method |
Country Status (1)
| Country | Link |
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| CN (1) | CN108062936B (en) |
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| WO2020133634A1 (en) * | 2018-12-27 | 2020-07-02 | 惠科股份有限公司 | Overcurrent protection method, overcurrent protection circuit, and display apparatus |
| WO2021103183A1 (en) * | 2019-11-29 | 2021-06-03 | Tcl华星光电技术有限公司 | Drive circuit, drive method, and display apparatus |
| CN113012609A (en) * | 2020-10-22 | 2021-06-22 | 重庆康佳光电技术研究院有限公司 | Display panel manufacturing method and display panel |
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| Publication number | Publication date |
|---|---|
| CN108062936B (en) | 2020-06-16 |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee after: TCL Huaxing Photoelectric Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
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