CN108038023A - A kind of signal processing method of multi-level flash, device, equipment and storage medium - Google Patents
A kind of signal processing method of multi-level flash, device, equipment and storage medium Download PDFInfo
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- CN108038023A CN108038023A CN201711436379.0A CN201711436379A CN108038023A CN 108038023 A CN108038023 A CN 108038023A CN 201711436379 A CN201711436379 A CN 201711436379A CN 108038023 A CN108038023 A CN 108038023A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0411—Online error correction
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Abstract
The invention discloses a kind of signal processing method of multi-level flash, device, equipment and computer-readable recording medium, including first round error-correcting decoding is carried out to each byte in each flash cell in multi-level flash and obtains each decoding；Each decoding is compared to determine whether each byte decodes correctly with the codeword sequence prestored；Posterior information corresponding with successfully decoded flash cell is calculated according to the first calculation relational expression；Prior information corresponding with the flash cell of decoding failure is obtained from each prior information being previously obtained；Calculated and one-to-one first interference strength of each flash cell according to posterior information corresponding with successfully decoded each flash cell and prior information corresponding with each flash cell of decoding failure；Posterior information post-compensation is carried out to each threshold voltage according to each first interference strength, is obtained and the one-to-one first post-compensation threshold voltage of each flash cell.Improve the reliability of multi-level flash data storage.
Description
Technical field
The present embodiments relate to signal processing technology field, more particularly to a kind of signal processing side of multi-level flash
Method, device, equipment and computer-readable recording medium.
Background technology
Flash memory (Flash memory) is a kind of semi conductor computer memory with many ideal characterisiticses, with science and technology
Development, flash memory device reads and writes using 1 × nmCMOS transistors and faster process so that each flash cell can be with
The data of 1bit are stored over, this kind of flash memory is known as multi-level flash (MLC).But with the increase of flash memory storage density, it is each
The distance between flash cell is gradually reduced, and just generates several the problem of influencing storage data reliability therewith.Due to CMOS
The special construction of transistor, also result in the parasitism electricity between each consecutive storage unit while flash memory storage density increase
Hold coupling effect, in flash array, the parasitic capacitance coupling effect between each adjacent flash cell is CCI (cell-to-
Cell interference), CCI is considered as the main interference for causing flash threshold voltage's distribiuting to change, it will
Cause data storing reliability problem, increase the design complexities of coder in Channel Detection difficulty and flash controller.
Since a variety of interference reduce the reliability of data storage, so needing to add ECCs in flash controller
(error-correcting codes) partly ensures the accuracy of reading and writing data, and based on the LDPC for calculating Soft Inform ation
(Low-density parity-check) code can significantly strengthen the error correcting capability of MLC type flash memories, so in flash-memory channels
It can farthest ensure the reliability of the transmission of data using LDPC code.But also it is not enough to only with powerful error correcting code
Ensure the reliability of reading data to greatest extent, and since CCI is as most important interference in flash-memory channels, so how to have
The elimination CCI of effect is the premise for obtaining maximum error-correcting performance and improving data storing reliability.
At present, the method for eliminating CCI be detect flash cell threshold voltage and using conventional post-compensation by way of come
CCI is eliminated, but the threshold voltage for using this method to be read when carrying out after post-compensationIt is the voltage after CCI is disturbed, and
That we are actually needed is the threshold voltage V after programming, and the threshold voltage after interference can be more than the threshold voltage after programmingSo subsequently calculating CCI intensityWhen make the CCI intensity that calculatesIt is bigger than normal, so as to cause aggrieved in elimination
Overcompensation phenomenon can be caused during the CCI interference of unit, causes aggrieved unit to eliminate the threshold voltage after CCIIt can be less than actual
VoltageAnd with the increase of interference coefficient, overcompensation phenomenon can be increasingly severe, causes threshold voltage
Distribution function occurs significantly to move to left, and it is bad so to may result in signal processing results performance, it is impossible to CCI interference is effectively eliminated,
It is difficult to the reliability for obtaining maximum error-correcting performance and ensuring data storage, and this method is for the flash memory list in erase status
Member can not eliminate CCI.
Another kind is to detect flash-memory channels with adjacent cells threshold voltage prior information and combine post-compensation technology to disappear
Except CCI is disturbed, but this method is the threshold voltage after the compensation obtained using conventional post-compensation methodCalculate priori letter
X is ceased, and interference strength is calculated according to the prior information, due to the threshold value electricity after the compensation that is obtained using conventional post-compensation method
PressureLess than virtual voltage, so being based on the threshold voltageIt is obtaining the result is that each state judge voltage near it is one small
In the range of exist, and the increase of interference coefficient can aggravate the inaccuracy of prior information, cause result and virtual voltage to be deposited
In some gaps, calculate interference strength less than normal, cause post-compensation value bigger than normal, so as to deviate the threshold voltage after programming.
It can be seen from the above, two kinds of post-compensation methods of the prior art there are it is certain the defects of, it is difficult to effectively eliminate CCI
Interference, signal processing performance is bad, is limited error-correcting performance, it is difficult to ensures the reliability of data storage.
In consideration of it, how to provide a kind of signal processing method for the multi-level flash for solving above-mentioned technical problem, device, equipment
And computer-readable recording medium becomes the current problem to be solved of those skilled in the art.
The content of the invention
The purpose of the embodiment of the present invention is to provide a kind of signal processing method of multi-level flash, device, equipment and computer
Readable storage medium storing program for executing, can eliminate the CCI that the flash cell in programming state is subject to a greater extent and do in use
Disturb, and the CCI interference that the flash cell in erase status is subject to can also be effectively eliminated, to obtain the error correcting capability of bigger,
Improve the reliability of data storage.
In order to solve the above technical problems, an embodiment of the present invention provides a kind of signal processing method of multi-level flash, including：
S11：To in each flash cell in multi-level flash each byte carry out first round error-correcting decoding, obtain with each
The byte decodes correspondingly；
S12：It is compared being decoded correspondingly with each byte with the codeword sequence prestored, to determine
Whether each byte decodes correctly；
S13：It is correct to judge whether all bytes in z-th of flash cell decode, if it is, z-th of sudden strain of a muscle
Memory cell is successfully decoded, and enters S14；Otherwise, z-th of flash cell decoding failure, and enter S15；Wherein, z ∈ Z, Z
For the flash cell sum in the multi-level flash；
S14：Posterior information corresponding with z-th of flash cell is calculated according to the first calculation relational expression；Wherein,
One calculation relational expression isWherein, XeFor the equal threshold voltage of erase status, XspFor sentencing under programming state sp
Constant voltage, Δ VppFor program voltage section；
S15：From it is precalculating, with each one-to-one prior information of flash cell obtain with it is described
The corresponding prior information of z-th of flash cell；
S16：According to the successfully decoded one-to-one posterior information of each flash cell and each with decoding failure
The one-to-one prior information of flash cell calculates and each one-to-one first interference strength of flash cell；
S17：Posterior information is carried out to the corresponding threshold voltage of corresponding flash cell according to each first interference strength
Post-compensation, to obtain and each one-to-one first post-compensation threshold voltage of flash cell；Each flash cell
One-to-one threshold voltage is read in advance to be obtained.
Optionally, each byte in each flash cell in multi-level flash carries out first round error-correcting decoding, obtains
Include to the process decoded correspondingly with each byte：
S111：Obtain each threshold voltage distribution function corresponding with each flash cell in multi-level flash；
S112：Calculated and corresponding flash memory list according to threshold voltage distribution function corresponding with each flash cell
The one-to-one maximum likelihood ratio of each byte in member；
S113：Translated according to each byte progress first round error correction is compared with each one-to-one maximum likelihood of byte
Code, obtains decoding correspondingly with each byte in each flash cell.
Optionally, the calculating process with each one-to-one prior information of flash cell is：
Calculated and each sudden strain of a muscle according to one-to-one threshold voltage of flash cell read in advance and each
One-to-one second interference strength of memory cell；
Post-compensation is carried out to the corresponding threshold voltage of corresponding flash cell according to each second interference strength, to obtain
With each one-to-one second post-compensation threshold voltage of flash cell；
Obtained and each flash memory according to each one-to-one second post-compensation threshold voltage of flash cell
The corresponding second post-compensation threshold voltage distribution function of unit；
Calculate and each one-to-one second distribution function parameter of second post-compensation threshold voltage distribution function；
According to each second distribution function parameter, each second post-compensation threshold voltage distribution function, each
The second post-compensation threshold voltage, the average voltage of erase status and the corresponding judgement voltage of each programming state, obtain with
The one-to-one prior information of threshold voltage of each flash cell.
Optionally, it is described to calculate and each one-to-one second point of second post-compensation threshold voltage distribution function
The process of cloth function parameter is：
Calculated and each second post-compensation according to gaussian kernel function and each second post-compensation threshold voltage
One-to-one first distribution function parameter of threshold voltage distribution function.
Optionally, further include：
Obtained and each flash memory according to each one-to-one first post-compensation threshold voltage of flash cell
The corresponding each first post-compensation threshold voltage distribution function of unit；
Calculate and each one-to-one first distribution function parameter of first post-compensation threshold voltage distribution function；
According to each first distribution function parameter and each corresponding 3rd post-compensation threshold voltage distribution function pair
Each byte in each flash cell carries out the second wheel error-correcting decoding, and determines bit error code rate according to decoding result.
The embodiment of the present invention provides a kind of signal processing apparatus of multi-level flash accordingly, including：
First error-correcting decoding module, carries out first round error correction to each byte in each flash cell in multi-level flash and translates
Code, obtains decoding correspondingly with each byte；
Comparison module, is compared for will be decoded correspondingly with each byte with the codeword sequence prestored
It is right, to determine whether each byte decodes correctly；
Judgment module, for judging all bytes in z-th of flash cell, whether decoding is correct, if it is, institute
It is successfully decoded to state z-th of flash cell, and triggers the first computing module；Otherwise, z-th of flash cell decoding failure, and
Trigger acquisition module；Wherein, z ∈ Z, Z are the flash cell sum in the multi-level flash；
First computing module, it is corresponding with z-th of flash cell for being calculated according to the first calculation relational expression
Posterior information；Wherein, the first calculation relational expression isWherein, XeFor the equal threshold voltage of erase status, Xsp
For the judgement voltage under programming state sp, Δ VppFor program voltage section；
The acquisition module, for believing from the one-to-one priori of flash cell precalculate and each
Prior information corresponding with z-th of flash cell is obtained in breath；
Second computing module, for according to the successfully decoded one-to-one posterior information of each flash cell and with translating
The one-to-one prior information of each flash cell of code failure calculates and each flash cell one-to-one first
Interference strength；
Compensating module, for being carried out according to each first interference strength to the corresponding threshold voltage of corresponding flash cell
Posterior information post-compensation, to obtain and each one-to-one first post-compensation threshold voltage of flash cell；It is each described
The one-to-one threshold voltage of flash cell reads obtain in advance.
Optionally, the first error-correcting decoding module includes：
Acquiring unit, for obtaining each threshold voltage distribution letter corresponding with each flash cell in multi-level flash
Number；
Computing unit, for according to threshold voltage distribution function corresponding to each flash cell calculate with it is corresponding
Flash cell in the one-to-one maximum likelihood ratio of each byte；
Decoding unit, for comparing each byte progress first according to each one-to-one maximum likelihood of byte
Error-correcting decoding is taken turns, obtains decoding correspondingly with each byte in each flash cell.
Optionally, the calculating process with each one-to-one prior information of flash cell is：
Calculated and each sudden strain of a muscle according to one-to-one threshold voltage of flash cell read in advance and each
One-to-one second interference strength of memory cell；
Post-compensation is carried out to the corresponding threshold voltage of corresponding flash cell according to each second interference strength, to obtain
With each one-to-one second post-compensation threshold voltage of flash cell；
Obtained and each flash memory according to each one-to-one second post-compensation threshold voltage of flash cell
The corresponding second post-compensation threshold voltage distribution function of unit；
Calculate and each one-to-one second distribution function parameter of second post-compensation threshold voltage distribution function；
According to each second distribution function parameter, each second post-compensation threshold voltage distribution function, each
The second post-compensation threshold voltage, the average voltage of erase status and the corresponding judgement voltage of each programming state, obtain with
The one-to-one prior information of threshold voltage of each flash cell.
An embodiment of the present invention provides a kind of signal handling equipment of multi-level flash, including：
Memory, for storing computer program；
Processor, for performing computer program when, realize the signal processing method of multi-level flash as described above
Step.
An embodiment of the present invention provides a kind of computer-readable recording medium, stored on the computer-readable recording medium
There is computer program, the computer program realizes the signal processing method of multi-level flash as described above when being executed by processor
The step of.
An embodiment of the present invention provides a kind of signal processing method of multi-level flash, device, equipment and computer-readable deposit
Storage media, including：To in each flash cell in multi-level flash each byte carry out first round error-correcting decoding, obtain with each
Byte decodes correspondingly；It is compared being decoded correspondingly with each byte with the codeword sequence prestored, with
Determine whether each byte decodes correctly；It is correct to judge whether all bytes in z-th of flash cell decode, if so,
Then z-th of flash cell is successfully decoded, and calculates posteriority letter corresponding with z-th of flash cell according to the first calculation relational expression
Breath；Otherwise, z-th of flash cell decoding failure, from priori letter precalculating, one-to-one with each flash cell
Prior information corresponding with z-th of flash cell is obtained in breath；Wherein, z ∈ Z, Z are the flash cell sum in multi-level flash；
According to the successfully decoded one-to-one posterior information of each flash cell and with each flash cell of decoding failure one by one
Corresponding prior information calculates and one-to-one first interference strength of each flash cell；According to each first interference strength
Posterior information post-compensation is carried out to the corresponding threshold voltage of corresponding flash cell, it is one-to-one with each flash cell to obtain
First post-compensation threshold voltage；Each one-to-one threshold voltage of flash cell reads obtain in advance.
The embodiment of the present invention, can by carrying out wheel error-correcting decoding to each byte in each flash cell in multi-level flash
To determine each flash cell of successfully decoded each flash cell and decoding failure, calculate with it is successfully decoded each
The corresponding posterior information of flash cell, then obtained out from precomputing in prior information corresponding with each flash cell
Prior information corresponding with each flash cell of decoding failure, so as to be believed according to the posteriority of successfully decoded each flash cell
The prior information of each flash cell of breath and decoding failure calculates the first interference strength corresponding with each flash cell, and leads to
Cross the interference strength of each flash cell and posterior information post-compensation carried out to corresponding flash cell, so as to get each first after
Threshold voltage is compensated closer to the threshold voltage after programming, the flash cell in programming state is eliminated to a greater extent and is subject to
CCI interference, and the CCI interference that the flash cell in erase status is subject to can also be effectively eliminated, to obtain entangling for bigger
Wrong ability, improves the reliability of data storage.
Brief description of the drawings
To describe the technical solutions in the embodiments of the present invention more clearly, below will be to institute in the prior art and embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, drawings in the following description are only some implementations of the present invention
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 is a kind of flow diagram of the signal processing method of multi-level flash provided in an embodiment of the present invention；
Fig. 2 is a kind of structure diagram of the signal processing apparatus of multi-level flash provided in an embodiment of the present invention.
Embodiment
An embodiment of the present invention provides a kind of signal processing method of multi-level flash, device, equipment and computer-readable deposit
Storage media, can eliminate the CCI interference that the flash cell in programming state is subject to a greater extent in use, and
The CCI interference that the flash cell in erase status is subject to can also be effectively eliminated, to obtain the error correcting capability of bigger, improves data
The reliability of storage.
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, the technical solution in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
Part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
All other embodiments obtained without making creative work, belong to the scope of protection of the invention.
Fig. 1 is refer to, Fig. 1 is that a kind of flow of signal processing method of multi-level flash provided in an embodiment of the present invention is illustrated
Figure.
This method includes S11~S17, is specially as follows：
S11：To in each flash cell in multi-level flash each byte carry out first round error-correcting decoding, obtain with each
Byte decodes correspondingly；
It should be noted that include multiple bytes in each flash cell in multi-level flash, for example, in three-level flash memory
Each flash cell include three bytes.By to each word in each flash cell in the multi-level flash after interference
Section carries out first round error-correcting decoding, can obtain decoding after error-correcting decoding, corresponding with each byte.
S12：It is compared being decoded correspondingly with each byte with the codeword sequence prestored, it is each to determine
Whether byte decodes correctly；
Specifically, codeword sequence corresponding with each flash cell in multi-level flash, subsequence can be obtained in advance
In each code word correspond to corresponding byte, to each byte carry out first round error-correcting decoding after, each byte is corresponding
Decoding code word corresponding with corresponding byte is compared, if the corresponding decoding of some byte code word one corresponding with the byte
Cause, then illustrate that byte decoding is correct, if it is inconsistent, illustrating the byte decoding error.
S13：It is correct to judge whether all bytes in z-th of flash cell decode, if it is, z-th of flash memory list
Member is successfully decoded, and enters S14；Otherwise, z-th of flash cell decoding failure, and enter S15；Wherein, z ∈ Z, Z are Multi-stage flash
Flash cell sum in depositing；
It should be noted that the Z in the embodiment of the present invention represents the flash cell total amount in multi-level flash, for example, multistage
Flash memory is m grades of flash memories, its wordline is i, bit line j, then the m grades of flash memory shares i × j flash cell, and the code stored
Word length u=i*j*m.
Specifically, since each flash cell includes multiple bytes, so all bytes only in flash cell
When decoding correct, the flash cell is just successfully decoded, successfully decoded flash cell can be labeled as 0 at this time；Work as flash memory
There are one or more byte decoding errors in the corresponding each byte of unit, corresponding flash cell at this time may be used with regard to decoding failure
The flash cell is labeled as 1.
Corresponding successfully decoded flash cell calculates corresponding posterior information, and by the posterior information for more accurate
Post-compensation, then no longer calculate corresponding posterior information for the flash cell of decoding failure, if with mistake posteriority
Information can then cause the mistake of bigger if compensating, so then being needed with right with it for the flash cell of decoding failure
The prior information answered replaces corresponding posterior information, specifically refer to S14 and S15.
S14：Posterior information corresponding with z-th of flash cell is calculated according to the first calculation relational expression；Wherein, the first meter
Calculating relational expression isWherein, XeFor the equal threshold voltage of erase status, XspFor the judgement electricity under programming state sp
Pressure, Δ VppFor program voltage section；
It should be noted that for successfully decoded flash cell, calculated according to the first calculation relational expression corresponding
Posterior information (namely threshold voltage posterior information) Y, namely calculate one-to-one with each successfully decoded flash cell
Posterior information, wherein, programming state can be 111,110,100,101,001,000,010 and 011 8 states, namely sp ∈
[111,110,100,101,001,000,010,011], certainly, programming state are also not limited to above-mentioned 8 states, specifically can be with
It is determined according to actual conditions.
In addition, program voltage interval Δ VppIt can preset, and its concrete numerical value can be carried out according to actual conditions
Determine.
S15：Obtained from the precalculate and one-to-one prior information of each flash cell and z-th of sudden strain of a muscle
The corresponding prior information of memory cell；
It should also be noted that, the embodiment of the present invention precomputes prior information corresponding with each flash cell, when
During some flash cell decoding failure, then elder generation corresponding with the flash cell is determined from each prior information precalculated
Information is tested, for the calculating of the first follow-up interference strength.
S16：According to the successfully decoded one-to-one posterior information of each flash cell and each with decoding failure
The one-to-one prior information of flash cell calculates and one-to-one first interference strength of each flash cell；
Specifically, decoding situation that can be to each flash cell counts, with judge whether all flash memories
Unit is successfully decoded, and when all flash cells are successfully decoded, the flash cell quantity of decoding failure is 0 at this time,
Need not obtain prior information, direct basis and each one-to-one posterior information calculation of flash cell go out with each
It is dry specifically can to calculate first to one-to-one first interference strength according to the second calculation formula for the flash cell
Intensity (total interference strength of first interference strength for adjacent flash cell to aggrieved unit) is disturbed, wherein, the second calculation formula
For：
I1(p, q)=μxy[Y(p+1,q-1)-Xe]+uy[Y(p+1,q)-Xe]+μxy[Y(p+1,q+1)-Xe]
Wherein, p ∈ (1, i), q ∈ (1, j), I1(p, q) represents that adjacent flash cell is pointed to pth row, the flash memory of q row
First interference strength of unit, μxyFor the parasitic electric coupling ratio in 45 ° of directions, uyFor the parasitic electric coupling ratio in 90 ° of directions.
In addition, when some flash cell decoding failure, it is necessary to which the flash cell threshold voltage posteriority of relevant position is believed
Breath Y is replaced with prior information X corresponding with the flash cell, for example, the flash cell decoding of the position correspondence as (p+1, q-1)
Failure, then can calculate adjacent flash cell to the first dry of the flash cell of pth row, q row according to the 3rd calculation formula
Disturb intensity I1(p, q), wherein, the 3rd calculation formula is：
I1(p, q)=μxy[X(p+1,q-1)-Xe]+uy[Y(p+1,q)-Xe]+μxy[Y(p+1,q+1)-Xe]
Wherein, X (p+1, q-1) represents the corresponding prior information of flash cell arranged positioned at the row of pth+1, q-1.
S17：Mended after carrying out posterior information to the corresponding threshold voltage of corresponding flash cell according to each first interference strength
Repay, to obtain and the one-to-one first post-compensation threshold voltage of each flash cell；Each one-to-one threshold of flash cell
Threshold voltage reads obtain in advance.
It should be noted that obtain with after one-to-one first interference strength of each flash cell, according to each
One interference strength is to the corresponding threshold voltage of corresponding flash cellMore accurate post-compensation is carried out, namely carries out posteriority
Information post-compensation, specifically can be according to the 4th calculation formulaTo corresponding flash memory list
Member carry out posterior information post-compensation, and using equal flash cell posterior information detection flash-memory channels progress post-compensation after, can
So that the first obtained post-compensation threshold voltage is done closer to the threshold voltage after programming so as to preferably eliminate CCI
Disturb.
The embodiment of the present invention, can by carrying out wheel error-correcting decoding to each byte in each flash cell in multi-level flash
To determine each flash cell of successfully decoded each flash cell and decoding failure, calculate with it is successfully decoded each
The corresponding posterior information of flash cell, then obtained out from precomputing in prior information corresponding with each flash cell
Prior information corresponding with each flash cell of decoding failure, so as to be believed according to the posteriority of successfully decoded each flash cell
The prior information of each flash cell of breath and decoding failure calculates the first interference strength corresponding with each flash cell, and leads to
Cross the interference strength of each flash cell and posterior information post-compensation carried out to corresponding flash cell, so as to get each first after
Threshold voltage is compensated closer to the threshold voltage after programming, the flash cell in programming state is eliminated to a greater extent and is subject to
CCI interference, and the CCI interference that the flash cell in erase status is subject to can also be effectively eliminated, to obtain entangling for bigger
Wrong ability, improves the reliability of data storage.
On the basis of above-described embodiment：
As a kind of preferred embodiment, in above-mentioned S11 to each byte in each flash cell in multi-level flash
First round error-correcting decoding is carried out, the process for obtaining decoding correspondingly with each byte can include S111~S113, specifically
It is as follows：
S111：Obtain each threshold voltage distribution function corresponding with each flash cell in multi-level flash；
It should be noted that the corresponding threshold voltage of each flash cell in multi-level flash after reading interference, and according to
Threshold voltage distribution function corresponding with each flash cell is determined according to threshold voltage corresponding with each flash cell, wherein,
Each the corresponding threshold voltage ranges of threshold voltage distribution function, threshold voltage are located in corresponding threshold voltage ranges
The corresponding threshold voltage distribution function of multiple flash cells is identical.
S112：According to threshold voltage distribution function corresponding with each flash cell calculate with corresponding flash cell
The one-to-one maximum likelihood ratio of each byte；
Specifically, each threshold voltage distribution function is respectively provided with two adjacent reference voltages, two adjacent reference voltages
Two terminal voltages of i.e. each threshold voltage distribution function.The maximum likelihood ratio of each byte in each flash cell is calculated
When, two adjacent reference voltages R of acquisition threshold voltage distribution function corresponding with the flash celllAnd Rr, and calculate with being somebody's turn to do
The corresponding probability density function P of threshold voltage distribution functionk(x), according to corresponding two adjacent reference voltages RlAnd Rr, it is corresponding
Probability density function Pk(x) and each byte for calculating in corresponding flash cell of the 5th calculation formula is maximum correspondingly
Likelihood ratio, wherein, the 5th calculation formula is：
Wherein, L (bi) represent the maximum of i-th of byte seemingly
So ratio, SiRepresent the state that i-th of byte is 1.
S113：First round error-correcting decoding is carried out according to each byte is compared with the one-to-one maximum likelihood of each byte,
Obtain decoding correspondingly with each byte in each flash cell.
It should be noted that can be utilized in the embodiment of the present invention phase is compared with the one-to-one maximum likelihood of each byte
The byte answered carries out first round error-correcting decoding, can specifically use BP decoding algorithms.
As a kind of preferred embodiment, the meter with the one-to-one prior information of each flash cell in above-mentioned S15
Calculation process is specifically as follows：
Calculated and each flash cell one according to the read in advance and one-to-one threshold voltage of each flash cell
One corresponding second interference strength；
It should be noted that calculated in the embodiment of the present invention previously according to conventional post-compensation corresponding with each flash cell
The second interference strength.Specifically, can with the corresponding threshold voltage of each flash cell in the multi-level flash after reading interference,
And the second interference strength corresponding with each flash cell is calculated according to the 6th calculation formula, which is adjacent
Wherein, the 6th calculation formula is total interference strength that flash cell produces corresponding flash cell：
Wherein, V (p, q) represents the corresponding threshold voltage of flash cell arranged positioned at pth row, q, I2(p, q) represents position
In corresponding second interference strength of flash cell that pth row, q are arranged, μxyFor the parasitic electric coupling ratio in 45 ° of directions, uyFor 90 ° of sides
To parasitic electric coupling ratio, XeFor the equal threshold voltage of erase status.
According to each second interference strength to the corresponding threshold voltage of corresponding flash cell carry out post-compensation, with obtain with often
A one-to-one second post-compensation threshold voltage of flash cell；
Specifically, it is being calculated with after one-to-one second interference strength of each flash cell, utilizing each second
Interference strength carries out conventional post-compensation to the threshold voltage of corresponding flash cell, can specifically utilize formulaObtain with the one-to-one second post-compensation threshold voltage of each flash cell, wherein,Represent the corresponding second post-compensation threshold voltage of flash cell arranged positioned at pth row, q.
It is corresponding with each flash cell according to being obtained with the one-to-one second post-compensation threshold voltage of each flash cell
The second post-compensation threshold voltage distribution function；
Specifically, can according to the one-to-one second post-compensation threshold voltage of each flash cell determine with each
The one-to-one second post-compensation threshold voltage distribution function of flash cell, wherein, each second post-compensation threshold voltage distribution
Function pair answers a second post-compensation threshold voltage window, and each in same second post-compensation threshold voltage window
The corresponding flash cell of two post-compensation threshold voltages has the second identical post-compensation threshold voltage distribution function.For example, programming
State is 8 states, is respectively 111,110,100,101,001,000,010 and 011.
Calculate and each one-to-one second distribution function parameter of second post-compensation threshold voltage distribution function；
It should be noted that in order to specifically determine each second post-compensation threshold voltage distribution function, it is necessary to calculate every
Second distribution function parameter of a second post-compensation threshold voltage distribution functionWherein, sp ∈ [111,110,
100th, 101,001,000,010,011], so as to obtain corresponding with each second post-compensation threshold voltage distribution function
Two distribution function parameters.
Specifically, can be according to gaussian kernel function (the 7th calculation formula and the 8th calculation formula) and each second post-compensation
Threshold voltage calculates and each one-to-one first distribution function parameter of second post-compensation threshold voltage distribution function.Its
In, the 7th calculation formula and the 8th calculation formula are respectively：
With
Wherein, N is the number of memory cells in each wordline,For Gaussian Profile kernel function.
According to being mended after each second distribution function parameter, each second post-compensation threshold voltage distribution function, each second
Threshold voltage, the average voltage of erase status and the corresponding judgement voltage of each programming state are repaid, is obtained and each flash cell
The one-to-one prior information of threshold voltage.
Specifically, determining the second distribution function corresponding with each second post-compensation threshold voltage distribution function
After parameter, you can determine the specific functional value of the second post-compensation threshold voltage distribution function, can specifically be calculated by the 9th public
Formula obtain with the one-to-one prior information X of the threshold voltage of each flash cell, wherein, the 9th calculation formula is：
Wherein,Represent to mend after the flash cell corresponding second that pth row, q are arranged
Repay threshold voltage,With
Represent that the second post-compensation threshold voltage in programming state 111,110,100,101,001,000,010 and 011 is distributed respectively
Function, XeRepresent the equal threshold voltage of erase status, X110、X100、X101、X001、X000、X010And X011Corresponding programming shape is represented respectively
The judgement voltage of state, each judgement voltage can be preset, and X (p, q) represents to correspond to positioned at the flash cell that pth row, q are arranged
Prior information.After prior information corresponding with each flash cell is calculated, each prior information can be carried out
Preserve, and when subsequently carrying out first round error-correcting decoding, the flash cell of decoding error is calculated using corresponding prior information
First interference strength of corresponding flash cell.
As a kind of preferred embodiment, this method can also comprise the following steps：
It is corresponding with each flash cell according to being obtained with the one-to-one first post-compensation threshold voltage of each flash cell
Each first post-compensation threshold voltage distribution function；Calculate a pair of with each first post-compensation threshold voltage distribution function one
The first distribution function parameter answered；
According to each first distribution function parameter and each corresponding first post-compensation threshold voltage distribution function to each
Each byte in flash cell carries out the second wheel error-correcting decoding, and determines bit error code rate according to decoding result.
It should be noted that after posterior information post-compensation is carried out to each flash cell, according to each first post-compensation
The corresponding first post-compensation threshold voltage window of threshold voltage is assured that out each correspondingly with each flash cell
First post-compensation threshold voltage distribution function, then each first post-compensation threshold voltage distribution function is to the every of each flash cell
A byte carries out the second wheel error-correcting decoding.Certainly, need at this time according to above-mentioned 7th calculation formula and the calculating of the 8th calculation formula
Go out the first distribution function parameter corresponding with each first post-compensation threshold voltage distribution function.Such as 3 grades of flash memories, can be with
The maximum likelihood ratio of each byte in each flash cell is calculated according to the following formula：
Wherein, Ltsb(p, q) represents the corresponding maximum of the 3rd byte being located in pth row, the flash cell that q is arranged seemingly
So ratio, Lmsb(p, q) represents the corresponding maximum likelihood ratio of second byte in the flash cell that pth row, q are arranged, Llsb
(p, q) represents the corresponding maximum likelihood ratio of first character section in the flash cell that pth row, q are arranged.
Calculated according to each first distribution function parameter and each corresponding first post-compensation threshold voltage distribution function
After going out the corresponding maximum likelihood ratio of each byte in each flash cell, the second wheel error-correcting decoding is carried out to each byte and is obtained
Decoded to each byte one-to-one each second, and the codeword sequence that still root prestores is compared, to determine
Which which correct byte decoding error of byte decoding, so as to obtain corresponding bit error code rate, so as to according to the bit
Error code rate judges whether to reach preset standard, to further determine that the degree eliminated to CCI interference, and can also be according to each
First post-compensation threshold voltage distribution function carries out posterior information post-compensation again, so as to preferably eliminate the base of CCI interference
On plinth further eliminate CCI interference, so as to get each post-compensation threshold voltage further close to the threshold after each programming
Threshold voltage, to further improve the data storing reliability of multi-level flash.
On the basis of above-described embodiment, the embodiment of the present invention provides a kind of signal processing device of multi-level flash accordingly
Put, specifically refer to Fig. 2, which includes：
First error-correcting decoding module 1, first round error correction is carried out to each byte in each flash cell in multi-level flash
Decoding, obtains decoding correspondingly with each byte；
Comparison module 2, is compared for will be decoded correspondingly with each byte with the codeword sequence prestored,
To determine whether each byte decodes correctly；
Judgment module 3, for judging all bytes in z-th of flash cell, whether decoding is correct, if it is, the
Z flash cell is successfully decoded, and triggers the first computing module 4；Otherwise, z-th of flash cell decoding failure, and trigger acquisition
Module 5；Wherein, z ∈ Z, Z are the flash cell sum in multi-level flash；
First computing module 4, for calculating posteriority letter corresponding with z-th of flash cell according to the first calculation relational expression
Breath；Wherein, the first calculation relational expression isWherein, XeFor the equal threshold voltage of erase status, XspTo program shape
Judgement voltage under state sp, Δ VppFor program voltage section；
Acquisition module 5, for from it is precalculating, with being obtained in the one-to-one prior information of each flash cell
Prior information corresponding with z-th of flash cell；
Second computing module 6, for according to the successfully decoded one-to-one posterior information of each flash cell and with
The one-to-one prior information of each flash cell of decoding failure calculates dry with each flash cell one-to-one first
Disturb intensity；
Compensating module 7, after being carried out according to each first interference strength to the corresponding threshold voltage of corresponding flash cell
Information post-compensation is tested, to obtain and the one-to-one first post-compensation threshold voltage of each flash cell；Each flash cell one
One corresponding threshold voltage reads obtain in advance.
Optionally, the first error-correcting decoding module 1 includes：
Acquiring unit, for obtaining each threshold voltage distribution letter corresponding with each flash cell in multi-level flash
Number；
Computing unit, dodges for being calculated according to threshold voltage distribution function corresponding with each flash cell with corresponding
The one-to-one maximum likelihood ratio of each byte in memory cell；
Decoding unit, for entangling according to comparing each byte with the one-to-one maximum likelihood of each byte and carry out the first round
Mistranslation code, obtains decoding correspondingly with each byte in each flash cell.
Optionally, the calculating process with the one-to-one prior information of each flash cell is：
Calculated and each flash cell one according to the read in advance and one-to-one threshold voltage of each flash cell
One corresponding second interference strength；
According to each second interference strength to the corresponding threshold voltage of corresponding flash cell carry out post-compensation, with obtain with often
A one-to-one second post-compensation threshold voltage of flash cell；
It is corresponding with each flash cell according to being obtained with the one-to-one second post-compensation threshold voltage of each flash cell
The second post-compensation threshold voltage distribution function；
Calculate and each one-to-one second distribution function parameter of second post-compensation threshold voltage distribution function；
According to being mended after each second distribution function parameter, each second post-compensation threshold voltage distribution function, each second
Threshold voltage, the average voltage of erase status and the corresponding judgement voltage of each programming state are repaid, is obtained and each flash cell
The one-to-one prior information of threshold voltage.
It should be noted that the embodiment of the present invention has beneficial effect same as the previously described embodiments, for of the invention real
Specific introduce for applying the signal processing method of multi-level flash involved in example refer to above method embodiment, and the application exists
This is repeated no more.
On the basis of above-described embodiment, an embodiment of the present invention provides a kind of signal handling equipment of multi-level flash, bag
Include：
Memory, for storing computer program；
Processor, the step of signal processing method such as above-mentioned multi-level flash is realized during for performing computer program.
It should be noted that the embodiment of the present invention has beneficial effect same as the previously described embodiments, for of the invention real
Specific introduce for applying the signal processing method of multi-level flash involved in example refer to above method embodiment, and the application exists
This is repeated no more.
On the basis of above-described embodiment, an embodiment of the present invention provides a kind of computer-readable recording medium, computer
Computer program is stored with readable storage medium storing program for executing, the letter such as above-mentioned multi-level flash is realized when computer program is executed by processor
The step of number processing method.
It should be noted that the embodiment of the present invention has beneficial effect same as the previously described embodiments, for of the invention real
Specific introduce for applying the signal processing method of multi-level flash involved in example refer to above method embodiment, and the application exists
This is repeated no more.
It should also be noted that, in the present specification, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or order.Moreover, term " comprising ", "comprising" or its any other variant meaning
Covering non-exclusive inclusion, so that process, method, article or equipment including a series of elements not only include that
A little key elements, but also including other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic key element of equipment.In the absence of more restrictions, the key element limited by sentence "including a ...", is not arranged
Except also there are other identical element in the process, method, article or apparatus that includes the element.
The foregoing description of the disclosed embodiments, enables professional and technical personnel in the field to realize or use the present invention.
A variety of modifications to these embodiments will be apparent for those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, it is of the invention
The embodiments shown herein is not intended to be limited to, and is to fit to and the principles and novel features disclosed herein phase one
The most wide scope caused.
Claims (10)
- A kind of 1. signal processing method of multi-level flash, it is characterised in that including：S11：First round error-correcting decoding is carried out to each byte in each flash cell in multi-level flash, is obtained and each described Byte decodes correspondingly；S12：It is compared being decoded correspondingly with each byte with the codeword sequence prestored, it is each to determine Whether the byte decodes correctly；S13：It is correct to judge whether all bytes in z-th of flash cell decode, if it is, z-th of flash memory list Member is successfully decoded, and enters S14；Otherwise, z-th of flash cell decoding failure, and enter S15；Wherein, z ∈ Z, Z are institute State the flash cell sum in multi-level flash；S14：Posterior information corresponding with z-th of flash cell is calculated according to the first calculation relational expression；Wherein, the first meter Calculating relational expression isWherein, XeFor the equal threshold voltage of erase status, XspFor the judgement electricity under programming state sp Pressure, Δ VppFor program voltage section；S15：Obtained and the z from precalculate and each one-to-one prior information of flash cell The corresponding prior information of a flash cell；S16：According to each flash memory with the successfully decoded one-to-one posterior information of each flash cell and with decoding failure The one-to-one prior information of unit calculates and each one-to-one first interference strength of flash cell；S17：Mended after carrying out posterior information to the corresponding threshold voltage of corresponding flash cell according to each first interference strength Repay, to obtain and each one-to-one first post-compensation threshold voltage of flash cell；Each flash cell is one by one Corresponding threshold voltage reads obtain in advance.
- 2. the signal processing method of multi-level flash according to claim 1, it is characterised in that described to each in multi-level flash Each byte in a flash cell carries out first round error-correcting decoding, obtains the mistake decoded correspondingly with each byte Journey includes：S111：Obtain each threshold voltage distribution function corresponding with each flash cell in multi-level flash；S112：According to threshold voltage distribution function corresponding with each flash cell calculate with corresponding flash cell The one-to-one maximum likelihood ratio of each byte；S113：First round error-correcting decoding is carried out according to each byte is compared with each one-to-one maximum likelihood of byte, Obtain decoding correspondingly with each byte in each flash cell.
- 3. the signal processing method of multi-level flash according to claim 2, it is characterised in that described and each flash memory The calculating process of the one-to-one prior information of unit is：Calculated and each flash memory list according to one-to-one threshold voltage of flash cell read in advance and each One-to-one second interference strength of member；According to each second interference strength to the corresponding threshold voltage of corresponding flash cell carry out post-compensation, with obtain with often A one-to-one second post-compensation threshold voltage of the flash cell；Obtained and each flash cell according to each one-to-one second post-compensation threshold voltage of flash cell Corresponding second post-compensation threshold voltage distribution function；Calculate and each one-to-one second distribution function parameter of second post-compensation threshold voltage distribution function；According to each second distribution function parameter, each second post-compensation threshold voltage distribution function, each described Second post-compensation threshold voltage, the average voltage of erase status and the corresponding judgement voltage of each programming state, obtain with each The one-to-one prior information of threshold voltage of the flash cell.
- 4. the signal processing method of multi-level flash according to claim 3, it is characterised in that described to calculate and each institute The process for stating the second one-to-one second distribution function parameter of post-compensation threshold voltage distribution function is：Calculated and each second post-compensation threshold value according to gaussian kernel function and each second post-compensation threshold voltage One-to-one first distribution function parameter of voltage distribution functions.
- 5. the signal processing method of multi-level flash according to claim 1, it is characterised in that further include：Obtained and each flash cell according to each one-to-one first post-compensation threshold voltage of flash cell Corresponding each first post-compensation threshold voltage distribution function；Calculate and each one-to-one first distribution function parameter of first post-compensation threshold voltage distribution function；According to each first distribution function parameter and each corresponding 3rd post-compensation threshold voltage distribution function to each Each byte in flash cell carries out the second wheel error-correcting decoding, and determines bit error code rate according to decoding result.
- A kind of 6. signal processing apparatus of multi-level flash, it is characterised in that including：First error-correcting decoding module, first round error-correcting decoding is carried out to each byte in each flash cell in multi-level flash, Obtain decoding correspondingly with each byte；Comparison module, is compared for will be decoded correspondingly with each byte with the codeword sequence prestored, To determine whether each byte decodes correctly；Judgment module, for judging all bytes in z-th of flash cell, whether decoding is correct, if it is, the z A flash cell is successfully decoded, and triggers the first computing module；Otherwise, z-th of flash cell decoding failure, and trigger and obtain Modulus block；Wherein, z ∈ Z, Z are the flash cell sum in the multi-level flash；First computing module, for according to the first calculation relational expression calculate it is corresponding with z-th of flash cell after Test information；Wherein, the first calculation relational expression isWherein, XeFor the equal threshold voltage of erase status, XspTo compile Judgement voltage under journey state sp, Δ VppFor program voltage section；The acquisition module, for from precalculate and each one-to-one prior information of flash cell Obtain prior information corresponding with z-th of flash cell；Second computing module, for being lost according to the successfully decoded one-to-one posterior information of each flash cell and with decoding The one-to-one prior information of each flash cell lost calculates and each one-to-one first interference of flash cell Intensity；Compensating module, for carrying out posteriority to the corresponding threshold voltage of corresponding flash cell according to each first interference strength Information post-compensation, to obtain and each one-to-one first post-compensation threshold voltage of flash cell；Each flash memory The one-to-one threshold voltage of unit reads obtain in advance.
- 7. the signal processing apparatus of multi-level flash according to claim 6, it is characterised in that the first error-correcting decoding mould Block includes：Acquiring unit, for obtaining each threshold voltage distribution function corresponding with each flash cell in multi-level flash；Computing unit, dodges for being calculated according to threshold voltage distribution function corresponding with each flash cell with corresponding The one-to-one maximum likelihood ratio of each byte in memory cell；Decoding unit, for entangling according to comparing each byte with each one-to-one maximum likelihood of byte and carry out the first round Mistranslation code, obtains decoding correspondingly with each byte in each flash cell.
- 8. the signal processing apparatus of multi-level flash according to claim 7, it is characterised in that described and each flash memory The calculating process of the one-to-one prior information of unit is：Calculated and each flash memory list according to one-to-one threshold voltage of flash cell read in advance and each One-to-one second interference strength of member；According to each second interference strength to the corresponding threshold voltage of corresponding flash cell carry out post-compensation, with obtain with often A one-to-one second post-compensation threshold voltage of the flash cell；Obtained and each flash cell according to each one-to-one second post-compensation threshold voltage of flash cell Corresponding second post-compensation threshold voltage distribution function；Calculate and each one-to-one second distribution function parameter of second post-compensation threshold voltage distribution function；According to each second distribution function parameter, each second post-compensation threshold voltage distribution function, each described Second post-compensation threshold voltage, the average voltage of erase status and the corresponding judgement voltage of each programming state, obtain with each The one-to-one prior information of threshold voltage of the flash cell.
- A kind of 9. signal handling equipment of multi-level flash, it is characterised in that including：Memory, for storing computer program；Processor, the letter of the multi-level flash as described in claim 1 to 5 any one is realized during for performing the computer program The step of number processing method.
- 10. a kind of computer-readable recording medium, it is characterised in that be stored with computer on the computer-readable recording medium Program, realizes the signal of the multi-level flash as described in claim 1 to 5 any one when the computer program is executed by processor The step of processing method.
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