CN108037965B

CN108037965B - Method and device for reading and writing target chip

Info

Publication number: CN108037965B
Application number: CN201711469102.8A
Authority: CN
Inventors: 陆舟; 于华章
Original assignee: Feitian Technologies Co Ltd
Current assignee: Feitian Technologies Co Ltd
Priority date: 2017-12-29
Filing date: 2017-12-29
Publication date: 2021-01-01
Anticipated expiration: 2037-12-29
Also published as: CN108037965A

Abstract

The invention relates to the field of intelligent cards, in particular to a method and a device for reading and writing a target chip, wherein the method comprises the following steps: a method for writing data to be written into a write address of a target chip by a main control chip and a method for reading data from a read address of the target chip by the main control chip; the main control chip is added in the device, and the upper computer reads and writes the target chip through the main control chip, so that external reading and writing equipment is not needed, and the cost is reduced; the target chip only needs to reserve one clock port and one data port, the main control chip can operate the target chip, only three registers in the target chip need to be operated, the occupied memory is small, and the complex operations of firmware upgrading can be completed.

Description

Method and device for reading and writing target chip

Technical Field

The invention relates to the field of smart cards, in particular to a method and a device for reading and writing a target chip.

Background

In the prior art, when an upper computer executes an operation of reading and writing a target chip in a device, the device is required to reserve a port, and the upper computer needs to execute the operation of reading and writing the target chip through an external reading and writing device, for example, when firmware of an ARM chip in the device needs to be upgraded, the device is required to reserve a plurality of data ports for upgrading operation; moreover, many devices such as FIDO devices and bluetooth devices need to upgrade their internal chips through an external firmware programming device when performing firmware upgrade operations, which is complicated in operation and high in cost.

Disclosure of Invention

To solve the above problems, according to an aspect of the present invention, a method and an apparatus for reading and writing a target chip are provided;

the invention provides a method for reading and writing a target chip, which comprises the following steps: a method for writing data to be written into a write address of a target chip by a main control chip and a method for reading data from a read address of the target chip by the main control chip;

the method for writing the data to be written into the write address of the target chip by the main control chip comprises the following steps:

step A1, the main control chip organizes the command of writing address register and sends the command of writing address register to the target chip;

step A2, the main control chip judges whether the confirmation response sent by the target chip is received, if yes, step A3 is executed, otherwise, the process is ended;

step A3, the main control chip sends the write address to the target chip;

step A4, the main control chip organizes the write-read-write register command and sends the write-read-write register command to the target chip;

step A5, the main control chip judges whether the confirmation response sent by the target chip is received, if yes, step A6 is executed, otherwise, the process is ended;

step A6, the main control chip sends the data to be written to the target chip;

the method for reading data from the reading address of the target chip by the main control chip comprises the following steps:

step B1, the main control chip organizes the write address register command and sends the write address register command to the target chip;

step B2, the main control chip judges whether the confirmation response sent by the target chip is received, if yes, step B3 is executed, otherwise, the process is ended;

step B3, the main control chip sends the read address to the target chip;

b4, the main control chip organizes the read-write register command and sends the read-write register command to the target chip;

step B5, the main control chip judges whether the confirmation response sent by the target chip is received, if yes, step B6 is executed, otherwise, the process is ended;

and step B6, the main control chip receives the data returned by the target chip.

The invention also provides a device for reading and writing a target chip, which comprises: a read data module and a write data module;

the write data module includes:

the first organization command submodule is used for organizing a write address register command;

the first sending submodule is used for sending the write address register command organized by the first organization command submodule to a target chip;

the first judgment submodule is used for judging whether a confirmation response sent by the target chip is received or not after the first sending submodule sends the address register writing command to the target chip;

the first termination submodule is used for terminating when the first judgment submodule judges that the confirmation response sent by the target chip is not received;

the first sending submodule is also used for sending the write-in address to the target chip when the first judging submodule judges that the confirmation response sent by the target chip is received;

the second organization command submodule is used for organizing a write-read-write register command after the first sending submodule sends a write address to the target chip;

the first sending submodule is also used for sending the read-write register command organized by the second organization command submodule to a target chip;

the second judgment submodule is used for judging whether a confirmation response sent by the target chip is received or not after the first sending submodule sends a read-write register command to the target chip;

the first sending submodule is also used for sending the data to be written to the target chip when the second judging submodule judges that the confirmation response sent by the target chip is received;

the first termination submodule is also used for terminating when the second judgment submodule judges that the confirmation response sent by the target chip is not received;

the data reading module comprises:

the third organization command submodule is used for organizing the write address register command;

the second sending submodule is used for sending the write address register command organized by the third organization command submodule to the target chip;

the third judgment submodule is used for judging whether a confirmation response sent by the target chip is received or not when the second sending submodule sends the address register writing command to the target chip;

the second ending submodule is used for ending when the third judging submodule judges that the confirmation response sent by the target chip is not received;

the second sending submodule is also used for sending a reading address to the target chip after the third judging submodule judges that the confirmation response sent by the target chip is received;

the fourth organization command submodule is used for organizing the read-write register command after the second sending submodule sends the read address to the target chip;

the second sending submodule is also used for sending the read-write register command organized by the fourth organization command submodule to the target chip;

the fourth judgment submodule is used for judging whether a confirmation response sent by the target chip is received or not after the second sending submodule sends a read-write register command to the target chip;

the first receiving submodule is also used for receiving data returned by the target chip when the fourth judging submodule judges that the confirmation response sent by the target chip is received;

and the second ending submodule is also used for ending when the fourth judging submodule judges that the acknowledgement response sent by the target chip is not received.

The invention has the beneficial effects that: the main control chip is added in the device, and the upper computer reads and writes the target chip through the main control chip, so that external reading and writing equipment is not needed, and the cost is reduced; the target chip only needs to reserve one clock port and one data port, the main control chip can operate the target chip, only three registers in the target chip need to be operated, the occupied memory is small, and the complex operations of firmware upgrading can be completed.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 to fig. 2 are flowcharts of a method for reading and writing a target chip according to embodiment 1 of the present invention;

fig. 3 to fig. 5 are flowcharts of a firmware upgrading method according to embodiment 2 of the present invention;

fig. 6 is a block diagram of an apparatus for reading from and writing to a target chip according to embodiment 3 of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example 1

The embodiment provides a method for reading and writing a target chip, which comprises the following steps: a method for writing data to be written into a write address of a target chip by a main control chip and a method for reading data from a read address of the target chip by the main control chip;

the method for writing the data to be written into the write address of the target chip by the main control chip, referring to fig. 1, includes:

step A3, the main control chip sends the write address to the target chip;

step A6, the main control chip sends the data to be written to the target chip;

optionally, step a4 is preceded by:

step 101, setting a self-increasing mode with a preset length as a current self-increasing mode by a main control chip;

and 102, executing an operation of configuring an address register on the target chip by the main control chip, and configuring the address register into a current self-increment mode.

Further, after step 102, step a4 further includes: the main control chip takes the length of the target data as an initial value of the current length, and sequentially obtains data with preset length from the target data as data to be written;

it should be noted that, before step a1, the method further includes: the main control chip receives a data writing command sent by the upper computer, and acquires target data and a writing address from the data writing command or acquires the target data and a preset writing address from the data writing command.

Correspondingly, step a6 is followed by: the main control chip updates the current length, judges whether the current length is a preset value or not, and if yes, the writing operation is finished; otherwise, sequentially acquiring data with preset length from the target data as the current data to be written.

Alternatively, step a4 is preceded by:

step 201, the main control chip takes the target data length as an initial value of the current length;

further, step a1 is preceded by: the main control chip receives a data writing command sent by the upper computer, and acquires target data and a writing address from the data writing command or acquires the target data and a preset writing address from the data writing command.

Step 202, the main control chip selects a self-increment mode according to the current length, and the selected self-increment mode is used as the current self-increment mode; the main control chip executes the operation of configuring the address register to the target chip and configures the address register into a current self-increment mode;

step 203, the main control chip sequentially acquires data with the length matched with the current self-increment mode from the target data as data to be written;

correspondingly, step a6 is followed by: the main control chip updates the current length, judges whether the current length is a preset value or not, and if yes, the writing operation is finished; otherwise, the procedure returns to step 202.

Furthermore, after the main control chip determines that the current length is not the preset value, the method further includes: and the main control chip judges whether the address register needs to be reconfigured according to the current length, if so, the step 202 is returned, and if not, the step 203 is returned.

It should be noted that, the main control chip executes the operation of configuring the address register to the target chip, and configures the address register to be in the current self-increment mode, which specifically includes:

301, the main control chip organizes a write configuration register command and sends the write configuration register command to a target chip;

step 302, the main control chip judges whether a confirmation response sent by the target chip is received, if so, step 303 is executed, otherwise, the process is ended;

step 303, the main control chip sends the configuration information of the address register to the target chip; the configuration information of the address register is used for configuring the address register to be in the current self-increment mode.

Preferably, step a1 is preceded by:

step C1, the main control chip receives the selection command sent by the upper computer, acquires and stores the target chip identification from the selection command, and returns a successful selection response to the upper computer;

and step C2, the main control chip receives a command for establishing the secure channel sent by the upper computer, and the secure channel is established by the target chip corresponding to the target chip identification.

More specifically, the method for writing the data to be written into the write address of the target chip by the main control chip specifically includes:

step A1 is that the main control chip organizes the write address register command, sets the data port as the output mode, and sends the write address register command to the target chip through the data port;

step A2 specifically includes that the main control chip sets a data port as an input mode and judges whether a confirmation response sent by the target chip is received, if yes, step A3 is executed, and if not, the step is ended;

step A3 is that the main control chip sets a data port as an output mode, and sends the address of the data to be written in the target chip to the target chip through the data port;

step A4 is that the main control chip organizes the write-read-write register command and sends the write-read-write register command to the target chip;

step a5 specifically includes that the main control chip sets the data port as an input mode, and determines whether a confirmation response sent by the target chip is received, if yes, step a6 is executed, otherwise, the process is ended;

step a6 is specifically that the main control chip sets the data port as an output mode, and sends the data to be written to the target chip through the data port.

Preferably, step a1 is preceded by: the main control chip executes the operation of acquiring the state of the nonvolatile memory of the target chip; and judging the state of the nonvolatile memory returned by the target chip, executing the step A1 when the state of the nonvolatile memory is in a ready state, and returning to continuously execute the operation of the main control chip for acquiring the state of the nonvolatile memory of the target chip when the state of the nonvolatile memory is in a non-ready state.

Further, the operation of the main control chip to acquire the state of the nonvolatile memory of the target chip specifically includes:

step 401, the master control chip organizes a write address register command and sends the write address register command to a target chip;

step 402, the main control chip judges whether a confirmation response sent by the target chip is received, if so, step 403 is executed, otherwise, the process is finished;

step 403, the main control chip sends the address of the nonvolatile memory control register to the target chip;

step 404, the main control chip organizes a read-write register command and sends the read-write register command to a target chip;

step 405, the main control chip judges whether a confirmation response sent by the target chip is received, if yes, step 406 is executed, otherwise, the process is ended;

and step 406, the main control chip receives the nonvolatile memory state returned by the target chip, and executes step a1 when the nonvolatile memory state is the ready state, otherwise, continues to wait, and executes step 404.

Preferably, step a1 is preceded by: and the main control chip resets the target chip.

Furthermore, the resetting of the target chip by the main control chip specifically comprises: the main control chip sets the data port as an output mode, and continuously sends preset levels of preset periods on the data port.

Preferably, step a1 is preceded by: the main control chip controls the target chip to be powered on;

the main control chip controls the target chip to be electrified specifically comprises the following steps:

d1, the main control chip organizes the write control register command and sends the write control register command to the target chip;

d2, the main control chip judges whether the confirmation response sent by the target chip is received, if yes, the step D3 is executed, otherwise, the operation is finished;

and D3, the main control chip sends the preset value to the target chip.

Preferably, step D3 is followed by:

e1, the main control chip organizes the read control register command and sends the read control register command to the target chip;

e2, the main control chip judges whether the confirmation response sent by the target chip is received, if yes, the step E3 is executed, otherwise, the exception is thrown out;

and E3, the main control chip receives the read control register response sent by the target chip, judges whether the power-on is successful according to the read control register response, if so, the power-on is successful, otherwise, the step E1 is returned.

The present embodiment further provides a method for reading data from a read address of a target chip by a master control chip, and the method includes, with reference to fig. 2:

step B3, the main control chip sends the read address to the target chip;

Preferably, step B4 is preceded by:

step 501, setting a self-increment mode with a preset length as a current self-increment mode by a main control chip;

step 502, the main control chip executes the operation of configuring the address register to the target chip, and configures the address register to be in the current self-increment mode.

Optionally, step B4 is preceded by: the main control chip takes a preset reading length as an initial value of the current length;

correspondingly, step B6 is followed by: the main control chip updates the current length according to the self-increasing mode of the preset length, judges whether the current length is the preset value or not, and if yes, the reading operation is finished; otherwise, return to step B4.

Alternatively, step B4 is preceded by:

601, the main control chip takes a preset reading length as an initial value of the current length;

step 602, the main control chip selects a self-increment mode according to the current length, and the selected self-increment mode is used as the current self-increment mode; the main control chip executes the operation of configuring the address register to the target chip and configures the address register into a current self-increment mode;

correspondingly, step B6 is followed by: the main control chip updates the current length according to the current self-increment mode, judges that the current length is a preset value, if yes, returns to the step 602; otherwise the read operation ends.

Preferably, after the main control chip determines that the current length is not the preset value, the method further includes: and the main control chip judges that the address registers need to be reconfigured according to the current length, if so, the step 602 is returned, and if not, the step B4 is returned.

Further, the main control chip executes an operation of configuring the address register to the target chip, and configures the address register to be in the current self-increment mode, which specifically includes:

701, organizing a write configuration register command by a main control chip, and sending the write configuration register command to a target chip;

step 702, the main control chip judges whether a confirmation response sent by the target chip is received, if so, step 703 is executed, otherwise, the process is ended;

step 703, the main control chip sends the configuration information of the address register to the target chip; the configuration information of the address register is used for configuring the address register to be in the current self-increment mode.

The method for reading data from the reading address of the target chip by the main control chip specifically comprises the following steps:

the step B1 specifically includes: the main control chip organizes a write address register command, sets a data port as an output mode, and sends the write address register command to a target chip through the data port;

the step B2 specifically includes: the main control chip sets the data port as an input mode, and judges whether a confirmation response sent by the target chip is received, if so, the step B3 is executed, otherwise, the operation is finished;

the step B3 specifically includes: the master control chip sets a data port as an output mode and sends an address of data to be written in a target chip to the target chip through the data port;

the step B4 specifically includes: the main control chip organizes a read-write register command and sends the read-write register command to a target chip through a data port;

the step B5 specifically includes: the main control chip sets the data port as an input mode, judges whether a confirmation response sent by the target chip is received, if so, executes the step B6, otherwise, ends;

the step B6 specifically includes: and the main control chip receives the data returned by the target chip.

Preferably, step B1 is preceded by: the main control chip executes the operation of acquiring the state of the nonvolatile memory of the target chip; and judging the state of the nonvolatile memory returned by the target chip, executing the step B1 when the state of the nonvolatile memory is in a ready state, and returning to continuously execute the operation of acquiring the state of the nonvolatile memory of the target chip by the main control chip when the state of the nonvolatile memory is in a non-ready state.

Further, the operation of the main control chip to acquire the state of the nonvolatile memory of the target chip specifically includes steps 401 to 406;

preferably, step B1 is preceded by: and the main control chip resets the target chip.

Preferably, step B1 is preceded by: the main control chip controls the target chip to be powered on;

and D3, the main control chip sends the preset value to the target chip.

Preferably, step D3 is followed by:

Example 2

This embodiment provides a flowchart of a firmware upgrading method, where a device includes a main control chip and a target chip, as shown in fig. 3 to 5, and the method includes:

step 101, powering on a main control chip;

102, receiving an APDU command sent by an upper computer by a main control chip, and judging the command type; when the received APDU command is a selection command, execute step 103; when the received APDU command is a command for establishing a secure channel, execute step 106; when the received APDU command is a firmware upgrade command, execute step 107;

in this embodiment, the APDU command format is: CLA + INS + P1+ P2+ Lc + Data; CLA is the category byte of the command, INS is the instruction byte of the command, P1 and P2 are parameters, Lc is the length of Data in the command, and Data is Data;

the selection command received in this embodiment is: 0X 00A 40400 + LC + DATA

The command for establishing the secure channel is as follows: 0X 8050000008 + DATA

The firmware upgrading command is as follows: 0X 80BA 0100 LC + DATA

The main control chip receives an APDU command sent by an upper computer, and the judgment command type specifically comprises the following steps: reading an instruction byte of the APDU command to determine a command type, wherein the command type is a selection command when the instruction byte of the command is 0X A4, the command type is a firmware upgrade command when the instruction byte of the command is 0X BA, and the command type is a command for establishing a secure channel when the instruction byte of the command is 0X 50;

103, the main control chip acquires a target chip identifier from the selection command;

in this embodiment, the selection command specifically includes: 0X 00a 40400081122334455667788; the main control chip acquires a Data part from the selection command as a target chip identifier, and specifically comprises the following steps: 0X 1122334455667788;

step 104, the main control chip judges whether a peripheral chip corresponding to the target chip identification exists, if so, the peripheral chip corresponding to the target chip identification is used as the target chip, step 105 is executed, otherwise, error processing is carried out;

105, initializing a data port by a main control chip, and setting a firmware upgrading identification position; returning to the step 102;

106, establishing a safety channel between the main control chip and the target chip; returning to the step 102;

step 107, the main control chip judges whether the firmware upgrading identification position is set, if so, step 108 is executed, otherwise, error processing is performed;

step 108, the main control chip judges whether a safety channel is established with the target chip, if so, step 109 is executed, otherwise, error processing is carried out;

it should be noted that the error processing in step 107 and step 108 may be ending of error reporting, or returning to step 102;

step 109, the main control chip judges whether the received firmware upgrading command is the first block, if so, step 110 is executed, otherwise, step 116 is executed;

step 110, initializing a target chip by a main control chip;

and step 111, the main control chip executes the operation of reading the state of the nonvolatile memory of the target chip.

Specifically, referring to fig. 2, step 111 specifically includes:

step 111-1, the main control chip organizes a write address register command, sets a data port to be in an output mode, and sends the write address register command to a target chip through the data port;

it should be noted that the commands for the main control chip to operate the register in the target chip are all SWD commands, and the SWD commands specifically include: start + APnDP + RnW + A [ 2: 3] + Party + Stop, wherein Start is a Start bit, APnDP is the register type of the current operation, and when APnDP is 0, the register of the current operation is a DP register; when APnDP is 1, indicating that the register currently operated is an AP register; RnW is the current operation type, when RnW is 1 indicates the current operation is a read operation; when RnW is 0, it indicates that the current operation is a write operation; a [ 2: 3 is the register address of the current operation; parity is APnDP + RnW + a [ 2: 3 ]; STOP: a stop bit fixed to 0; park is that the complement bit is always 1;

in this embodiment, the command for organizing the write address register by the main control chip specifically includes: the main control chip sequentially splices the address register type 1, the current operation type, namely the write operation 0, and the address 01 of the address register, obtains the parity bit 0 according to the splicing result, and sequentially splices the start bit 1, the address register type 1, the current operation type, namely the write operation 0, the address 01 of the address register, the parity bit 0, the stop bit 0, and the supplement bit 1 to obtain a write address register command 11001001.

It should be noted that, the clock port of the main control chip is always at a high level when not receiving and transmitting data;

in this embodiment, the sending, by the main control chip, the write address register command to the target chip through the data port specifically includes:

step R1, the master control chip sets the clock port to low level, sequentially obtains one bit of data from the command of the write address register as the current data, sets the data port according to the current data, and lasts for a preset time;

in more detail, the data port is set to a high level when the current data is "1", and the data port is set to a low level when the current data is "0";

and step R2, the main control chip judges whether the write address register command contains data which is not acquired, if yes, the clock port is set to be at high level, the preset time is continued, the step R1 is returned, and if not, the clock port is set to be at high level.

Step 111-2, the main control chip sets the data port as an input mode, judges whether to receive a confirmation response sent by the target chip, if so, executes step 111-3, otherwise, throws out an exception;

specifically, when the confirmation response received by the main control chip is 001, the operation is successful, otherwise, the operation is failed;

preferably, step 111-1 is preceded by: the main control chip sets an initial value of the number of times of sending the command of writing the address register.

Correspondingly, in step 111-2, after the main control chip does not receive the acknowledgement response sent by the target chip, the method further includes: the main control chip updates the frequency of sending the write address register command, judges whether the frequency of sending the write address register command is greater than the preset frequency, if so, throws the exception, otherwise, returns to the step 111-1;

step 111-3, the main control chip sets the data port to be in an output mode and sends the address of the nonvolatile memory control register to the target chip through the data port;

in this embodiment, the address of the nonvolatile memory control register is specifically: 0x 10000010;

111-4, the main control chip organizes a read-write register command, sets the data port to be in an output mode, and sends the read-write register command to the target chip through the data port;

in this embodiment, the main control chip organizes the read/write register command specifically as follows: the main control chip sequentially splices the read-write register type 1, the current operation type, namely the read operation 1, and the address 01 of the read-write register, obtains the parity bit 0 according to the splicing result, and sequentially splices the start bit 1, the read-write register type 1, the current operation type, namely the read operation 1, the address 11 of the read-write register, the parity bit 0, the stop bit 0, and the supplement bit 1 to obtain a read-write register command 11111001.

Step 111-5, the main control chip sets the data port as an input mode, judges whether to receive a confirmation response sent by the target chip, if so, executes step 111-6, otherwise, throws out an exception;

111-6, the main control chip receives the state that the target chip returns to the nonvolatile memory;

step 112, the main control chip judges the state of the nonvolatile memory returned by the target chip, when the state of the nonvolatile memory is a preparation state, step 113 is executed, and when the state of the nonvolatile memory is a non-preparation state, step 111 is returned;

step 113, the main control chip organizes the write address register command, sets the data port as an output mode, and sends the write address register command to the target chip through the data port;

in this embodiment, the process that the main control chip sends the write address register command to the target chip through the data port is similar to the steps R1-R2 and is not repeated here;

step 114, the main control chip sets the data port as an input mode, judges whether to receive a confirmation response sent by the target chip, if so, executes step 113, otherwise, performs error processing;

preferably, step 113 further comprises: the main control chip sets an initial value of the number of times of sending the command of writing the address register.

Correspondingly, in step 114, after the main control chip does not receive the acknowledgement response sent by the target chip, the method further includes: the main control chip updates the frequency of sending the write address register command, judges whether the frequency of sending the write address register command is greater than the preset frequency, if so, throws an exception, otherwise, returns to the step 113;

step 115, the main control chip sets the data port to be in an output mode and sends the initial address of the nonvolatile memory to the target chip through the data port;

step 116, the main control chip acquires firmware upgrading data from the firmware upgrading command, and takes the length of the firmware upgrading data as the current length;

step 117, the main control chip selects a self-increment mode according to the current length, and takes the selected self-increment mode as the current self-increment mode;

in the embodiment, three selectable increasing modes are provided, namely an 8-bit increasing mode, a 16-bit increasing mode and a 32-bit increasing mode; when the current length is not more than 16 bits, an 8-bit auto-increment mode is selected; when the current length is not less than 16 bits and not more than 32 bits, selecting a 16-bit auto-increment mode; when the current length is not less than 32 bits, selecting a 32-bit auto-increment mode;

for example, when the current length is 15 bits, an 8-bit auto-increment mode is selected;

step 118, the main control chip executes the operation of configuring the address register, and configures the address register into the current self-increment mode.

Specifically, step 118 specifically includes:

step 118-1, the main control chip organizes a write configuration register command, sets the data port to be in an output mode, and sends the write configuration register command to the target chip through the data port;

specifically, in this embodiment, the command for organizing the write configuration register by the main control chip specifically includes: the main control chip sequentially splices the configuration register type 1, the current operation type, namely the write operation 0, and the address 01 of the configuration register, obtains the parity check bit 0 according to the splicing result, and sequentially splices the start bit 1, the configuration register type 1, the current operation type, namely the write operation 0, the address 00 of the configuration register, the parity check bit 1, the stop bit 0, and the supplement bit 1 to obtain a write configuration register command 11000101.

Step 118-2, the main control chip sets the data port as an input mode, judges whether to receive a confirmation response sent by the target chip, if so, executes step 118-3, otherwise, throws out an exception;

specifically, when the main control chip receives 001, executing step 118-3, otherwise, throwing the exception;

step 118-3, the main control chip sends the configuration information of the address register to the target chip, wherein the configuration information of the address register is the information for configuring the address register into an 8-bit self-increment mode;

specifically, the configuration information is specifically: 0x 23000050;

preferably, step 118-1 is preceded by: the main control chip sets an initial value of the times of writing the configuration register command;

correspondingly, after the master chip does not receive the acknowledgement response sent by the target chip in step 118-2, the method further includes: the main control chip updates the times of sending the write configuration register, judges whether the times of sending the write configuration register command is larger than the preset times, if so, throws the exception, otherwise, returns to the step 118-1;

step 119, the main control chip sequentially acquires data with the length matched with the current self-increment mode from the data to be written as the current data to be written;

step 120, the main control chip organizes the write-read-write register command, sets the data port as an output mode, and sends the write-read-write register command to the target chip through the data port;

in this embodiment, the main control chip organizes the write/read register command specifically as follows: the main control chip sequentially splices the read-write register type 1, the current operation type, namely the write operation 0, and the address 11 of the read-write register, obtains the parity bit 1 according to the splicing result, and sequentially splices the start bit 1, the read-write register type 1, the current operation type, namely the write operation 0, the address 11 of the read-write register, the parity bit 1, the stop bit 0, and the supplement bit 1 to obtain a write-read-write register command 11011101.

Step 121, the main control chip sets the data port as an input mode, and judges whether to receive a confirmation response sent by the target chip, if yes, step 122 is executed, otherwise, error processing is performed;

preferably, step 120 further comprises: the main control chip sets an initial value of the times of writing and reading the register commands;

correspondingly, in step 121, the main control chip updates the number of times of sending the write-read-write register command, and judges whether the number of times of sending the write-read-write register command is greater than a preset number of times, if so, the exception is thrown out, otherwise, the step 120 is returned to;

step 122, the main control chip sets the data port to be in an output mode, and sends the data to be written to the target chip through the data port;

step 123, the main control chip updates the cyclic redundancy code according to the data to be written;

step 124, the main control chip updates the current length, judges whether the current length is 0, if yes, step 126 is executed, otherwise step 125 is executed;

step 125, the main control chip judges whether the self-increment mode of the address register needs to be reconfigured according to the current length, if so, the step 117 is returned, otherwise, the step 119 is returned;

step 126, the main control chip judges whether the received firmware upgrading command is the last block, if so, step 127 is executed; otherwise, returning to step 114;

127, setting the length of the firmware upgrading data as the current length by the main control chip;

and step 128, the main control chip executes the operation of reading the state of the nonvolatile memory of the target chip.

Step 128 is similar to step 112 and will not be described herein again;

step 129, the main control chip judges the state of the nonvolatile memory returned by the target chip, when the state of the nonvolatile memory is a preparation state, step 130 is executed, and when the state of the nonvolatile memory is a non-preparation state, step 128 is returned;

step 130, the main control chip organizes a write address register command, sets the data port to be in an output mode, and sends the write address register command to the target chip through the data port;

step 130 is similar to step 111 and will not be described herein.

Step 131, the main control chip sets the data port to an input mode, and determines whether to receive a confirmation response sent by the target chip, if yes, step 132 is executed, otherwise, error processing is performed;

step 132, the main control chip sets the data port to be in an output mode, and sends the initial address of the nonvolatile memory to the target chip through the data port;

step 133, the main control chip selects a self-increment mode according to the current length, and takes the selected self-increment mode as the current self-increment mode;

step 134, the main control chip executes the operation of configuring the address register, and configures the address register into the current self-increment mode;

step 134 is similar to step 118 and will not be described herein;

step 135, the main control chip organizes the read-write register command, sets the data port as an output mode, and sends the read-write register command to the target chip through the data port;

step 136, the main control chip sets the data port to an input mode, and determines whether to receive a confirmation response sent by the target chip, if yes, step 137 is executed, otherwise, error processing is performed;

step 137, the main control chip receives the data returned by the target chip; and storing the data in a cache region;

step 138, the main control chip updates the cyclic redundancy check code according to the data in the cache region;

step 139, the main control chip updates the current length and judges whether the current length is equal to 0, if yes, step 141 is executed, otherwise step 140 is executed;

step 140, the main control chip determines whether the self-increment mode of the address register needs to be reconfigured, if yes, the step 133 is returned, otherwise, the step 135 is returned;

and step 141, the main control chip judges whether the cyclic redundancy code is matched with the cyclic redundancy check code, if so, the firmware is successfully upgraded, and otherwise, error processing is performed.

Specifically, step 110 includes:

step 201, resetting a target chip by a main control chip;

specifically, the main control chip sets a data port as an output mode, and continuously sends a high level of a preset period on the data port;

the preset period in this embodiment is 50 periods, and may also be any period greater than 48 periods;

step 202, the main control chip controls the target chip to be electrified;

step 202 specifically includes:

202-1, the main control chip organizes a write control register command, sets a data port to be in an output mode, and sends the write control register command to a target chip through the data port;

in this embodiment, the command for organizing the write control register by the main control chip specifically includes: the main control chip sequentially splices the control register type 0, the current operation type, namely the write operation 0, and the address 01 of the control register, obtains the parity bit 1 according to the splicing result, and sequentially splices the start bit 1, the control register type 0, the current operation type, namely the write operation 0, the address 01 of the control register, the parity bit 1, the stop bit 0, and the supplement bit 1 to obtain a write control register command 10001101.

Step 202-2, the main control chip sets the data port as an input mode, judges whether a confirmation response sent by the target chip is received, if so, executes step 202-3, otherwise, throws out an exception;

specifically, when the confirmation response received by the main control chip is 001, the operation is successful, and when the confirmation response received by the main control chip is 100, the operation is failed;

step 202-3, the main control chip sets the data port to be in an output mode and sends the preset value to the target chip through the data port;

specifically, the data sent by the main control chip to the target chip is: 0x50000F00

Preferably, step 202-1 is preceded by: the main control chip sets an initial value of the number of times of sending the command of writing the control register;

correspondingly, in step 202-2, when the master control chip does not receive the acknowledgement response returned by the target chip, the method further includes: the main control chip updates the frequency of sending the write control register command, judges whether the frequency of sending the write control register command is greater than the preset frequency, if so, throws an exception, otherwise, returns to the step 202;

step 203, the main control chip judges whether the target chip is successfully electrified, if so, step 204 is executed, and step 203 is continuously executed;

specifically, step 203 includes:

203-1, the main control chip organizes a read control register command and sends the read control register command to a target chip through a data port;

in this embodiment, the command for organizing the read control register by the main control chip specifically includes: the main control chip sequentially splices the control register type 1, the current operation type, namely, the read operation 1, and the address 11 of the control register, obtains the parity bit 0 according to the splicing result, and sequentially splices the start bit 1, the control register type 1, the current operation type, namely, the read operation 1, the address 01 of the control register, the parity bit 1, the stop bit 0, and the supplement bit 1 to obtain a read control register command 10001101.

Step 203-2, the main control chip sets the data port as an input mode, judges whether a confirmation response sent by the target chip is received, if so, executes step 203-3, otherwise, throws out an exception;

203-3, the main control chip receives a read control register response sent by the target chip, judges whether the power-on is successful according to the read control register response, if so, executes the step 204, otherwise, returns to the step 203-1;

in this embodiment, the data received by the main control chip is: 0XF0000F 00; and acquiring the 29 th bit and the 31 th bit of the received data, judging that the power-on is successful by the main control chip when the two bits of data are both 1, and otherwise, judging that the power-on is failed.

Step 204, the main control chip executes the operation of reading the state of the nonvolatile memory of the target chip;

step 205, the main control chip judges the state of the nonvolatile memory returned by the target chip, if the state is a preparation state, step 206 is executed, and if the state is a non-preparation state, step 204 is returned;

step 206, the main control chip executes the operation of erasing the nonvolatile memory of the target chip; finishing initialization;

specifically, step 206 specifically includes:

step 206-1, the main control chip organizes the write address register command, sets the data port as an output mode, and sends the write address register command to the target chip through the data port;

step 206-2, the main control chip sets the data port as an input mode, judges whether to receive a confirmation response sent by the target chip, if so, executes step 206-3, otherwise, throws out an exception;

step 206-3, the main control chip sets the data port to be in an output mode and sends the initial address of the nonvolatile memory to the target chip through the data port;

step 206-4, the main control chip organizes the write-read-write register command, sets the data port as an output mode, and sends the write-read-write register command to the target chip through the data port;

step 206-5, the main control chip sets the data port as an input mode, judges whether to receive a confirmation response sent by the target chip, if so, executes step 206-6, otherwise, throws out an exception;

and step 206-6, the main control chip sets the data port to be in an output mode and sends the preset value to the target chip through the data port.

Example 3

The present embodiment provides a device for reading and writing a target chip, which includes a write data module 1 and a read data module 2, see fig. 6.

Wherein the write data module 1 comprises:

a first organizing command submodule 11 for organizing the write address register command;

a first sending submodule 12, configured to send a write address register command organized by the first organization command submodule 11 to a target chip;

the first judging submodule 13 is configured to judge whether a confirmation response sent by the target chip is received after the first sending submodule 12 sends the address register writing command to the target chip;

a first ending submodule 14, configured to end when the first determining submodule 13 determines that the acknowledgement response sent by the target chip is not received;

the first sending submodule 12 is further configured to send the write address to the target chip when the first judging submodule 13 judges that the acknowledgement response sent by the target chip is received;

the second organization command submodule 15 is used for organizing the write-read-write register command after the first sending submodule 12 sends the write address to the target chip;

the first sending submodule 12 is further configured to send the read-write register command organized by the second organization command submodule 15 to the target chip;

the second judging submodule 16 is configured to judge whether a confirmation response sent by the target chip is received after the first sending submodule 12 sends the read-write register command to the target chip;

the first sending submodule 12 is further configured to send the data to be written to the target chip when the second determining submodule 16 determines that the acknowledgement response sent by the target chip is received;

the first termination submodule 14 is further configured to terminate when the second determination submodule 16 determines that the acknowledgement response sent by the target chip is not received;

it should be noted that the write data module 1 further includes:

and the second receiving submodule is used for receiving a write data command sent by the upper computer and acquiring target data and a write address from the write data command or acquiring the target data and a preset write address from the write data command.

Optionally, the write data module 1 further includes:

the first setting submodule is used for setting a self-increment mode with a preset length as a current self-increment mode;

the first configuration address register submodule is used for executing configuration address register operation on a target chip and configuring the address register into a current self-increment mode set by the first setting submodule;

and the second organization command submodule 15 is used for organizing the write-read-write register command after the first sending submodule 12 sends the write address to the target chip and the first configuration address register submodule executes the configuration address register operation.

Further, the write data module 1 further includes:

the second setting submodule is used for taking the target data length as an initial value of the current length;

the first updating submodule is used for updating the current length after the first sending submodule 12 sends the data to be written to the target chip;

a fifth judgment submodule, configured to judge whether the current length updated by the first updating submodule is a preset value;

the first obtaining submodule is used for sequentially obtaining data with preset length from the target data as data to be written when the fifth judging submodule judges that the current length of the updated first updating submodule is not the preset value;

the first ending submodule is further used for ending when the fifth judging submodule judges that the updated current length is the preset value.

Alternatively, the write data module 1 further includes: the third setting submodule is used for taking the target data length as an initial value of the current length;

the first selection submodule is used for selecting a self-increasing mode according to the current length set by the third setting submodule and taking the selected self-increasing mode as the current self-increasing mode;

the first configuration address register submodule is used for executing configuration address register operation on a target chip and configuring an address register into a current self-increment mode;

the first sending submodule 12 is specifically configured to, when the second judging submodule 16 judges that the acknowledgement response sent by the target chip is received, sequentially obtain, from the target data, data with a length matched with the current auto-increment mode as data to be written; sending data to be written to a target chip; the second obtaining submodule is also used for obtaining data to be written and sending the data to be written to the target chip;

the second updating submodule is used for updating the current length after the first sending submodule 12 sends the data to be written to the target chip;

a sixth judgment submodule, configured to judge whether the current length updated by the second updating submodule is a preset value;

the second obtaining submodule is used for obtaining data with the length matched with the current self-increment mode as data to be written when the sixth judging submodule judges that the current length updated by the second updating submodule is not the preset value;

the first ending sub-module 14 is further configured to end when the sixth determining sub-module determines that the updated current length is the preset value.

Furthermore, when the sixth judgment submodule judges that the current length updated by the second updating submodule is not the preset value, the sixth judgment submodule is further used for judging whether the address register needs to be reconfigured according to the current length;

the first configuration address register submodule is also used for reconfiguring the address register according to the current length and configuring the address register into a current self-increment mode when the sixth judgment submodule judges that the address register needs to be reconfigured;

the second obtaining submodule is specifically used for obtaining data with the length matched with the current self-increment mode from the target data as to-be-written data when the sixth judging submodule judges that the address register does not need to be reconfigured; and the sixth judging submodule is also used for acquiring data with the length matched with the current self-increment mode reconfigured by the first configuration address register submodule from the target data as the data to be written when the sixth judging submodule judges that the address register needs to be reconfigured.

In more detail, the first configuration address register submodule specifically includes:

a first organization command unit for organizing the write configuration register commands;

the first sending unit is used for sending the write configuration register command organized by the first organization command unit to a target chip;

the first judging unit is used for judging whether the confirmation response sent by the target chip is received or not;

the first sending unit 12 is further configured to send the configuration information of the address register to the target chip when the first determining unit determines that the acknowledgement response sent by the target chip is received; the configuration information of the address register is used for configuring the address register to be in a current self-increment mode;

the first end sub-module 14 is further configured to end after the first sending unit does not receive the acknowledgement response sent by the target chip.

Preferably, the write data module 1 further includes:

the third receiving submodule is used for receiving a selection command sent by the upper computer; the host computer is also used for receiving a command for establishing a safety channel sent by the host computer;

the second selection submodule is specifically used for acquiring and storing the target chip identifier from the selection command when the third receiving submodule receives the selection command;

the first sending submodule 12 is further configured to return a successful selection response to the upper computer after the second selecting submodule acquires and stores the target chip identifier;

and the safe channel establishing submodule is used for establishing a safe channel with the target chip corresponding to the target chip identification stored by the second selection submodule when the third receiving submodule receives the safe channel establishing command.

In more detail, the write data module 1 further includes: a first port conversion submodule;

a first port conversion submodule, configured to set the data port to an output mode after the first organization command submodule 11 organizes the write address register command; the first sending submodule 12 is further configured to set the data port to an input mode after sending the write address register command to the target chip; the first judging submodule 13 is further configured to set the data port to the output mode after judging that the acknowledgement response sent by the target chip is received; and is further configured to set the data port to an input mode after the first sending submodule 12 sends a write-read-write register command to the target chip, and is further configured to set the data port to an output mode after the second judging submodule 16 judges that a received acknowledgement response sent by the target chip is received.

Preferably, the write data module further comprises:

the first nonvolatile memory state obtaining submodule is used for executing the operation of obtaining the nonvolatile memory state of the target chip; the tenth judging submodule is also used for acquiring the nonvolatile memory state of the target chip when judging that the nonvolatile memory state is the non-preparation state;

a tenth judging submodule, configured to judge a state of the nonvolatile memory returned by the target chip;

the first organizing command submodule 11 is specifically configured to organize the write address register command when the tenth determining submodule determines that the nonvolatile memory state is the ready state.

In more detail, the first sub-module for obtaining the status of the nonvolatile memory specifically includes:

a third organization command unit for organizing the write address register command; the tenth judging submodule is used for organizing a write address register command when judging that the state of the nonvolatile memory is a non-preparation state;

the third sending unit is used for sending the write address register command organized by the third organizing command unit to the target chip;

the third judging unit is used for judging whether a confirmation response sent by the target chip is received or not after the third sending unit sends the address register writing command;

the third sending unit is also used for sending the address of the nonvolatile memory control register to the target chip when the third judging unit judges that the acknowledgement response sent by the target chip is received;

the fourth organization command unit is used for organizing the read-write register command;

the third sending unit is also used for sending the read-write register command organized by the fourth organization command unit to the target chip;

the fourth judging unit is used for judging whether a confirmation response sent by the target chip is received or not after the third sending unit sends the read-write register command;

the first receiving unit is used for receiving the state of the nonvolatile memory returned by the target chip after the fourth judging unit judges that the confirmation response sent by the target chip is received;

the first termination submodule 14 is further configured to terminate after the fourth determination unit determines that the acknowledgement response sent by the target chip is not received;

preferably, the write data module further includes a first reset submodule for resetting the target chip;

the first reset submodule is specifically used for setting the data port to be in an output mode and continuously sending a preset level of a preset period on the data port;

preferably, the write data module further includes a second upper electronic module, configured to control the target chip to be powered on;

the second upper electronic module includes:

the eighth organization command unit is used for organizing the write control register command;

the seventh sending unit is used for sending the write control register command organized by the eighth organization command unit to the target chip;

the eighth judging unit is used for judging whether a confirmation response returned by the target chip is received or not after the seventh sending unit sends the command of writing the control register;

a seventh sending unit, configured to send the preset value to the target chip after the eighth determining unit determines that the acknowledgement response is received;

the second ending submodule 24 is further configured to end after the eighth judging unit judges that the acknowledgement response is not received.

The second upper electronic module further includes: the second data port conversion unit is used for setting the data port to be in an input mode after the seventh sending unit sends the write control register command; and is further configured to set the data port to the output mode after the eighth judging unit judges that the confirmation response is received.

The read data module 2 in the read/write device includes:

a third organization command submodule 21 for organizing the write address register command;

the second sending submodule 22 is configured to send the write address register command organized by the third organizing submodule 22 to the target chip;

the third judging submodule 23 is configured to judge whether a confirmation response sent by the target chip is received when the second sending submodule 22 sends the address register writing command to the target chip;

the second ending submodule 24 is configured to end when the third judging submodule 23 judges that the acknowledgement response sent by the target chip is not received;

the second sending submodule 22 is further configured to send a read address to the target chip after the third determining submodule 23 determines that the acknowledgement response sent by the target chip is received;

a fourth organization command submodule 25, configured to organize a read/write register command after the second sending submodule 22 sends the read address to the target chip;

the second sending submodule 22 is further configured to send the read-write register command organized by the fourth organization command submodule 25 to the target chip;

a fourth determining submodule 26, configured to determine whether a confirmation response sent by the target chip is received after the second sending submodule 22 sends a read/write register command to the target chip;

the first receiving submodule 27 is further configured to receive data returned by the target chip when the fourth judging submodule 26 judges that the acknowledgement response sent by the target chip is received;

the second ending submodule 24 is further configured to end when the fourth judging submodule 26 judges that the acknowledgement response sent by the target chip is not received.

Preferably, the data reading module 2 further includes:

the fourth setting submodule is used for setting the self-increment mode with the preset length as the current self-increment mode;

the second configuration address register submodule is used for executing the operation of configuring the address register on the target chip and setting the address register as the current self-increment mode set by the fourth setting submodule;

a fourth organization command submodule 25, configured to organize a read/write register command after the second sending submodule 22 sends the write address to the target chip and the second configuration address register submodule executes the configuration address register operation;

furthermore, the data reading module 2 further includes:

the fifth setting submodule is used for taking the preset reading length as the initial value of the current length;

a third updating submodule, configured to update the current length after the first receiving submodule 27 receives the data returned by the target chip;

the seventh judgment submodule is used for judging whether the current length updated by the third updating submodule is a preset value or not;

the fourth organization command submodule 25 is further configured to, when the seventh judgment submodule judges that the current length updated by the third updating submodule is not the preset value, organize the read-write register command;

the second ending sub-module 24 is further configured to end when the seventh determining sub-module determines that the current length updated by the third updating sub-module is the preset value.

Preferably, the data reading module 2 further includes:

a sixth setting submodule, configured to use a preset read length as an initial value of the current length;

the third selection submodule is used for selecting a self-increasing mode according to the current length set by the sixth setting module, and taking the selected self-increasing mode as the current self-increasing mode; the self-increment mode is selected according to the current length updated by the third updating submodule, and the selected self-increment mode is used as the current self-increment mode;

the second configuration address register submodule is used for executing the operation of configuring the address register on the target chip and configuring the address register into a current self-increment mode selected by the third selection submodule;

a third updating submodule, configured to update the current length according to the current self-increment mode when the first receiving submodule 27 receives a response returned by the target chip;

the eighth judgment submodule is used for judging whether the current length updated by the third updating submodule is a preset value or not;

the fourth organization command submodule 25 is further configured to, when the eighth judgment submodule judges that the current length updated by the third updating submodule is not the preset value, organize the read-write register command;

the second ending sub-module 24 is further configured to end when the eighth determining sub-module determines that the current length updated by the third updating sub-module is the preset value.

Furthermore, the data reading module 2 further includes:

the ninth judgment submodule is used for judging whether the address register needs to be reconfigured according to the current length when the eighth judgment submodule judges that the current length is not the preset value;

the second configuration address register submodule is also used for selecting a self-increasing mode according to the current length updated by the third updating submodule when the ninth judging submodule judges that the address register needs to be reconfigured, and taking the selected self-increasing mode as the current self-increasing mode;

the second termination submodule 24 is also arranged to terminate when the ninth decision submodule decides that the address register does not need to be reconfigured.

It should be noted that the second configuration address register submodule specifically includes:

a second organization command unit for organizing the write configuration register command;

the second sending unit is used for sending the write configuration register command organized by the second organization command unit to the target chip;

the second judgment unit is used for judging whether the confirmation response sent by the target chip is received or not;

the second sending unit is further used for sending the configuration information of the address register to the target chip when the second judging unit judges that the confirmation response sent by the target chip is received; the configuration information of the address register is used for configuring the address register to be in a current self-increment mode;

and the second ending submodule 24 is further configured to end when the second determining unit does not receive the acknowledgement response sent by the target chip.

Preferably, the data reading module 2 further includes: a second port conversion submodule;

a second port conversion submodule for setting the data port to an output mode after the third organization command submodule 21 organizes the write address register command; the second sending submodule 22 is further configured to set the data port to an input mode after sending the write address register command to the target chip; the third judging submodule 23 is further configured to set the data port to the output mode after the third judging submodule 23 judges that the acknowledgement response sent by the target chip is received; and is also used to set the data port to the input mode after the second sending submodule 22 sends the read/write register command to the target chip.

Preferably, the data reading module 2 further includes:

the second nonvolatile memory state obtaining submodule is used for executing the operation of obtaining the nonvolatile memory state of the target chip; an operation for acquiring the nonvolatile memory state of the target chip when the eleventh judgment sub-module judges that the nonvolatile memory state is the non-ready state;

the eleventh judging submodule is used for judging the state of the nonvolatile memory returned by the target chip;

the third organizing command submodule 21 is specifically configured to organize the write address register command when the eleventh judging submodule judges that the nonvolatile memory state is the ready state.

In more detail, the second sub-module for obtaining the status of the nonvolatile memory specifically includes:

a fifth organization command unit for organizing the write address register command; the eleventh judging submodule is used for organizing a write address register command when judging that the nonvolatile memory is in a non-preparation state;

a fourth sending unit, configured to send the write address register command organized by the fifth organization command unit to the target chip;

the fifth judging unit is used for judging whether a confirmation response sent by the target chip is received or not after the fourth sending submodule sends the address register writing command;

the fourth sending unit is further used for sending the address of the nonvolatile memory control register to the target chip when the fourth judging unit judges that the acknowledgement response sent by the target chip is received;

the sixth organization command unit is used for organizing the read-write register command;

the fourth sending unit is also used for sending the read-write register command organized by the sixth organization command unit to the target chip;

the sixth judging unit is used for judging whether a confirmation response sent by the target chip is received or not after the fourth sending unit sends the read-write register command;

the second receiving unit is used for receiving the state of the nonvolatile memory returned by the target chip after the sixth judging unit judges that the confirmation response sent by the target chip is received;

the second ending submodule 24 is further configured to end after the fourth judging unit judges that the acknowledgement response sent by the target chip is not received.

Preferably, the read data module 2 further includes a second reset submodule for resetting the target chip.

And the second reset submodule is specifically used for setting the data port to be in an output mode and continuously sending the preset level of the preset period on the data port.

The data reading module 2 also comprises a first upper electronic module which is used for controlling the target chip to be electrified;

the first upper electronic module includes:

a seventh organization command unit for organizing the write control register commands;

the sixth sending unit is used for sending the write control register command organized by the seventh organization command unit to the target chip;

the seventh judging unit is used for judging whether a confirmation response returned by the target chip is received or not after the sixth sending unit sends the write control register command;

a sixth sending unit, configured to send the preset value to the target chip after the seventh determining unit determines that the acknowledgement response is received;

a second ending sub-module 24, further configured to end when the seventh determining unit determines that no acknowledgement response is received;

the first upper electronic module further includes: the first data port conversion unit is used for setting the data port to be in an input mode after the sixth sending unit sends the write control register command; and is also used for setting the data port to the output mode after the seventh judging unit judges that the confirmation response is received.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method of reading from and writing to a target chip, comprising: a method for writing data to be written into a write address of a target chip by a main control chip and a method for reading data from a read address of the target chip by the main control chip;

step A1, the master control chip organizes a write address register command and sends the write address register command to a target chip;

step A3, the master control chip sends the write address to a target chip;

step A4, the master control chip organizes the write-read-write register command and sends the write-read-write register command to the target chip;

step A6, the main control chip sends the data to be written to a target chip;

step B1, the master control chip organizes the write address register command and sends the write address register command to the target chip;

step B3, the main control chip sends the read address to a target chip;

step B4, the master control chip organizes the read-write register command and sends the read-write register command to the target chip;

2. The method of claim 1, wherein step a4 is preceded by:

and 102, the main control chip executes the operation of configuring the address register to the target chip and configures the address register to be in the current self-increment mode.

3. The method of claim 2, wherein after said step 102, said step a4 is preceded by the steps of: the main control chip takes the length of the target data as an initial value of the current length, and sequentially obtains data with preset length from the target data as data to be written;

the step a6 further includes: the main control chip updates the current length, judges whether the current length is a preset value or not, and if yes, the writing operation is finished; otherwise, the data with preset length is obtained from the target data sequence and is used as the current data to be written.

4. The method of claim 1, wherein step a4 is preceded by:

the step a6 further includes: the main control chip updates the current length, judges whether the current length is a preset value or not, and if yes, the writing operation is finished; otherwise, the procedure returns to step 202.

5. The method of claim 4, wherein after the main control chip determines that the current length is not a preset value, the method further comprises: and the main control chip judges whether the address register needs to be reconfigured according to the current length, if so, the step 202 is returned, and if not, the step 203 is returned.

6. The method according to claim 2 or 4, wherein the main control chip performs an operation of configuring an address register on the target chip and configures the address register in the current self-increment mode, specifically comprising:

301, organizing a write configuration register command by the master control chip, and sending the write configuration register command to a target chip;

step 303, the main control chip sends the configuration information of the address register to a target chip; and the configuration information of the address register is used for configuring the address register to be in the current self-increment mode.

7. The method of claim 3 or 4, wherein the step A1 is preceded by the steps of: the method comprises the steps that a main control chip receives a data writing command sent by an upper computer, and target data and a writing address are obtained from the data writing command or the target data and a preset writing address are obtained from the data writing command.

8. The method of claim 1, wherein step a1 is preceded by:

step C1, the main control chip receives a selection command sent by the upper computer, acquires and stores a target chip identification from the selection command, and returns a successful selection response to the upper computer;

and step C2, the main control chip receives a command for establishing a secure channel sent by an upper computer, and establishes a secure channel with the target chip corresponding to the target chip identification.

9. The method of claim 1, wherein the method for the master control chip to write the data to be written to the write address of the target chip specifically comprises:

the step a1 is specifically that the main control chip organizes a write address register command, sets a data port as an output mode, and sends the write address register command to a target chip through the data port;

the step a2 specifically includes that the main control chip sets a data port as an input mode, and determines whether a confirmation response sent by a target chip is received, if yes, step A3 is executed, otherwise, the process is ended;

the step a3 is specifically that the main control chip sets a data port as an output mode, and sends an address of data to be written in a target chip to the target chip through the data port;

the step a4 is to organize a write/read register command by the main control chip and send the write/read register command to the target chip;

the step a5 is specifically that the master control chip sets a data port as an input mode, and determines whether a confirmation response sent by the target chip is received, if yes, step a6 is executed, otherwise, the process is ended;

specifically, in the step a6, the main control chip sets a data port as an output mode, and sends the data to be written to the target chip through the data port.

10. The method of claim 1, wherein step B4 is preceded by the further step of:

step 502, the main control chip executes the operation of configuring the address register to the target chip and configures the address register to be in the current self-increment mode.

11. The method of claim 10, wherein step B4 is preceded by the further step of: the main control chip takes a preset reading length as an initial value of the current length;

the step B6 further includes: the main control chip updates the current length according to the self-increasing mode of the preset length, judges whether the current length is the preset value or not, and if yes, the reading operation is finished; otherwise, return to step B4.

12. The method of claim 1, wherein step B4 is preceded by the further step of:

the step B6 further includes: the main control chip updates the current length according to the current self-increment mode, judges that the current length is a preset value, if yes, returns to the step 602; otherwise the read operation ends.

13. The method of claim 12, wherein after the main control chip determines that the current length is not a preset value, the method further comprises: and the main control chip judges whether the address registers need to be reconfigured according to the current length, if so, the step 602 is returned, otherwise, the step B4 is returned.

14. The method according to claim 10 or 12, wherein the main control chip performs an operation of configuring an address register on the target chip and configures the address register in the current self-increment mode, specifically comprising:

701, organizing a write configuration register command by the master control chip, and sending the write configuration register command to a target chip;

step 703, the main control chip sends the configuration information of the address register to the target chip; and the configuration information of the address register is used for configuring the address register to be in the current self-increment mode.

15. The method of claim 1, wherein the master chip performing a read operation on the target chip specifically comprises:

the step B1 specifically includes: the master control chip organizes a write address register command, sets a data port as an output mode, and sends the write address register command to a target chip through the data port;

the step B4 specifically includes: the master control chip organizes a read-write register command and sends the read-write register command to the target chip through the data port;

the step B5 specifically includes: the main control chip sets a data port as an input mode, judges whether a confirmation response sent by the target chip is received, if so, executes the step B6, otherwise, finishes;

16. The method of claim 1, wherein step a1 is preceded by: the main control chip executes the operation of acquiring the state of the nonvolatile memory of the target chip; and judging the state of the nonvolatile memory returned by the target chip, executing the step A1 when the state of the nonvolatile memory is in a ready state, and returning to continuously execute the operation of the main control chip for acquiring the state of the nonvolatile memory of the target chip when the state of the nonvolatile memory is in a non-ready state.

17. The method of claim 1, wherein step B1 is preceded by the further step of: the main control chip executes the operation of acquiring the state of the nonvolatile memory of the target chip; and judging the state of the nonvolatile memory returned by the target chip, executing the step B1 when the state of the nonvolatile memory is in a ready state, and returning to continuously execute the operation of acquiring the state of the nonvolatile memory of the target chip by the main control chip when the state of the nonvolatile memory is in a non-ready state.

18. The method according to claim 16 or 17, wherein the operation of the main control chip to acquire the nonvolatile memory state of the target chip specifically comprises:

step 402, the main control chip judges whether a confirmation response sent by the target chip is received, if so, step 403 is executed, otherwise, the process is ended;

step 403, the main control chip sends the address of the nonvolatile memory control register to a target chip;

step 404, the master control chip organizes a read-write register command and sends the read-write register command to the target chip;

and step 406, the main control chip receives the nonvolatile memory state returned by the target chip, and when the nonvolatile memory state is the ready state, step a1 is executed, otherwise, step 404 is executed after continuing to wait.

19. The method of claim 1, wherein the step a1 or B1 is preceded by: and the main control chip resets the target chip.

20. The method of claim 19, wherein the resetting the target chip by the master chip is specifically: the main control chip sets the data port as an output mode, and continuously sends preset levels of preset periods on the data port.

21. The method of claim 1, wherein prior to step a1 or prior to step B1, further comprising: the main control chip controls the target chip to be powered on;

d1, the main control chip organizes the command of the write control register and sends the command of the write control register to the target chip;

and D3, the main control chip sends the preset value to the target chip.

22. The method of claim 21, wherein said step D3 is further followed by:

23. An apparatus for reading from and writing to a target chip, comprising: a read data module and a write data module;

the write data module includes:

the first judgment submodule is used for judging whether a confirmation response sent by a target chip is received or not after the first sending submodule sends a write address register command to the target chip;

the first sending submodule is also used for sending a write address to the target chip when the first judging submodule judges that the confirmation response sent by the target chip is received;

the second organization command submodule is used for organizing a write-read-write register command after the first sending submodule sends the write address to the target chip;

the first sending submodule is also used for sending the read-write register command organized by the second organization command submodule to the target chip;

the second judgment submodule is used for judging whether a confirmation response sent by a target chip is received or not after the first sending submodule sends a read-write register command to the target chip;

the first sending submodule is further configured to send data to be written to a target chip when the second judging submodule judges that a confirmation response sent by the target chip is received;

the first termination submodule is further configured to terminate when the second determination submodule determines that the acknowledgement response sent by the target chip is not received;

the read data module comprises:

the second sending submodule is used for sending the write address register command organized by the third organization command submodule to a target chip;

the third judgment submodule is used for judging whether a confirmation response sent by the target chip is received or not when the second sending submodule sends a write address register command to the target chip;

the second sending submodule is further configured to send a read address to the target chip after the third judging submodule determines that the acknowledgement response sent by the target chip is received;

the fourth organization command submodule is used for organizing a read-write register command after the second sending submodule sends a read address to the target chip;

24. The apparatus of claim 23, wherein the write data module further comprises:

the first configuration address register submodule is used for executing configuration address register operation on a target chip and configuring an address register into a current self-increment mode set by the first setting submodule;

the second organization command submodule is used for organizing a write-read-write register command after the first sending submodule sends the write address to the target chip and the first configuration address register submodule executes a configuration address register operation.

25. The apparatus of claim 24, wherein the write data module further comprises:

the first updating submodule is used for updating the current length after the first sending submodule sends the data to be written to the target chip;

the first obtaining sub-module is used for sequentially obtaining data with preset length from the target data as data to be written when the fifth judging sub-module judges that the current length updated by the first updating sub-module is not a preset value;

the first ending sub-module is further configured to end when the fifth determining sub-module determines that the updated current length is a preset value.

26. The apparatus of claim 23, wherein the write data module further comprises: the third setting submodule is used for taking the target data length as an initial value of the current length;

the first sending submodule is specifically configured to, when the second judging submodule judges that the acknowledgement response sent by the target chip is received, sequentially obtain, from the target data, data with a length matched with the current self-increment mode as data to be written; sending the data to be written to a target chip; the second obtaining submodule is used for obtaining data to be written from the target chip;

the second updating submodule is used for updating the current length after the first sending submodule sends the data to be written to the target chip;

the second obtaining submodule is used for obtaining data with the length matched with the current self-increment mode as data to be written when the sixth judging submodule judges that the current length updated by the second updating submodule is not a preset value;

the first ending sub-module is further configured to end when the sixth determining sub-module determines that the updated current length is a preset value.

27. The apparatus of claim 26, wherein when the sixth determining sub-module determines that the current length updated by the second updating sub-module is not a preset value, the sixth determining sub-module is further configured to determine whether to reconfigure an address register according to the current length;

the first configuration address register submodule is further configured to reconfigure the address register according to the current length and configure the address register in the current self-increment mode when the sixth judgment submodule judges that the address register needs to be reconfigured;

the second obtaining submodule is specifically configured to obtain, as data to be written, data of a length matched with the current auto-increment mode from target data when the sixth judging submodule judges that the address register does not need to be reconfigured; and the sixth judging submodule is further configured to, when the address register needs to be reconfigured by the sixth judging submodule, acquire, from target data, data of a length matched with the current self-increment mode reconfigured by the first configuration address register submodule as data to be written.

28. The apparatus of claim 24 or 26, wherein the first configuration address register submodule specifically comprises:

the first sending unit is further configured to send the configuration information of the address register to a target chip when the first determining unit determines that the acknowledgement response sent by the target chip is received; the configuration information of the address register is used for configuring the address register to be in a current self-increment mode;

the first ending module is further configured to end when the first determining unit determines that the acknowledgement response sent by the target chip is not received.

29. The apparatus of claim 25 or 26, wherein the write data module further comprises:

and the second receiving submodule is used for receiving a write data command sent by an upper computer, and acquiring target data and a write address from the write data command or acquiring the target data and a preset write address from the write data command.

30. The apparatus of claim 23, wherein the write data module further comprises:

the second selection submodule is specifically used for acquiring and storing a target chip identifier from the selection command when the third receiving submodule receives the selection command;

the first sending submodule is also used for returning a successful selection response to the upper computer after the second selection submodule acquires and stores the target chip identifier;

and the safe channel establishing submodule is used for establishing a safe channel with the target chip corresponding to the target chip identification stored by the second selection submodule when the third receiving submodule receives a safe channel establishing command.

31. The apparatus of claim 23, wherein the write data module further comprises: a first port conversion submodule;

the first port conversion submodule is used for setting a data port as an output mode after the first organization command submodule organizes a write address register command; the first sending submodule is also used for setting a data port to be in an input mode after the first sending submodule sends a write address register command to a target chip; the first judgment submodule is also used for setting a data port to be in an output mode after judging that the confirmation response sent by the target chip is received; the second judging submodule is further configured to set the data port as an input mode after the first sending submodule sends a write-read-write register command to a target chip, and is further configured to set the data port as an output mode after the second judging submodule judges that a received acknowledgement response sent by the target chip is received.

32. The apparatus of claim 23, wherein the read data module further comprises:

and the fourth organization command submodule is used for organizing a read-write register command after the second sending submodule sends the write address to the target chip and the second configuration address register submodule executes a configuration address register operation.

33. The apparatus of claim 32, wherein the read data module further comprises:

the third updating submodule is used for updating the current length after the first receiving submodule receives the data returned by the target chip;

a seventh judging submodule, configured to judge whether the current length updated by the third updating submodule is a preset value;

the fourth organization command submodule is further configured to organize a read-write register command when the seventh judgment submodule judges that the current length updated by the third updating submodule is not a preset value;

the second ending submodule is further configured to end when the seventh judging submodule determines that the current length updated by the third updating submodule is a preset value.

34. The apparatus of claim 23, wherein the read data module further comprises:

the third selection submodule is used for selecting a self-increasing mode according to the current length set by the sixth setting submodule, and taking the selected self-increasing mode as the current self-increasing mode; the self-increment mode is selected according to the current length updated by the third updating submodule, and the selected self-increment mode is used as the current self-increment mode;

the second configuration address register submodule is used for executing the operation of configuring the address register on the target chip and configuring the address register into the current self-increment mode selected by the third selection submodule;

the third updating submodule is used for updating the current length according to the current self-increment mode when the first receiving submodule receives the response returned by the target chip;

the eighth judging submodule is used for judging whether the current length updated by the third updating submodule is a preset value or not;

the fourth organization command submodule is further configured to organize a read-write register command when the eighth judgment submodule judges that the current length updated by the third updating submodule is not a preset value;

the second ending submodule is further configured to end when the eighth determining submodule determines that the current length updated by the third updating submodule is a preset value.

35. The apparatus of claim 34, wherein the read data module further comprises:

a ninth judging submodule, configured to judge whether the address register needs to be reconfigured according to the current length when the eighth judging submodule judges that the current length is not the preset value;

the second configuration address register submodule is further configured to select a self-increment mode according to the current length updated by the third updating submodule when the ninth judging submodule judges that the address register needs to be reconfigured, and take the selected self-increment mode as the current self-increment mode;

the second ending submodule is further configured to end when the ninth determining submodule determines that the address register does not need to be reconfigured.

36. The apparatus of claim 32 or 34, wherein the second configuration address register submodule specifically comprises:

the second sending unit is used for sending the write configuration register command organized by the second organization command unit to a target chip;

the second judging unit is used for judging whether the confirmation response sent by the target chip is received or not;

the second sending unit is further configured to send the configuration information of the address register to the target chip when the second determining unit determines that the acknowledgement response sent by the target chip is received; the configuration information of the address register is used for configuring the address register to be in a current self-increment mode;

the second ending submodule is further configured to end when the second determining unit determines that the acknowledgement response sent by the target chip is not received.

37. The apparatus of claim 23, wherein the read data module further comprises: a second port conversion submodule;

the second port conversion submodule is used for setting a data port as an output mode after the third organization command submodule organizes a write address register command; the second sending submodule is also used for setting a data port to be in an input mode after the second sending submodule sends a write address register command to a target chip; the third judgment submodule is also used for setting the data port to be in an output mode after the third judgment submodule judges that the confirmation response sent by the target chip is received; and the second sending submodule is also used for setting the data port as an input mode after the second sending submodule sends a read-write register command to the target chip.

38. The apparatus of claim 23, wherein the write data module further comprises:

the first organizing command submodule is specifically configured to organize a write address register command when the tenth determining submodule determines that the nonvolatile memory is in the ready state.

39. The apparatus of claim 38, wherein the first obtain non-volatile memory status submodule specifically comprises:

a third organization command unit for organizing the write address register command; the tenth judging submodule is also used for organizing a write address register command when judging that the state of the nonvolatile memory is a non-preparation state;

a third sending unit, configured to send the write address register command organized by the third organizing command unit to the target chip;

the third judging unit is used for judging whether the confirmation response sent by the target chip is received or not after the third sending unit sends the command of writing the address register;

the third sending unit is further configured to send the address of the nonvolatile memory control register to the target chip when the third determining unit determines that the acknowledgement response sent by the target chip is received;

the third sending unit is further configured to send the read/write register command organized by the fourth organization command unit to the target chip;

the fourth judging unit is used for judging whether the confirmation response sent by the target chip is received or not after the third sending unit sends the read-write register command;

the first ending module is further configured to end after the fourth determining unit determines that the acknowledgement response sent by the target chip is not received.

40. The apparatus of claim 23, wherein the read data module further comprises:

an eleventh judging submodule, configured to judge a state of a nonvolatile memory returned by the target chip;

the third organizing command submodule is specifically configured to organize a write address register command when the eleventh judging submodule judges that the nonvolatile memory is in the ready state.

41. The apparatus of claim 40, wherein the second obtain non-volatile memory status submodule specifically comprises:

a fifth organization command unit for organizing the write address register command; the eleventh judging submodule is also used for organizing a write address register command when judging that the state of the nonvolatile memory is a non-preparation state;

a fifth judging unit, configured to judge whether a confirmation response sent by the target chip is received after the fourth sending unit sends the address register writing command;

the fourth sending unit is further configured to send the address of the nonvolatile memory control register to the target chip when the fourth determining unit determines that the acknowledgement response sent by the target chip is received;

the fourth sending unit is further configured to send the read/write register command organized by the sixth organization command unit to the target chip;

a sixth judging unit, configured to judge whether a confirmation response sent by the target chip is received after the fourth sending unit sends a read/write register command;

the second receiving unit is used for receiving the state of the nonvolatile memory returned by the target chip after the sixth judging unit judges that the acknowledgement response sent by the target chip is received;

the second ending submodule is further configured to end after the fourth determining unit determines that the acknowledgement response sent by the target chip is not received.

42. The apparatus of claim 23, wherein the write data module further comprises a first reset submodule to reset a target chip;

the data reading module further comprises a second reset submodule for resetting the target chip.

43. The apparatus according to claim 42, wherein the first reset submodule, in particular for setting the data port to the output mode, continuously transmits a preset level for a preset period on the data port;

the second reset submodule is specifically configured to set the data port to an output mode, and continuously send a preset level of a preset period on the data port.

44. The apparatus of claim 23,

the data reading module also comprises a first upper electronic module which is used for controlling the target chip to be electrified;

the first upper electronic module includes:

a sixth sending unit, configured to send the write control register command organized by the seventh organization command unit to a target chip;

a seventh judging unit, configured to judge whether a confirmation response returned by the target chip is received after the sixth sending unit sends the write control register command;

the sixth sending unit is configured to send the preset value to the target chip after the seventh determining unit determines that the acknowledgement response is received;

the second ending submodule is further configured to end when the seventh judging unit judges that no acknowledgement response is received;

the write-in data module also comprises a second upper electronic module which is used for controlling the target chip to be electrified;

the second upper electronic module includes:

a seventh sending unit, configured to send the write control register command organized by the eighth organization command unit to a target chip;

an eighth judging unit, configured to judge whether a confirmation response returned by the target chip is received after the seventh sending unit sends the write control register command;

the seventh sending unit is configured to send the preset value to the target chip after the eighth determining unit determines that the acknowledgement response is received;

the first ending sub-module is further configured to end after the eighth determining unit determines that no acknowledgement response is received.

45. The apparatus of claim 44, wherein the first upper electronic module further comprises: the first data port conversion unit is used for setting the data port to be in an input mode after the sixth sending unit sends a write control register command; the seventh judging unit is further configured to set the data port to the output mode after determining that the confirmation response is received;

the second upper electronic module further comprises: a second data port conversion unit, configured to set the data port to an input mode after the seventh sending unit sends the write control register command; and the eighth judging unit is further configured to set the data port to the output mode after determining that the confirmation response is received.