CN108036861A - A kind of single-photon detector of shared digital quantizer - Google Patents
A kind of single-photon detector of shared digital quantizer Download PDFInfo
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- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
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Abstract
The present invention relates to a kind of single-photon detector of shared digital quantizer, including N group single-photon detectings slowdown monitoring circuit, N number of digital quantizer and main control processor, main control processor is connected with N group single-photon detecting slowdown monitoring circuits, each group of single-photon detecting slowdown monitoring circuit is connected with a digital quantizer, and each group of single-photon detecting slowdown monitoring circuit includes multiple single photon detection units, a digital quantizer is connected with multiple single photon detection units；Each group of single-photon detecting slowdown monitoring circuit, the enabled control signal exported according to main control processor gate a single photon detection unit corresponding with enabled control signal, detect photon and pulse signal is produced when receiving photon to digital quantizer；Digital quantizer, the time interval of photon transmission is calculated according to pulse signal；Main control processor determines the distance between object and detector using time interval, completes detection.This detector shares the strategy of digital quantizer using row, improves the light receiving efficiency and integrated level of chip.
Description
Technical field
The present invention relates to photon detection field, more specifically to a kind of single photon detection of shared digital quantizer
Device.
Background technology
In recent years, unmanned technology becomes the hot spot of research, and the barrier on road is dynamically identified by various kinds of sensors
Hinder thing, such as automobile, bicycle and pedestrian etc..It is small by illumination effect since laser radar detection precision is high, it can directly acquire
Obstacle position information, therefore laser radar promises to be one of important sensing system of pilotless automobile.Text at present
Offer report if the laser radar that the manufacturers such as Google, Audi and most of research institution use is typically from SILK,
This several company of Velodyne, UTM.The maximum range of these laser radars is in the scope of 30m-174m, and minimum precision is in 1cm-
The scope of 10cm, scope of the frame per second in 10fps-20fps.Sensor pixel is 16 × 1,32 × 1,64 × 1 etc..
At present, TOF (flight time) laser ranging may be generally divided into two major classes, and one kind is phase type, and another kind is
Pulsed.The advantages of Laser Range Finding Based on Phase is exactly high certainty of measurement, and shortcoming is exactly that measurement distance is restricted.And Geiger mode angular position digitizer
TOF sensor belongs to pulsed, and this is a kind of, its advantage be realize it is simple in structure, can be to remote, low backward energy target is real
Now at a high speed, low-power consumption, high-precision range information obtains, so showing extraordinary prospect in Unmanned Systems.
The TOF sensor of Geiger mode angular position digitizer is to utilize single-photon avalanche diode (SPAD) detection being operated under Geiger mode angular position digitizer
The sensitiveness of photon, passage time digital quantizer (TDC) are recorded the photon that laser radar is launched and are received with sensor
Time interval between photon, is judged between target and sensor using time-correlated single photon counting t (TCSPC)
Distance, and build depth image.
For the design of SPAD pixels, there are two designs to consider that first is quenching circuit, and second is the elimination of afterpulse
Circuit.
Common quenching circuit has three kinds, and gate pulse is quenched, and passive type is quenched and active is quenched.Electricity is quenched in gate pulse
Road requires gate pulse signals and incident photon fully synchronized, otherwise can reduce counting rate.Passive type quenching circuit usually requires
The very big resistance of series connection, which could be realized, to be quenched, generally hundreds of nanosecond, and easily produce afterpulse.It is active that utilization is quenched
The advantage of feedback, by the snowslide pulse feedback that single photon signal produces to the driving voltage of SPAD, makes the biased electrical of SPAD
Pressure is dropped to below avalanche threshold voltage rapidly, to ensure that snowslide is thoroughly quickly quenched, and can prevent from being touched again during fast quick-recovery
Hair, and reduce the electricity that each snowslide produces, the number of afterpulse is reduced to a certain extent.Its biggest advantage is just
It is fast to be in response to speed, afterpulse number is few, and counting rate is high, is often used in the case where continuous signal detects.
In avalanche process, the carrier captured by interface impurity is released after snowslide by the delay in a moment
Come, snowslide can be triggered again under strong electric field, produce the afterpulse unrelated with a preceding photoproduction pulse.Moreover, each SPAD
Be required for a TDC cooperating, area occupied is very big, is unfavorable for the integrated of process chip.
The content of the invention
The technical problem to be solved in the present invention is, for the drawbacks described above of the prior art, there is provided the shared numeral of one kind turns
The single-photon detector of parallel operation.
The technical solution adopted by the present invention to solve the technical problems is：Construct a kind of single photon of shared digital quantizer
Detector, including N group single-photon detectings slowdown monitoring circuit, N number of digital quantizer and main control processor, the main control processor with it is described
N group single-photon detectings slowdown monitoring circuit connects, and each group of single-photon detecting slowdown monitoring circuit is connected with a digital quantizer, and each group of single photon
Detection circuit includes multiple single photon detection units, and a digital quantizer connects with multiple single photon detection units
Connect；N is the positive integer more than 1；
The main control processor is used to export enabled control signal；
Single-photon detecting slowdown monitoring circuit described in each group, gates one according to the enabled control signal and believes with the enabled control
Number corresponding single photon detection unit, for detecting photon and pulse signal being produced when receiving photon to the numeral conversion
Device；
The digital quantizer, the time interval of photon transmission is calculated according to the pulse signal, and is sent to described
Main control processor；
The main control processor determines the distance between object and detector using the time interval, completes detection.
Preferably, each described single photon detection unit includes a single-photon avalanche diode, quenching circuit and guarantor
Hold circuit；
The cathode of the single-photon avalanche diode meets positive high voltage power supply, the anode of the single-photon avalanche diode and institute
The test side connection of quenching circuit is stated, the output terminal of the quenching circuit is connected with the input terminal of the holding circuit, the guarantor
The output terminal for holding circuit is connected with the digital quantizer, the reset terminal of the feedback end of the holding circuit and the quenching circuit
Connection, the quenching circuit and the holding circuit are also connected with the main control processor respectively；
The enabled control signal of main control processor output is to the quenching circuit and holding circuit, so that the single photon
Avalanche diode is in acquisition mode, and in the single-photon avalanche diode snowslide, quickly will by the quenching circuit
Avalanche quenching, and control the single-photon avalanche diode to return to acquisition mode by the holding circuit, while also pass through institute
State holding circuit and send pulse signal to the digital quantizer.
Preferably, the quenching circuit includes the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, first and door, second
With door and the first phase inverter, wherein,
The grid of first NMOS tube is connected with described first with the output terminal of door, and the source electrode of first NMOS tube connects
Ground, the drain electrode of first NMOS tube are connected with the anode of the single-photon avalanche diode；Described first is defeated with the first of door
Enter end to be connected with the feedback end of the holding circuit by the reset terminal, described first inputs the enabled control of termination with the second of door
Signal processed；
The grid of second NMOS tube and drain electrode short circuit, the drain electrode of second NMOS tube also with the single-photon avalanche
The anode connection of diode, the source electrode of second NMOS tube are connected with the drain electrode of the 3rd NMOS tube, the 3rd NMOS
The source electrode ground connection of pipe, the grid of the 3rd NMOS tube is connected with described second with the output terminal of door, described second and door the
Two input terminals are connected with the output terminal of first phase inverter, and described second connects enabled control signal with the first input end of door,
The input terminal of first phase inverter is connected with the anode of the single-photon avalanche diode；
First NMOS tube drain electrode also respectively with second NMOS tube drain electrode and first phase inverter it is defeated
Enter end connection, and the drain electrode and the drain electrode of second NMOS tube and the input of first phase inverter of first NMOS tube
The node of end connection is the test side of the quenching circuit.
Preferably, first phase inverter includes the first PMOS tube and the 4th NMOS tube, wherein,
The grid of first PMOS tube is connected with the grid of the 4th NMOS tube, and the grid of first PMOS tube
It is connected with anode of the connecting node of the grid of the 4th NMOS tube also with the single-photon avalanche diode, described first
The drain electrode of PMOS tube connects high level, and the source electrode of first PMOS tube is connected with the drain electrode of the 4th NMOS tube, and described first
The source electrode of PMOS tube is also connected with the connecting node of the drain electrode of the 4th NMOS tube with described second with the second input terminal of door,
The source electrode ground connection of 4th NMOS tube；
The source electrode of first PMOS tube and the connecting node of the drain electrode of the 4th NMOS tube are first phase inverter
Output terminal, the output terminal of the first anti-device and second with the connecting node of the second input terminal of door is the quenching circuit
Output terminal.
Preferably, the holding circuit includes the second phase inverter, the 3rd and door, the 4th and door, resistance and capacitance, its
In,
The input terminal of second phase inverter is connected with the output terminal of the quenching circuit, the output of second phase inverter
End be connected respectively with the described 3rd with the first input end of door and the 4th with the second input terminal of door, second phase inverter it is defeated
Outlet also passes sequentially through the resistance and capacity earth；Described 3rd inputs the enabled control signal of termination with the second of door, described
3rd is connected with the output terminal of door with the digital quantizer；Described 4th with the first input end of door be connected to the resistance with
Between capacitance, the described 4th is connected with the output terminal of door with the reset terminal of the quenching circuit；
The input terminal of first phase inverter is the input terminal of the holding circuit, and the described 4th and the output terminal of door are institute
State the feedback end of holding circuit, the described 3rd with output terminal that the output terminal of door is the holding circuit.
Preferably, second phase inverter includes the second PMOS tube and the 5th NMOS tube；
The grid of second PMOS tube is connected with the grid of the 5th NMOS tube, and the grid of second PMOS tube
It is connected with output terminal of the connecting node of the grid of the 5th NMOS tube also with the quenching circuit, the second PMOS tube leakage
Pole connects high level, and the drain electrode of second PMOS tube is connected with the described 4th with door, and the source electrode of second PMOS tube connects the 5th
The drain electrode of NMOS tube, the source electrode ground connection of the 5th NMOS tube, the source electrode of second PMOS tube and the 5th NMOS tube
The connecting node of drain electrode is the output terminal of second phase inverter.
Preferably, the described 4th includes the 3rd PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th NMOS tube, the with door
Seven NMOS tubes and the 8th NMOS tube；
The grid of 3rd PMOS tube and the output terminal of second phase inverter, the 3rd with the first input end of door and
The grid connection of 6th NMOS tube, the drain electrode of the 3rd PMOS tube and drain electrode and the 5th PMOS tube of the 4th PMOS tube
Drain electrode connect and be connected to the drain electrode of second PMOS tube, source electrode and the 4th PMOS tube of the 3rd PMOS tube
Source electrode connects and is connected to the drain electrode of the 6th NMOS tube；The drain electrode and the leakage of the 4th PMOS tube of 5th PMOS tube
Pole connects；
The grid of 4th PMOS tube is connected with the grid of the 7th NMOS tube, and the drain electrode of the 6th NMOS tube is also
Be connected with the grid of the 5th PMOS tube and the grid of the 8th NMOS tube, the grid of the 7th NMOS tube also with it is described
Connecting node connection between resistance and capacitance；The source electrode of 6th NMOS tube is connected with the drain electrode of the 7th NMOS tube, described
The source electrode ground connection of 7th NMOS tube；The source electrode of 5th PMOS tube is connected with the drain electrode of the 8th NMOS tube, and the described 8th
The source electrode ground connection of NMOS tube；The source electrode of 5th PMOS tube and the connecting node of the 8th NMOS tube are defeated with door for the described 4th
Outlet.
Preferably, single-photon detecting slowdown monitoring circuit described in each group further includes shared circuit, multiple single photon detection units
It is connected by the shared circuit with a digital quantizer；
The shared circuit includes first switch circuit, and the first switch circuit and a single photon detection unit connect
Connect；
The shared circuit further includes at least one second switch circuit, row latch, the first row latch, the 12nd
NMOS tube, row phase inverter, row pull-up resistor and the first row pull-up resistor, the first switch circuit include the 9th NMOS tube, the
Ten NMOS tubes and the 11st NMOS tube；
The grid of 9th NMOS tube respectively the grid with the tenth NMOS tube, the 11st NMOS tube grid and
The output terminal connection of the holding circuit of the single photon detection unit, the drain electrode of the 9th NMOS tube pass through the row pull-up electricity
Resistance is connected with high level, and the drain electrode of the 9th NMOS tube is also connected by the input terminal of the row phase inverter and the row latch
Connect, meanwhile, the drain electrode of the 9th NMOS tube is connected with least one second switch circuit, the source of the 9th NMOS tube
Pole is grounded, and the output terminal of the row latch is connected with the main control processor；
The drain electrode of tenth NMOS tube after the drain electrode short circuit of the 11st NMOS tube by the first row with being pulled up
Resistance connects high level, and the source electrode of the tenth NMOS tube after the source shorted of the 11st NMOS tube with being grounded；Described tenth
Source electrode of the source electrode of NMOS tube also with the 12nd NMOS tube is connected, and the grid of the 12nd NMOS tube is latched with the row
Device connects, and the drain electrode of the 12nd NMOS tube is connected with the input terminal of the row phase inverter；The leakage of 11st NMOS tube
First input end of the pole also with the first row latch is connected, the second input terminal of the first row latch also with the row
The input terminal connection of phase inverter, the output terminal of the first row latch are connected with the digital quantizer.
Preferably, each described second switch circuit is connected with a single photon detection unit,
Each described second switch circuit includes the 13rd NMOS tube, the 14th NMOS tube, the 15th NMOS tube, second
Row pull-up resistor and the second row latch；
The grid of 13rd NMOS tube grid with the 14th NMOS tube, the 15th NMOS tube respectively
The holding circuit of grid and the single photon detection unit output terminal connection, the drain electrode of the 13rd NMOS tube with it is described
After the drain electrode short circuit of 9th NMOS tube, be additionally coupled to the input terminal of the row phase inverter, the source electrode of the 13rd NMOS tube with
It is grounded after the source electrode of 14th NMOS tube, the source shorted of the 15th NMOS tube；
By on second row after the drain electrode of 14th NMOS tube and the drain electrode short circuit of the 15th NMOS tube
Pull-up resistor connects high level, the connecting node of drain electrode with the drain electrode of the 15th NMOS tube of the 14th NMOS tube also with institute
State the first input end connection of the second row latch, the second input terminal of the second row latch also with the row phase inverter
Input terminal connects, and the output terminal of the second row latch is connected with the digital quantizer.
Preferably, the shared circuit further includes the first delay circuit and the second delay circuit, first delay circuit
It is connected between the grid of the tenth NMOS tube and the grid of the 11st NMOS tube, second delay circuit is connected to
Between the grid of 14th NMOS tube and the grid of the 15th NMOS tube.
Implement the single-photon detector of the shared digital quantizer of the present invention, have the advantages that：The present invention uses
Active that snowslide is quenched, fast response time, afterpulse number is few, counting rate is high, and the strategy of digital quantizer is also shared using row,
The light receiving efficiency of chip can not only be lifted while the quantity of required digital quantizer can also be greatly reduced, numeral is reduced and turn
The area occupied of parallel operation, so as to reduce the area of whole chip, improves the integrated level of chip.
Brief description of the drawings
Below in conjunction with accompanying drawings and embodiments, the invention will be further described, in attached drawing：
Fig. 1 is a kind of structure diagram of the single-photon detector of shared digital quantizer of the present invention；
Fig. 2 is a kind of chip block diagram of one preferred embodiment of single-photon detector of shared digital quantizer of the present invention；
Fig. 3 is quenching circuit and the circuit diagram of holding circuit in one embodiment of the invention single photon detection unit；
Fig. 4 is the schematic circuit diagram of the shared circuit of the present invention；
Fig. 5 is the oscillogram of first two columns pixel in detector in one embodiment of the invention.
Embodiment
In order to which the technical features, objects and effects of the present invention are more clearly understood, now compare attached drawing and describe in detail
The embodiment of the present invention.
It is vehicle-mounted sharp that the single-photon detector of the shared digital quantizer of the embodiment of the present invention can be applied to pilotless automobile
Optical radar.
As shown in Figure 1, the single-photon detector of the shared digital quantizer of the embodiment of the present invention includes N group single photon detections
Circuit 30, N number of digital quantizer 20 and main control processor 10, main control processor 10 are connected with N group single-photon detectings slowdown monitoring circuit 30,
Each group of single-photon detecting slowdown monitoring circuit 30 is connected with a digital quantizer 20, and each group of single-photon detecting slowdown monitoring circuit 30 is including multiple
Single photon detection unit, a digital quantizer 20 are connected with multiple single photon detection units；N is the positive integer more than 1；Master control
Processor 10 is used to export enabled control signal；Each group of single-photon detecting slowdown monitoring circuit 30, one is gated according to enabled control signal
Single photon detection unit corresponding with enabled control signal, for detecting photon and producing pulse signal extremely when receiving photon
Digital quantizer 20；Digital quantizer 20, the time interval of photon transmission is calculated according to pulse signal, and is sent to master control
Manage device 10；Main control processor 10 determines the distance between object and detector using time interval, completes detection.
Specifically, as shown in Figure 1, in the single-photon detector of the shared digital quantizer of the present embodiment, each group of monochromatic light
Sub- detection circuit 30 include 1,2,3 ..., m single photon detection unit, each single photon detection unit with a numeral
Converter 20 (TDC) connects, i.e., in the present embodiment, m single photon detection unit in each group of single-photon detecting slowdown monitoring circuit 30 is total to
With a TDC.By the way that the light receiving efficiency of chip by multiple one TDC of single photon detection units shared, can be greatly enhanced, at the same time
The use quantity of TDC can be also reduced, the area occupied of TDC is reduced, further increases the integrated level of chip, also reduce chip
Material cost.
Main control processor 10, exports enabled control signal and gates any of each group of single-photon detecting slowdown monitoring circuit 30 single photon
Probe unit, so that the single photon detection unit gated is under acquisition mode, and then the single photon detection for passing through the gating
Unit is used to detect photon, and produces pulse signal to digital quantizer 20 when receiving photon.Meanwhile handled by master control
The control selections of device 10, the single photon detection unit being not gated on then are in off position, and the single-photon detecting to being gated
Unit is surveyed to have no effect.I.e. in each group of single-photon detecting slowdown monitoring circuit 30, when any single photon detection unit is strobed
When, other single photon detection units are controlled in off working state, influence what is be strobed to avoid other single photon detection units
The detection of single photon detection unit, improves the stability and reliability of detector.
Optionally, in the present embodiment, the enabled control signal that main control processor 10 exports is low and high level signal, wherein,
The high level signal exported is used to gate single photon detection unit, and low level signal is used to control single photon detection unit to be in
Off working state.
Further, the state for controlling monochromatic light sub-control unit whether to be in detection photon by enabling control signal,
Just gate when needing the single photon detection unit to be detected, not gated then when the detection of single photon detection unit is not required, can be with
Avoid single photon detection unit from being chronically at acquisition mode, reduce the power consumption of detector, ensure that the reliability of detector.
Further, the single-photon detector of the shared digital quantizer of the embodiment of the present invention, passes through main control processor 10
Control action, realize it is active be quenched, faster, afterpulse number is few for speed of detection, and counting rate is high, it is possible to achieve moment quenches
Go out, improve detection accuracy.
Optionally, the main control processor 10 of the present embodiment can use dsp processor or fpga chip, used
The type selecting of dsp processor or fpga chip can need to be determined according to product, and the embodiment of the present invention is not especially limited.
As shown in Fig. 2, the core of the single-photon detector for the shared digital quantizer of an application specific embodiment of the invention
The block diagram of piece.In this embodiment, the chip selected by detector is the pixel unit of 4*16, each pixel unit is equipped with one
A single photon detection unit, therefore, it is one group to take 4 single photon detection units, and each group is connected with a TDC, i.e. 4 monochromatic lights
Sub- probe unit shares a TDC, then a total of 16 groups of single-photon detecting slowdown monitoring circuits 30 and 16 TDC, each group of single-photon detecting
Slowdown monitoring circuit 30 is correspondingly arranged with a TDC.By the design method, compared to traditional design method：One single photon detection
Unit just needs a TDC, and the present embodiment can greatly reduce the quantity and area of TDC, be more conducive to the integrated level of chip,
But also the light receiving efficiency of chip can be effectively lifted, validation test is carried out with the embodiment shown in Fig. 2, by by every 4 lists
Photon detection unit shares a TDC for one group, the charging efficiency of the photosensitive part of chip from 2.84074% original lifting to
10.4706%.
Refering to Fig. 3, Fig. 3 is quenching circuit 301 and holding circuit 302 in one embodiment of the invention single photon detection unit
Circuit diagram.
As shown in figure 3, in the present embodiment, each single photon detection unit includes a single-photon avalanche diode
(SPAD), quenching circuit 301 and holding circuit 302, the cathode of single-photon avalanche diode connect positive high voltage power supply, single-photon avalanche
The anode of diode is connected with the test side (SPAD_ANODE) of quenching circuit 301, the output terminal (QUENCH_ of quenching circuit 301
OUT) it is connected with the input terminal (HOLD_OFF) of holding circuit 302, output terminal (SPAD_TRIGGER) and the number of holding circuit 302
Word converter 20 connects, the feedback end (HOLD_OFF_OUT) of holding circuit 302 and the reset terminal (SPAD_ of quenching circuit 301
RESET) connect, quenching circuit 301 and holding circuit 302 are also connected (i.e. as shown in Fig. 2, being quenched with main control processor 10 respectively
Circuit 301 and holding circuit 302 are connected by Enable Pin (SPAD_EN) with main control processor 10, to receive main control processor 10
The enabled control signal of output)
The enabled control signal of the output of main control processor 10 is to quenching circuit 301 and holding circuit 302, so that single-photon avalanche
Diode is in acquisition mode, and in single-photon avalanche diode snowslide, by quenching circuit 301 quickly by avalanche quenching,
And control single-photon avalanche diode to return to acquisition mode by holding circuit 302, while also by holding circuit 302 to numeral
Converter 20 sends pulse signal.It is to be appreciated that in SPAD snowslides, control action and output by holding circuit 302
One feedback signal resets SPAD and it is in again under detection state, so as to substantially reduce snow to SPAD_RESET
The time that electric current flows through SPAD is collapsed, reduces the power consumption of SPAD, extends the service life of SPAD.
In the present embodiment, quenching circuit 301 can include the first NMOS tube MN0, the second NMOS tube MN1, the 3rd NMOS tube
MN2, first with door, second with door and the first phase inverter, wherein, the grid of the first NMOS tube MN0 with first and door output
End connection, the source electrode ground connection of the first NMOS tube MN0, the drain electrode of the first NMOS tube MN0 and the anode of single-photon avalanche diode connect
Connect；First is connected with the first input end of door by reset terminal with the feedback end of holding circuit 302, and first inputs with the second of door
The enabled control signal of termination.
The grid of second NMOS tube MN1 and drain electrode short circuit, the drain electrode of the second NMOS tube MN1 is also and single-photon avalanche diode
Anode connection, the source electrode of the second NMOS tube MN1 is connected with the drain electrode of the 3rd NMOS tube MN2, and the source electrode of the 3rd NMOS tube MN2 connects
Ground, the grid of the 3rd NMOS tube MN2 are connected with second with the output terminal of door, second with the second input terminal and the first phase inverter of door
Output terminal connection, second connects enabled control signal with the first input end of door, and input terminal and the single photon of the first phase inverter are avenged
Collapse the anode connection of diode.
The drain electrode of first NMOS tube MN0 also connects with the drain electrode of the second NMOS tube MN1 and the input terminal of the first phase inverter respectively
Connect, and the node that the drain electrode of the first NMOS tube MN0 is connected with the drain electrode of the second NMOS tube MN1 and the input terminal of the first phase inverter
For the test side of quenching circuit 301.
As shown in figure 3, when the enabled control signal SPAD_EN that main control processor 10 exports is low level, due to first
With door and second with the effect of door, the voltage of A points and B points is all low level, at this time the first NMOS tube MN0 and the 3rd NMOS tube
MN2 is in off-state, its conducting resistance is very big, and the test side (SPAD_ANODE) of quenching circuit 301 is and SPAD
Anode connection, since the conducting resistance of the 3rd NMOS tube MN2 is very big, the voltage at SPAD_ANODE is higher,
Reversed bias voltage which results in SPAD is less than breakdown voltage, and SPAD can not be biased under Geiger mode angular position digitizer.At this time, SPAD_RESET
Signal can not also reset SPAD.I.e. when the enabled control signal received by the single photon detection unit is believed for low level
Number when, which does not work.
When the enabled control signal SPAD_EN that main control processor 10 exports is high level, the first NMOS tube MN0 conductings,
SPAD_ANODE is shorted to ground at this time, i.e. the anode voltage of SPAD is pulled low, and the reversed bias voltage of SPAD is more than breakdown voltage,
SPAD is biased under Geiger mode angular position digitizer, i.e. SPAD is in acquisition mode.When SPAD receives photon, snowslide occurs for SPAD moments,
Avalanche current flows through the anode of SPAD from the cathode of SPAD, and the anode voltage of SPAD is quickly pulled up, and passes through the first phase inverter
High level at SPAD anodes is changed into low level by effect, and is transmitted to holding circuit 302, passes through holding circuit 302
The high level of SPAD anodes is kept for a period of time, and receive holding circuit 302 makes SPAD reset and again by SPAD_RESET again
It is reverse-biased under Geiger mode angular position digitizer.I.e. when SPAD receives photon, and snowslide occurs, acted on by quenching circuit 301 and raised rapidly
The anode voltage of SPAD, quickly by avalanche quenching, at the same time, the anode tap electricity of SPAD is made by the effect of holding circuit 302
Pressure is kept for a period of time, efficiently avoid the snowslide again triggered under strong electric field, is reduced unrelated with a preceding photoproduction pulse
Afterpulse.The closed circuit formed at the same time by holding circuit 302 and quenching circuit 301, realizes feedback, so that SPAD is extensive rapidly
Multiple acquisition mode, and the pulse signal that SPAD is produced is exported to digital quantizer 20 by holding circuit 302.
As known from the above, when main control processor 10 need to gate any one single photon in each group of single-photon detecting slowdown monitoring circuit 30
During probe unit, main control processor 10 exports the enabled control signal of a high level to quenching circuit 301 and holding circuit
302, to gate the SPAD being correspondingly arranged with the quenching circuit 301 and holding circuit 302, photon detection is realized by the SPAD；
Meanwhile main control processor 10 exports (m-1) a low level enabled control signal to remaining (m-1) a single photon detection list
Member, control are somebody's turn to do (m-1) a single photon detection unit and are in off working state.
Optionally, in the present embodiment, the first phase inverter can include the first PMOS tube PM0 and the 4th NMOS tube MN3, its
In, the grid of the first PMOS tube PM0 is connected with the grid of the 4th NMOS tube MN3, and the grid and the 4th of the first PMOS tube PM0
The connecting node of the grid of NMOS tube MN3 is also connected with the anode of single-photon avalanche diode, and the drain electrode of the first PMOS tube PM0 connects
High level, the source electrode of the first PMOS tube PM0 are connected with the drain electrode of the 4th NMOS tube MN3, the source electrode and the 4th of the first PMOS tube PM0
The connecting node of the drain electrode of NMOS tube MN3 is also connected with second with the second input terminal of door, and the source electrode of the 4th NMOS tube MN3 connects
Ground.
The connecting node of the drain electrode of the source electrode and the 4th NMOS tube MN3 of first PMOS tube PM0 is the output of the first phase inverter
End, the output terminal of the first anti-device and the second output terminal with the connecting node of the second input terminal of door for quenching circuit 301
(QUENCH_OUT)。
Optionally, the holding circuit 302 of the present embodiment can be including the second phase inverter, the 3rd and door, the 4th and door, resistance
And capacitance, wherein, the input terminal of the second phase inverter is connected with the output terminal of quenching circuit 301, the output terminal of the second phase inverter
It is connected respectively with the 3rd with the first input end of door and the 4th with the second input terminal of door, the output terminal of the second phase inverter is also successively
Pass through resistance and capacity earth；3rd with the second of door the enabled control signal of input termination, the 3rd with the output terminal and numeral of door
Converter connects；4th and the first input end of door be connected between resistance and capacitance, the 4th with the output terminal of door and being quenched electricity
The reset terminal connection on road 301；The input terminal of first phase inverter is the input terminal of holding circuit 302, and the 4th is with the output terminal of door
The feedback end of holding circuit 302, the 3rd with output terminal (SPAD_TRIGGER) that the output terminal of door is holding circuit 302.
Optionally, in the present embodiment, the second phase inverter can include the second PMOS tube PM1 and the 5th NMOS tube MN4；Second
The grid of PMOS tube PM1 is connected with the grid of the 5th NMOS tube MN4, and the grid and the 5th NMOS tube MN4 of the second PMOS tube PM1
Output terminal of the connecting node also with quenching circuit 301 of grid be connected, the second PMOS tube PM1 drain electrodes connect high level, second
The drain electrode of PMOS tube PM1 is connected with the 4th with door, and the source electrode of the second PMOS tube PM1 connects the drain electrode of the 5th NMOS tube MN4, and the 5th
The source electrode ground connection of NMOS tube MN4, the connecting node of the drain electrode of the source electrode and the 5th NMOS tube MN4 of the second PMOS tube PM1 is second
The output terminal of phase inverter.
Optionally, in the present embodiment the 4th with door include the 3rd PMOS tube PM2, the 4th PMOS tube PM3, the 5th PMOS tube
PM5, the 6th NMOS tube MN5, the 7th NMOS tube MN6 and the 8th NMOS tube MN7；
The grid of 3rd PMOS tube PM2 and the output terminal of the second phase inverter, the 3rd with the first input end and the 6th of door
The grid connection of NMOS tube MN5, the drain electrode of the 3rd PMOS tube PM2 and drain electrode and the 5th PMOS tube PM4 of the 4th PMOS tube PM3
Drain electrode connect and be connected to the drain electrode of the second PMOS tube PM1, the source electrode of the 3rd PMOS tube PM2 and the source of the 4th PMOS tube PM3
Pole connects and is connected to the drain electrode of the 6th NMOS tube MN5.
The grid of 4th PMOS tube PM3 is connected with the grid of the 7th NMOS tube PM6, the drain electrode of the 6th NMOS tube MN5 also with
The connection of the grid of the grid of 5th PMOS tube PM4 and the 8th NMOS tube MN7, the grid of the 7th NMOS tube MN6 also with resistance and electricity
Connecting node connection between appearance；The source electrode of 6th NMOS tube MN5 is connected with the drain electrode of the 7th NMOS tube MN6, the 7th NMOS tube
The source electrode ground connection of MN6；The source electrode of 5th PMOS tube PM4 is connected with the drain electrode of the 8th NMOS tube MN7, the source of the 8th NMOS tube MN7
Pole is grounded；The drain electrode of 5th PMOS tube is connected with the drain electrode of the 4th PMOS tube；The source electrode and the 8th NMOS tube of 5th PMOS tube PM4
The connecting node of MN7 is the 4th and the output terminal of door.
As shown in figure 3, when SPAD receives photon, and snowslide occurs, the second phase inverter receives the output of the first phase inverter
Low level, and low level is changed into high level from the effect of the second phase inverter, and it is transmitted to the 3rd and door, the 4th and door and electricity
The delay circuit of R and capacitance C compositions is hindered, at this time by the 3rd and the effect of door, the output terminal (SPAD_ of holding circuit 302
TRIGGER) signal of output is the pulse signal that SPAD is produced, by resistance R and the time-lag action of capacitance C, so that
The high voltage of SPAD anode taps is kept for a period of time, then feeds back to SPAD_RESET with goalkeeper's high level signal through the 4th, so that
SPAD reset and it is again reverse-biased under Geiger mode angular position digitizer (i.e. acquisition mode).
It is to be appreciated that the retention time of holding circuit 302 can be by resistance R and capacitance C and holding circuit 302
The threshold voltage of NMOS tube determines, and the threshold voltage of NMOS tube is determined by manufacture craft, therefore, is protected using different NMOS tubes
The retention time difference of circuit 302 is held, the present invention is not especially limited.In addition, retention time and the product of capacitance R and capacitance C
Correlation, therefore, can adjust the value of resistance R and capacitance C as needed to obtain the different retention times.Change speech
It, after selected NMOS tube determines, can by adjusting the value of resistance R and capacitance C to control the holding of holding circuit 302 when
Between.It should be noted that in order to ensure the security of SPAD, the retention time of holding circuit 302 should not design long, tool
The body time need to determine that the present invention is not especially limited according to the characteristic of the design of circuit, the requirement of chip and SPAD.
Optionally, in the present embodiment, each group of single-photon detecting slowdown monitoring circuit 30 further includes shared circuit 303, multiple monochromatic lights
Sub- probe unit is connected by shared circuit 303 with a digital quantizer 20.
Shared circuit 303 includes first switch circuit, and first switch circuit is connected with a single photon detection unit；It is shared
It is anti-that circuit 303 further includes at least one second switch circuit, row latch, the first row latch, the 12nd NMOS tube MN12, row
Phase device, row pull-up electricity R0 resistances and the first row pull-up resistor R1, first switch circuit include the 9th NMOS tube MN9, the tenth NMOS tube
MN10 and the 11st NMOS tube MN11；
The grid of the grid of 9th NMOS tube the MN9 grid with the tenth NMOS tube MN10, the 11st NMOS tube MN11 respectively
And the output terminal connection of the holding circuit 302 of single photon detection unit, the drain electrode of the 9th NMOS tube MN9 pass through row pull-up resistor
R0 is connected with high level (VDD), and the drain electrode of the 9th NMOS tube MN9 is also connected by row phase inverter with the input terminal of row latch,
Meanwhile the 9th the drain electrode of NMOS tube MN9 be connected with least one second switch circuit, the source electrode ground connection of the 9th NMOS tube MN9, row
The output terminal of latch is connected with main control processor 10.
The drain electrode of tenth NMOS tube MN10 after the drain electrode short circuit of the 11st NMOS tube MN11 with passing through the first row pull-up resistor
R0 connects high level (VDD), and the source electrode of the tenth NMOS tube MN10 after the source shorted of the 11st NMOS tube MN11 with being grounded；Tenth
Source electrode of the source electrode of NMOS tube MN10 also with the 12nd NMOS tube MN12 is connected, and grid and the row of the 12nd NMOS tube MN12 latch
Device connects, and the drain electrode of the 12nd NMOS tube MN12 is connected with the input terminal of row phase inverter；The drain electrode of 11st NMOS tube MN11 is also
It is connected with the first input end of the first row latch, the second input terminal of the first row latch also connects with the input terminal of row phase inverter
Connect, the output terminal of the first row latch is connected with digital quantizer 20.
Optionally, in the present embodiment, each second switch circuit is connected with a single photon detection unit.
Each second switch circuit includes the 13rd NMOS tube MN13, the 14th NMOS tube MN14, the 15th NMOS tube
MN15, the second row pull-up resistor R2 and the second row latch；
The grid of 13rd NMOS tube the MN13 grid with the 14th NMOS tube MN14, the 15th NMOS tube MN15 respectively
The output terminal connection of the holding circuit 302 of grid and single photon detection unit, the drain electrode and the 9th of the 13rd NMOS tube MN13
After the drain electrode short circuit of NMOS tube MN9, the input terminal of row phase inverter, the source electrode and the 14th of the 13rd NMOS tube MN13 are additionally coupled to
The source electrode of NMOS tube MN14, the 15th NMOS tube MN15 source shorted after be grounded；
The drain electrode of 14th NMOS tube MN14 by the second row after the drain electrode short circuit of the 15th NMOS tube MN15 with pulling up electricity
Resistance R2 connects high level (VDD), and the connecting node of drain electrode with the drain electrode of the 15th NMOS tube MN15 of the 14th NMOS tube MN14 is also
It is connected with the first input end of the second row latch, the second input terminal of the second row latch also connects with the input terminal of row phase inverter
Connect, the output terminal of the second row latch is connected with digital quantizer 20.
Optionally, in the present embodiment, shared circuit 303 further includes the first delay circuit and the second delay circuit, and first prolongs
When be electrically connected between the grid of the tenth NMOS tube MN10 and the grid of the 11st NMOS tube MN11, the second delay circuit connection
Between the grid of the 14th NMOS tube MN14 and the grid of the 15th NMOS tube MN15.
As shown in figure 4, it is the present invention 303 schematic circuit diagram of shared circuit.
In the schematic circuit diagram, the circuit that two row pixels (the first SPAD and the 2nd SPAD) share a TDC is illustrated
Figure, wherein, first switch circuit includes the 9th NMOS tube MN9, the tenth NMOS tube MN10, the 11st NMOS tube MN11, the 12nd
NMOS tube MN12, the first delay circuit, the 3rd delay circuit, row phase inverter, row latch, the first row latch, row pull-up electricity
Hinder R0 the first row pull-up resistors R1；Second switch circuit includes the 13rd NMOS tube MN13, the 14th NMOS tube MN14, the 15th
NMOS tube MN15, the second delay circuit, the second row latch and the second row pull-up resistor R2.
The grid of the grid of 9th NMOS tube the MN9 grid with the tenth NMOS tube NM10, the 11st NMOS tube NM11 respectively
And output terminal (SPAD_TRIGGER1) connection of the holding circuit 302 of single photon detection unit, the leakage of the 9th NMOS tube MN9
Pole is connected by row pull-up resistor R0 with high level (VDD), and the drain electrode of the 9th NMOS tube MN9 is also latched by row phase inverter and row
The input terminal connection of device, meanwhile, the drain electrode of the 9th NMOS tube is connected with the drain electrode of 13 NMOS tube MN13, the 9th NMOS tube MN9
Source electrode with being grounded again after the source electrode of the tenth NMOS tube MN10 and the source shorted of the 11st NMOS tube MN11, row latch it is defeated
Outlet (SPAD_COLUMN_1) is connected with main control processor 10, is handled by SPAD_COLUMN_1 output address datas to master control
Device 10；And first delay circuit be connected between the grid of the tenth NMOS tube MN10 and the grid of the 11st NMOS tube MN11.The
The drain electrode of ten NMOS tube MN10 by the first row pull-up resistor R1 after the drain electrode short circuit of the 11st NMOS tube MN11 with connecing high level
(VDD), the source electrode of the tenth NMOS tube MN10 after the source electrode MN11 short circuits of the 11st NMOS tube with being grounded；Tenth NMOS tube MN10's
Source electrode of the source electrode also with the 12nd NMOS tube MN12 is connected, and the grid of the 12nd NMOS tube MN12 is connected with row latch, and the tenth
The drain electrode of two NMOS tube MN12 is connected with the input terminal of row phase inverter；The drain electrode of 11st NMOS tube MN11 is also latched with the first row
The input terminal connection of device, the output terminal (SPAD_ROW_1) of the first row latch are connected with digital quantizer 20, the 3rd delay electricity
Road is connected between the drain electrode of input terminal and the 12nd NMOS tube MN12 of row phase inverter.
The grid of 13rd NMOS tube the MN13 grid with the 14th NMOS tube MN14, the 15th NMOS tube MN15 respectively
Output terminal (SPAD_TRIGGER2) connection of the holding circuit 302 of grid and single photon detection unit, the 13rd NMOS tube
The drain electrode of MN13 is with after the drain electrode short circuit of the 9th NMOS tube MN9, being additionally coupled to the input terminal of row phase inverter, the 13rd NMOS tube
The source electrode of MN13 after the source electrode of the 14th NMOS tube MN14, the source shorted of the 15th NMOS tube MN15 with being grounded；
The drain electrode of 14th NMOS tube MN14 by the second row after the drain electrode short circuit of the 15th NMOS tube MN15 with pulling up electricity
Resistance R2 connects high level (VDD), and the connecting node of drain electrode with the drain electrode of the 15th NMOS tube MN15 of the 14th NMOS tube MN14 is also
It is connected with the input terminal of the second row latch, output terminal (SPAD_ROW_2) and the digital quantizer 20 of the second row latch connect
Connect, the second delay circuit is connected between the grid of the 14th NMOS tube MN14 and the grid of the 15th NMOS tube MN15.
As shown in Figure 4, each group of multiple single photon detection units share a TDC by arranging, wherein, pass through SPAD_
COLUMN_1 exports column address data, and SPAD_ROW is used for output pulse signal, i.e., as shown in Figure 4, when gating first
During SPAD1, photon detection is carried out by first SPAD1, and the pulse signal that first SPAD1 is produced is exported by SPAD_ROW_1
To digital quantizer 20, time interval is calculated according to the pulse signal received by digital quantizer 20.
In other words, SPAD_TRIGGER ends are connected by controllable active quenching circuit 301 with shared circuit 303, by sharing
Circuit 303 using SPAD_TRIGGER signals read as TDC input signal, and by the geocoding of the SPAD of snowslide export to
Main control processor 10, sharing circuit 303 by this can realize that multiple SPAD share a TDC in a row.As shown in figure 4, this is common
Enjoying circuit 303 has two signal inputs, is respectively SPAD_TRIGGER1 and SPAD_TRIGGER2, in each single photon detection
In unit, whether the SPAD_EN controls SPAD in quenching circuit 301 therefore, passes through control in the state for detecting photon
SPAD_EN1 and SPAD_EN2 can allow SPAD1 and SPAD2 to be operated in different laser pulse periods, therefore, same to swash
Only have a SPAD_TRIGGER to export a pulse in the light pulse cycle.When any of each group of single-photon detecting slowdown monitoring circuit 30
After SPAD is strobed, if the SPAD receives photon generation snowslide, its avalanche signal can reflect on SPAD_ROW rapidly, make
For the input signal of TDC, for calculating the TOF times, and the address date of the SPAD is read by SPAD_COLUMN.
As shown in figure 5, the oscillogram of detector first two columns pixel during photon detection is carried out for the present embodiment, root
According to diagram, in same row, only a line SPAD is in acquisition mode in the same cycle, remaining SPAD is in inoperative shape
SELECT_ROW_ is to exercise energy control signal in state, wherein figure, in same row, can only have a line SPAD to enter detection shape every time
State；PHOTON_ represents a SPAD and receives a photon, and SPAD_COLUMN_ represents column address coding, and SPAD_ROW_ is represented
Row address encodes.
Above example only technical concepts and features to illustrate the invention, its object is to allow person skilled in the art
Scholar can understand present disclosure and implement accordingly, can not limit the scope of the invention.It is all to be wanted with right of the present invention
The equivalent changes and modifications that scope is done are sought, the covering scope of the claims in the present invention should all be belonged to.
It should be appreciated that for those of ordinary skills, can according to the above description be improved or converted,
And all these modifications and variations should all belong to the protection domain of appended claims of the present invention.
Claims (10)
1. a kind of single-photon detector of shared digital quantizer, it is characterised in that including N group single-photon detectings slowdown monitoring circuit, N number of number
Word converter and main control processor, the main control processor are connected with the N groups single-photon detecting slowdown monitoring circuit, each group of single photon
Detection circuit is connected with a digital quantizer, and each group of single-photon detecting slowdown monitoring circuit includes multiple single photon detection units, and one
A digital quantizer is connected with multiple single photon detection units；N is the positive integer more than 1；
The main control processor is used to export enabled control signal；
Single-photon detecting slowdown monitoring circuit described in each group, one and the enabled control signal pair are gated according to the enabled control signal
The single photon detection unit answered, for detecting photon and pulse signal being produced when receiving photon to the digital quantizer；
The digital quantizer, the time interval of photon transmission is calculated according to the pulse signal, and is sent to the master control
Processor；
The main control processor determines the distance between object and detector using the time interval, completes detection.
2. the single-photon detector of shared digital quantizer according to claim 1, it is characterised in that each described list
Photon detection unit includes a single-photon avalanche diode, quenching circuit and holding circuit；
The cathode of the single-photon avalanche diode connects positive high voltage power supply, and the anode of the single-photon avalanche diode is quenched with described
Go out the test side connection of circuit, the output terminal of the quenching circuit be connected with the input terminal of the holding circuit, and the holding is electric
The output terminal on road is connected with the digital quantizer, and the feedback end of the holding circuit and the reset terminal of the quenching circuit connect
Connect, the quenching circuit and the holding circuit are also connected with the main control processor respectively；
The enabled control signal of main control processor output is to the quenching circuit and holding circuit, so that the single-photon avalanche
Diode is in acquisition mode, and in the single-photon avalanche diode snowslide, by the quenching circuit quickly by snowslide
It is quenched, and controls the single-photon avalanche diode to return to acquisition mode by the holding circuit, while also passes through the guarantor
Hold circuit and send pulse signal to the digital quantizer.
3. the single-photon detector of shared digital quantizer according to claim 2, it is characterised in that the quenching circuit
Including the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, first and door, second and door and the first phase inverter, wherein,
The grid of first NMOS tube is connected with described first with the output terminal of door, the source electrode ground connection of first NMOS tube,
The drain electrode of first NMOS tube is connected with the anode of the single-photon avalanche diode；Described first with the first input end of door
It is connected by the reset terminal with the feedback end of the holding circuit, described first inputs the enabled control letter of termination with the second of door
Number；
The grid of second NMOS tube and drain electrode short circuit, the drain electrode of second NMOS tube also with two pole of single-photon avalanche
The anode connection of pipe, the source electrode of second NMOS tube are connected with the drain electrode of the 3rd NMOS tube, the 3rd NMOS tube
Source electrode is grounded, and the grid of the 3rd NMOS tube is connected with described second with the output terminal of door, and described second is defeated with the second of door
Enter end to be connected with the output terminal of first phase inverter, described second and the first input end of door connect enabled control signal, it is described
The input terminal of first phase inverter is connected with the anode of the single-photon avalanche diode；
First NMOS tube drain electrode also respectively with second NMOS tube drain electrode and first phase inverter input terminal
Connection, and the drain electrode of first NMOS tube connects with the drain electrode of second NMOS tube and the input terminal of first phase inverter
The node connect is the test side of the quenching circuit.
4. the single-photon detector of shared digital quantizer according to claim 3, it is characterised in that described first is anti-phase
Device includes the first PMOS tube and the 4th NMOS tube, wherein,
The grid of first PMOS tube is connected with the grid of the 4th NMOS tube, and the grid of first PMOS tube and institute
State anode of the connecting node of the grid of the 4th NMOS tube also with the single-photon avalanche diode to be connected, first PMOS tube
Drain electrode connect high level, the source electrode of first PMOS tube is connected with the drain electrode of the 4th NMOS tube, first PMOS tube
Source electrode be also connected with the connecting node of the drain electrode of the 4th NMOS tube with described second with the second input terminal of door, described
The source electrode ground connection of four NMOS tubes；
The source electrode of first PMOS tube and the connecting node of the drain electrode of the 4th NMOS tube are the defeated of first phase inverter
Outlet, the output terminal of the first anti-device and second with output that the connecting node of the second input terminal of door is the quenching circuit
End.
5. the single-photon detector of shared digital quantizer according to claim 2, it is characterised in that the holding circuit
Including the second phase inverter, the 3rd and door, the 4th and door, resistance and capacitance, wherein,
The input terminal of second phase inverter is connected with the output terminal of the quenching circuit, the output terminal point of second phase inverter
It is not connected with the described 3rd with the first input end of door and the 4th with the second input terminal of door, the output terminal of second phase inverter
Also pass sequentially through the resistance and capacity earth；Described 3rd with the second of door the enabled control signal of input termination, the described 3rd
It is connected with the output terminal of door with the digital quantizer；Described 4th is connected to the resistance and capacitance with the first input end of door
Between, the described 4th is connected with the output terminal of door with the reset terminal of the quenching circuit；
The input terminal of first phase inverter is the input terminal of the holding circuit, and the described 4th and the output terminal of door are the guarantor
Hold the feedback end of circuit, the described 3rd with output terminal that the output terminal of door is the holding circuit.
6. the single-photon detector of shared digital quantizer according to claim 5, it is characterised in that described second is anti-phase
Device includes the second PMOS tube and the 5th NMOS tube；
The grid of second PMOS tube is connected with the grid of the 5th NMOS tube, and the grid of second PMOS tube and institute
State output terminal of the connecting node of the grid of the 5th NMOS tube also with the quenching circuit to be connected, the second PMOS tube drain electrode connects
High level, the drain electrode of second PMOS tube are connected with the described 4th with door, and the source electrode of second PMOS tube meets the 5th NMOS
The drain electrode of pipe, the source electrode ground connection of the 5th NMOS tube, the source electrode of second PMOS tube and the drain electrode of the 5th NMOS tube
Connecting node be second phase inverter output terminal.
7. the single-photon detector of shared digital quantizer according to claim 6, it is characterised in that the described 4th and door
Including the 3rd PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th NMOS tube, the 7th NMOS tube and the 8th NMOS tube；
The grid of 3rd PMOS tube and the output terminal of second phase inverter, the 3rd with the first input end and the 6th of door
The grid connection of NMOS tube, drain electrode and the drain electrode of the 4th PMOS tube and the leakage of the 5th PMOS tube of the 3rd PMOS tube
Pole connects and is connected to the drain electrode of second PMOS tube, the source electrode of the 3rd PMOS tube and the source electrode of the 4th PMOS tube
Connect and be connected to the drain electrode of the 6th NMOS tube；
The grid of 4th PMOS tube is connected with the grid of the 7th NMOS tube, the drain electrode of the 6th NMOS tube also with institute
The grid for stating the 5th PMOS tube is connected with the grid of the 8th NMOS tube, the grid of the 7th NMOS tube also with the resistance
Connecting node connection between capacitance；The source electrode of 6th NMOS tube is connected with the drain electrode of the 7th NMOS tube, and the described 7th
The source electrode ground connection of NMOS tube；The source electrode of 5th PMOS tube is connected with the drain electrode of the 8th NMOS tube, the 8th NMOS
The source electrode ground connection of pipe；The drain electrode of 5th PMOS tube is connected with the drain electrode of the 4th PMOS tube；
The source electrode of 5th PMOS tube and the connecting node of the 8th NMOS tube are the described 4th and the output terminal of door.
8. the single-photon detector of shared digital quantizer according to claim 2, it is characterised in that single described in each group
Photon detection circuit further includes shared circuit, and multiple single photon detection units are turned by the shared circuit and a numeral
Parallel operation connects；
The shared circuit includes first switch circuit, and the first switch circuit is connected with a single photon detection unit；
The shared circuit further includes at least one second switch circuit, row latch, the first row latch, the 12nd NMOS
Pipe, row phase inverter, row pull-up resistor and the first row pull-up resistor, the first switch circuit include the 9th NMOS tube, the tenth
NMOS tube and the 11st NMOS tube；
The grid of 9th NMOS tube grid with the tenth NMOS tube, the grid of the 11st NMOS tube and described respectively
The output terminal connection of the holding circuit of single photon detection unit, the drain electrode of the 9th NMOS tube by the row pull-up resistor with
High level connects, and the drain electrode of the 9th NMOS tube is also connected by the row phase inverter with the input terminal of the row latch,
Meanwhile the drain electrode of the 9th NMOS tube is connected with least one second switch circuit, the source electrode of the 9th NMOS tube
Ground connection, the output terminal of the row latch are connected with the main control processor；
The drain electrode of tenth NMOS tube after the drain electrode short circuit of the 11st NMOS tube with passing through the first row pull-up resistor
High level is connect, the source electrode of the tenth NMOS tube after the source shorted of the 11st NMOS tube with being grounded；Tenth NMOS
Source electrode of the source electrode of pipe also with the 12nd NMOS tube is connected, and grid and the row latch of the 12nd NMOS tube connect
Connect, the drain electrode of the 12nd NMOS tube is connected with the input terminal of the row phase inverter；The drain electrode of 11st NMOS tube is also
It is connected with the first input end of the first row latch, the second input terminal of the first row latch is also anti-phase with the row
The input terminal connection of device, the output terminal of the first row latch are connected with the digital quantizer.
9. the single-photon detector of shared digital quantizer according to claim 8, it is characterised in that each described
Two on-off circuits are connected with a single photon detection unit,
Each described second switch circuit is including on the 13rd NMOS tube, the 14th NMOS tube, the 15th NMOS tube, the second row
Pull-up resistor and the second row latch；
The grid of 13rd NMOS tube grid with the 14th NMOS tube, the grid of the 15th NMOS tube respectively
And the output terminal connection of the holding circuit of the single photon detection unit, the drain electrode and the described 9th of the 13rd NMOS tube
After the drain electrode short circuit of NMOS tube, be additionally coupled to the input terminal of the row phase inverter, the source electrode of the 13rd NMOS tube with it is described
The source electrode of 14th NMOS tube, the 15th NMOS tube source shorted after be grounded；
The drain electrode of 14th NMOS tube by second row after the drain electrode short circuit of the 15th NMOS tube with pulling up electricity
Resistance connects high level, and the connecting node of drain electrode with the drain electrode of the 15th NMOS tube of the 14th NMOS tube is also with described the
The first input end connection of two row latch, the input of the second input terminal of the second row latch also with the row phase inverter
End connection, the output terminal of the second row latch are connected with the digital quantizer.
10. the single-photon detector of shared digital quantizer according to claim 9, it is characterised in that
The shared circuit further includes the first delay circuit and the second delay circuit, and first delay circuit is connected to described
Between the grid of ten NMOS tubes and the grid of the 11st NMOS tube, second delay circuit is connected to the described 14th
Between the grid of NMOS tube and the grid of the 15th NMOS tube.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110057457A (en) * | 2019-05-15 | 2019-07-26 | 南京邮电大学 | The concurrent detection circuit of photo-event and method of single photon 3D laser radar detection device |
| CN110134083A (en) * | 2019-04-28 | 2019-08-16 | 北京卫星制造厂有限公司 | A kind of cubicle switchboard configuration aerospace intelligent power distribution control device and method |
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| CN113759388A (en) * | 2020-06-02 | 2021-12-07 | 华中科技大学 | Time-of-flight measurement system and method of TDC-shared laser receiver |
| CN113759388B (en) * | 2020-06-02 | 2023-12-01 | 华中科技大学 | Time-of-flight measurement system and method of TDC shared laser receiver |
| CN114071040A (en) * | 2020-07-31 | 2022-02-18 | 宁波飞芯电子科技有限公司 | Image sensor and method for reading out signals |
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