CN108032875B

CN108032875B - Interlocking circuit, switching board and ground electronic unit

Info

Publication number: CN108032875B
Application number: CN201711106315.4A
Authority: CN
Inventors: 杨光伦; 王国英; 张轲
Original assignee: CRSC Research and Design Institute Group Co Ltd
Current assignee: CRSC Research and Design Institute Group Co Ltd
Priority date: 2017-11-10
Filing date: 2017-11-10
Publication date: 2021-01-22
Anticipated expiration: 2037-11-10
Also published as: CN108032875A

Abstract

The embodiment of the application discloses an interlocking circuit, a switching board and a ground electronic unit. Wherein the interlock circuit comprises: a first signal circuit for receiving a first signal and outputting a first output signal; a second signal circuit for receiving a second signal and outputting a second output signal; and the output circuit is used for mutually exclusive output of the first output signal and the second output signal. The interlocking circuit provided by the embodiment of the application is used in the switching board of the ground electronic unit, has a simple structure, and can be switched between two redundant signals instantly.

Description

Interlocking circuit, switching board and ground electronic unit

Technical Field

The present application belongs to the field of circuits, and more particularly, to an interlock circuit used in a ground electronic unit.

Background

A transponder Transmission system (BTS) is a safety Transmission system based on point information Transmission, and realizes safety information Transmission between roadside equipment or ground equipment and vehicle-mounted equipment. The transponder transmission system comprises three basic components, namely a transponder transmission module (BTM), a vehicle-mounted Antenna Unit (AU), an active transponder (Controlled Balise), a passive transponder (Fixed Balise) and a ground electronic unit (LEU).

The transponder installed in the center of the track does not need an external power supply, the BTM continuously radiates energy to the ground through the antenna unit AU during the running of the train, the transponder receives the power radiated by the antenna unit to work, internal coded information or coded information (only limited by an active transponder) of a ground electronic unit (LEU) is sent to the vehicle-mounted antenna AU, the vehicle-mounted antenna transmits a received uplink signal to the BTM, and the BTM sends the received data to the vehicle-mounted control core.

The LEU equipment comprises a switching board, and the switching board adopts relay logic and is responsible for selecting the final output of two paths of redundant interface signals when the LEU is in redundant use.

In the prior art, the switching of two redundant interface signals generally adopts manual switching or automatic switching, but the manual switching causes untimely switching, for example, when a system a fails, a worker finds that the system a fails first and then can switch to a system B; the existing automatic switching has complex circuits, and no simple scheme can realize the automatic switching of redundant interface signals at present.

Disclosure of Invention

The embodiment of the invention provides an interlocking circuit which is applied to a switching board in a ground electronic unit and realizes automatic switching of redundant interface signals by using a simpler circuit.

In one aspect, an embodiment of the present invention provides an interlock circuit, including:

a first signal circuit for receiving a first signal and outputting a first output signal;

a second signal circuit for receiving a second signal and outputting a second output signal;

and the output circuit is used for mutually exclusive output of the first output signal and the second output signal.

Further, the first signal circuit includes:

a first power supply;

a first relay including a first normally closed contact and a first normally open contact;

the second signal circuit includes:

a second power supply;

a second relay including a second normally closed contact and a second normally open contact;

the output end is composed of a first normally open contact and a second normally open contact.

Further, the first signal circuit further includes:

and the base electrode of the first triode receives the first signal, the collector electrode of the first triode is connected with the first relay, and the emitter electrode of the first triode is grounded.

The second signal circuit further includes:

and the base electrode of the second triode receives the second signal, the collector electrode of the second triode is connected with the second relay, and the emitter electrode of the second triode is grounded.

Further, the second circuit further includes:

and the delay circuit is used for delaying the time when the second circuit receives the second signal.

Furthermore, the delay circuit comprises a third power supply, a first resistor and a first capacitor, wherein two ends of the first resistor are respectively connected with the power supply and the first capacitor, the other end of the first capacitor is grounded, and power is supplied to the second circuit through a connection point of the first resistor and the first capacitor.

Further, the first and second circuits further include first and second and gate circuits, the first and second signals are input to the first and second circuits through output interfaces of the first and second and gate circuits, respectively, and the third power supply supplies power to the second and gate circuit.

Further, the first circuit further comprises a fourth power supply for supplying power to the first and gate circuit.

Further, the first signal and the second signal are processor signals of two systems respectively.

On the other hand, an embodiment of the present invention further provides a switch board, which is characterized by including: interlock circuit as described above

On the other hand, an embodiment of the present invention further provides a ground electronic unit, which is characterized by including: the switch plate.

Through the technical scheme, the circuit of the switching board in the prior art is simplified, and the complexity and the manufacturing cost of the circuit of the switching board are reduced.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application.

FIG. 1 is a schematic diagram of a typical application scenario of an embodiment of the present application;

fig. 2 is a schematic structural diagram of a switching plate in an embodiment of the present application;

fig. 3 is a schematic diagram of an interlock circuit provided in an embodiment of the present application.

Detailed Description

In order to make the objects, features and advantages of the present invention more apparent and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It will be understood by those within the art that the terms "first", "second", etc. in this application are used only to distinguish one device, module, parameter, etc., from another, and do not denote any particular technical meaning or necessary order therebetween.

Fig. 1 is a typical application scenario of the interlock circuit in the embodiment of the present application. As shown in fig. 1, which is a schematic structural diagram of an LEU device, a main function of the LEU device is to select an appropriate message or extract a message in communication data of an interface "S" according to an external input state (a serial input, a relay node state, or a current state) of the interface "S" and send the message to an active transponder through the interface "C". The LEU equipment mainly comprises a processing board, an output board, a monitoring board, an acquisition board and a switching board, and the circuit boards can be independent hardware circuit boards and also can be functional modules on the whole circuit board. The safety acquisition and acquisition self-checking functions of the LEU equipment are distributed in an acquisition board, and the functions of interface S communication data processing, message selection, equipment self-checking and the like are distributed in a processing board. The output board is responsible for carrying out DPBL coding on the transmission message sent by the processing board, converting the transmission message into a signal meeting the requirement of the interface 'C' index and sending the signal to the active responder. The switching board adopts relay logic and is responsible for selecting the final output of two paths of redundant interface signals when the LEU is in redundant use. The monitoring board monitors and records various operation state data in the LEU operation process.

The embodiment of the invention aims at the switching circuit in the switching board, and the interlocking of two redundant systems is realized by using a simpler circuit.

Fig. 2 is a schematic diagram of a switch board according to an embodiment of the present invention. The A-series equipment and the B-series equipment are mutually redundant equipment, and the switching board switches between the two systems. Specifically, the switching board switches and outputs according to the health states of the CPUs of the system A and the system B, when the CPU signals of the processing boards of the system A and the system B are healthy, the switching board preferentially outputs 4 paths of interface signals of the interface C of the system A through the motherboard, when the CPU signals of the system A are abnormal, the switching board switches the interface signals of the interface C from the system A to the system B, at the moment, the system A is in a recovery state, and the motherboard always keeps the interface output of the interface C of the system B unless the system B fails; similarly, when the CPU signal of the system B is abnormal, the switching board switches the output of the interface signal of "C" from the system B to the system a, and at this time, the system B is in a recovery state, and the motherboard also keeps the output of the interface of "C" of the system a all the time unless the system a fails. The two relays are interlocked, and the connection states are opposite. The output states of the interface signals of the system A and the system B are required to be output to a processing board and a monitoring board of the system A and the system B. The switchboard also comprises voltage conversion circuitry to convert the supply voltage to a suitable on-board voltage, such as 24V, 5V or 1.8V, etc. The switch board further includes a delay circuit for delaying the CPU signal of the system B to achieve the effect of preferentially outputting the CPU signal of the system a, which will be described in detail below.

FIG. 3 is a schematic diagram of an interlock circuit according to an embodiment of the present invention. The circuit controls relay coils of signal output channels of 'C' interfaces of the A-series equipment and the B-series equipment to be mutually connected to a group of normally closed contacts of a relay of an opposite system, and the switched signals are output through the normally open contacts, so that the technical effect that the A-series equipment and the B-series equipment can only have one output at most at the same time is achieved.

Specifically, the circuit mainly comprises three parts, wherein the first part is used for processing input signals of the A-series equipment, the second part is used for processing input signals of the B-series equipment, and the third part is used for outputting the A-series equipment and the B-series equipment to a motherboard.

The first part of the circuit comprises an AND gate circuit, the circuit comprises a power supply A _ VCC1 and a ground terminal A _ GND, two input ends and an output end, the two input ends respectively input two signals CPU _ A1 and CPU _ A2 which represent the health state of the CPU of the A-series equipment, when the two signals are healthy, the CPU _ A signal is high level, when the working state is abnormal, the CPU _ A signal is low level, and the signal CPU _ A is output to an interlocking circuit of a switching board; the first part also comprises a triode A _ Q, a power supply A _ VCC and a relay A _ K1, wherein the relay A _ K1 comprises a coil A _ K1A, a normally closed contact A _ K1B and a normally open contact A _ K1C.

The second part of the circuit comprises an AND gate circuit, the circuit comprises a power supply B _ VCC 1' and a ground terminal A _ GND, two input ends and an output end, the two input ends respectively input two signals CPU _ B1 and CPU _ B2 which represent the health state of the CPU of the B-system equipment, when the two signals are healthy, the CPU _ B signal is high level, when the working state is abnormal, the CPU _ B signal is low level, and the signal CPU _ B is output to an interlocking circuit of the switching board; the second part also comprises a triode B _ Q, a power supply B _ VCC and a relay B _ K1, wherein the relay B _ K1 comprises a coil B _ K1A, a normally closed contact B _ K1B and a normally open contact B _ K1C; the second part also comprises a delay circuit, as shown in fig. 3, the delay circuit comprises a power supply B _ VCC1, a resistor B _ R1 and a capacitor B _ C4, the power supply B _ VCC1 is connected with the resistor B _ R1, the other end of the resistor B _ R1 is connected with the capacitor B _ C4, the other section of the capacitor B _ C4 is grounded, and the power supply B _ VCC 1' is delayed to supply power to the and gate through the resistor B _ R1, so as to delay the output of the CPU _ B signal. In a preferred embodiment, the resistance of the resistor in the delay circuit is 121K, the capacitance of the capacitor is 100 μ F, and the CPU _ B signal is delayed for at least 1 second.

In the circuit, a signal CPU _ A of the A-series equipment is output to a base electrode of a triode A _ Q, one end of a coil A _ K1A of a relay A _ K1 is connected with a collector electrode of the triode A _ Q, a normally closed contact A _ K1B of a relay A _ K1 is connected with a power supply B _ VCC and a coil B _ K1A of a relay B _ K1, and a normally open contact of a relay A _ K1 is connected with an output end A _ Sout of the first circuit and an output end Sout of a motherboard and used as a switch between the two output ends; the signal CPU _ B of the B series equipment is output to the base electrode of the triode B _ Q, one end of a coil B _ K1A of a relay B _ K1 is connected with the collector electrode of the triode B _ Q, a normally closed contact B _ K1B of a relay B _ K1 is connected with a power supply A _ VCC and a coil A _ K1A of the relay A _ K1, and a normally open contact of a relay B _ K1 is connected with an output end B _ Sout of the first circuit and an output end Sout of a motherboard and used as a switch between the two output ends.

In the circuit, after the A-series equipment and the B-series equipment are normally started, the relays A _ K1 and the coils A _ K1A and B _ K1A of the B _ K1 are not electrified, the normally closed contacts A _ K1B and B _ K1B are closed and switched on, and under the action of the delay circuit, the level of the AND gate circuit rises and slows down, the power-on delay is realized, the output of the AND gate circuit is delayed, so that the signal CPU _ A is changed into high level before the signal CPU _ B, the collector current of the triode A _ Q rises after the level of the signal CPU _ A rises, the coil A _ K1A is electrified, the normally closed contact A _ K1B is disconnected, and the normally open contact A _ K1C is switched on. The normally closed contact A _ K1B is opened to make the triode B _ Q in a cut-off state, even if the level of the signal CPU _ B rises, the coil B _ K1A can not be electrified, so the normally open contact B _ K1C is opened, and the normally open contact A _ K1C is closed to make the output select A series device signal output.

When the A-series equipment is in fault and the B-series equipment is normal, the signal CPU _ A changes to low level, the relay coil A _ K1A is powered off, the normally closed contact A _ K1B is switched on, the signal CPU _ B is at high level at the moment, the relay coil B _ K1A is powered on, the normally closed contact B _ K1B is switched off, and the normally open contact B _ K1C is switched on. Since the normally closed contact B _ K1B is opened, the relay coil a _ K1A cannot be energized even after the signal CPU _ a is restored to the high level. And the normally open contact B _ K1C is turned on to output the device signal of the selection B.

The power supplies a _ VCC, AVCC1, B _ VCC, and B _ VCC1 may use the same or different levels depending on actual circuit requirements. The circuit may further include some peripheral circuits or components, as shown in fig. 3, the signal CPU _ a is grounded through the resistors a _ R5 and a _ R8, the power supplies a _ VCC1 and a _ VCC are grounded through the capacitors a _ C7 and a _ C8, and a diode connected in parallel with the transistor, and these circuits and components play a role of stabilizing and protecting the circuit, and those skilled in the art may add and delete the parameters, such as resistance and capacitance, of the above components according to actual needs, and may also set according to actual needs, without affecting the implementation of the embodiment of the present invention, and the embodiment of fig. 3 is only a possible design and does not limit the present invention.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the embodiments of the present invention, and those skilled in the art should make appropriate changes or modifications based on the concept of the present invention, which fall within the scope of the present invention.

Claims

1. An interlock circuit for use in a switchboard for a ground electronics unit, the interlock circuit comprising:

the output circuit is used for mutually exclusive outputting a first output signal and a second output signal;

the first signal circuit and the second signal circuit also comprise a first AND gate circuit and a second AND gate circuit, and the first signal and the second signal are respectively input into the first circuit and the second circuit through output interfaces of the first AND gate circuit and the second AND gate circuit;

the first signal circuit includes:

a first power supply;

the second signal circuit includes:

a second power supply;

the output circuit is composed of a first normally open contact and a second normally open contact, and when the second normally closed contact of the second relay is disconnected, the first relay cannot be electrified or the first normally closed contact of the first relay is disconnected, so that the second relay cannot be electrified.

2. The interlock circuit of claim 1, wherein:

the first signal circuit further includes:

a base electrode of the first triode receives the first signal, a collector electrode of the first triode is connected with the first relay, and an emitting electrode of the first triode is grounded;

the second signal circuit further includes:

3. The interlock circuit of claim 2, wherein:

the second circuit further comprises:

4. The interlock circuit of claim 3, wherein:

the delay circuit comprises a third power supply, a first resistor and a first capacitor, wherein two ends of the first resistor are respectively connected with the power supply and the first capacitor, the other end of the first capacitor is grounded, and power is supplied to the second circuit through a connecting point of the first resistor and the first capacitor.

5. The interlock circuit of claim 4, wherein:

and the third power supply supplies power to the second AND gate circuit.

6. The interlock circuit of claim 5 wherein:

the first circuit further comprises a fourth power supply for supplying power to the first and gate circuit.

7. The interlock circuit of claim 1, wherein:

the first signal and the second signal are processor state signals of two systems respectively.

8. A switchboard, characterized in that it comprises: the interlock circuit of any one of claims 1-7.

9. A ground electronics unit, comprising: the paddle of claim 8.