CN108024851A - Implanted device and its manufacture method - Google Patents

Implanted device and its manufacture method Download PDF

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Publication number
CN108024851A
CN108024851A CN201680049872.4A CN201680049872A CN108024851A CN 108024851 A CN108024851 A CN 108024851A CN 201680049872 A CN201680049872 A CN 201680049872A CN 108024851 A CN108024851 A CN 108024851A
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CN
China
Prior art keywords
packaging
biocompatibility
parylene
chip
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201680049872.4A
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Chinese (zh)
Inventor
戴聿昌
张瀚杰
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California Institute of Technology CalTech
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California Institute of Technology CalTech
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Publication date
Priority claimed from US14/838,788 external-priority patent/US10008443B2/en
Application filed by California Institute of Technology CalTech filed Critical California Institute of Technology CalTech
Publication of CN108024851A publication Critical patent/CN108024851A/en
Pending legal-status Critical Current

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    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
    • A61N1/00—Electrotherapy; Circuits therefor
    • A61N1/02—Details
    • A61N1/04—Electrodes
    • A61N1/05—Electrodes for implantation or insertion into the body, e.g. heart electrode
    • A61N1/0526—Head electrodes
    • A61N1/0543—Retinal electrodes
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
    • A61N1/00—Electrotherapy; Circuits therefor
    • A61N1/18—Applying electric currents by contact electrodes
    • A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
    • A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
    • A61N1/372—Arrangements in connection with the implantation of stimulators
    • A61N1/375—Constructional arrangements, e.g. casings
    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61N—ELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
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    • A61N1/32—Applying electric currents by contact electrodes alternating or intermittent currents
    • A61N1/36—Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
    • A61N1/372—Arrangements in connection with the implantation of stimulators
    • A61N1/375—Constructional arrangements, e.g. casings
    • A61N1/3758—Packaging of the components within the casing
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    • A61F—FILTERS IMPLANTABLE INTO BLOOD VESSELS; PROSTHESES; DEVICES PROVIDING PATENCY TO, OR PREVENTING COLLAPSING OF, TUBULAR STRUCTURES OF THE BODY, e.g. STENTS; ORTHOPAEDIC, NURSING OR CONTRACEPTIVE DEVICES; FOMENTATION; TREATMENT OR PROTECTION OF EYES OR EARS; BANDAGES, DRESSINGS OR ABSORBENT PADS; FIRST-AID KITS
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Abstract

The present invention provides the packing chip and technique for assembling retina prosthetic appliance.Advantageously, using photo-patterned adhesive or epoxy resin such as photoresist as glue chip is attached to aimed thin film (for example, Parylene) substrate so that chip is used as the annex for preventing layering.

Description

Implanted device and its manufacture method
Cross reference to related applications
This application claims the priority for the U.S. Patent Application No. 14/838,788 submitted for 28th in August in 2015, the Shen Please be the part continuation application for the U.S. Patent Application No. 13/830,272 submitted on March 14th, 2013, this application number 13/830, 272 require the priority of U.S. Patent Application No. 61/640,569 submitted on April 30th, 2012, for all purposes by them Disclosure be integrally incorporated with it accordingly by quoting.
Statement on the right of invention carried out under the research or development that federal government subsidizes
The present invention is in the case where U.S. government supports, is done under the fund ECC0310723 that National Science Foundation subsidizes Go out.Government has some rights to the present invention.
Invention field
In general, the present invention relates to biomedical implants, and more particularly to the life using Parylene substrate Thing medical implant, Parylene substrate allow to include semiconductor chip or other prefabricated electric component such as transistors, The whole connections and manufacture of the biomedical implants of resistor, capacitor or inductor.
Background of invention
One of ultimate challenge that prothesis implant body must pull against is the reliable bag of integrated circuit (IC) chip and biological device Dress, to bear corrosive body fluids.It is especially true for complicated neural implant and retinal implant, because may need Hundreds of or thousands of electrodes are wanted to be connected to necessary IC chip (referring to K.D.Wise et al., International Conference of the Engineering in Medicine and Biology Society on Neural Engineering 2007, the 398-401 pages).In contrast, pacemaker only has a stimulation channels, and cochlea implantation Thing only needs 5 to 6 stimulating electrodes just to recover the Listening Ability of Ethnic of impaired subjects (referring to K.Najafi et al., IEEE Conference on Nano/Micro Engineered and Molecular Systems, 2004, the 76-97 pages).This Outside, in order to avoid possible infection and medical complications, it is generally desirable to prosthetic appliance is fully located at the internal of subject.This meaning Taste integrating, even for the IC chip for high lead count implant device (high-lead-count implant device) Connect has high request with packing technique.It is as indicated previously, can be by conductive epoxy resin technique in Parylene-C Be aligned between interface and high-density multi-channel chip electrical connection (referring to, Jay H.C.Chang, Ray Huang and Y.C.Tai, Proc.TRANSDUCERS 2011, the 378-381 pages), wherein PDMS moulds are used to accommodate IC chip and fill When safety scraper buffering area.However, its it is too big so that it cannot in the eyeball of implantation people (<1cm3~2cm3) (referring to, M.Humayun et al., Vision Research, 43 (2003), the 2573-2581 pages).Further, since bonding is only relied upon and led Electric 2% of epoxy resin contact less than total connection area, even so also holding when small power is applied to the device of assembling Easily it is layered.This during operation can especially severe.Since intraocular retina prosthese of future generation needs that coil, electricity will be included The whole device of pole, stimulating chip and other ASIC is installed in the eyeball of people, it is therefore necessary to according to size and operative complications Both further design device.
Parylene-C has become the popular materials for the application of BioMEMS implants due to its superior performance (referring to, J.H.Chang et al., Proc.TRANSDUCERS 2011, the 390-393 pages；J.H.Chang et al., Proc.NEMS 2011, the 1067-1070 pages).It also served as combined for silicon wafer intermediate layer (referring to, H.Noh et al., J.Micromech.Microeng.14 (2004), 625；H.Kim et al., J.Microelectromech.Syst.14 (2005), 1347-1355).However, the combination between Parylene-C and silicon is still problematic.
In the presence of the kinds of processes for packing integrated circuit (IC) bare chip (dice).Some packing techniques cover will be more Kind electronic device (such as integrated circuit, such as passive device of inductor, capacitor or resistor) is merged into individual packaging Electronic module establishment.Although the progress of the prior art, although and being opened with microelectromechanical systems (MEMS) technology Implantable device has been sent out, but has stilled need more preferable packing technique, especially for the retina and nerve scaffold of high lead count Thing.The present invention provides these and other demands.
Invention summary
The present invention provides substrate, for being assembled into IC chip for the thin of medical implant such as retinal implant The method and technique of film substrate such as Parylene substrate.Advantageously, packing technique of the invention can be used for as low as 36mm2Area in produce the connection of 10,000 or more, this is rational chip ruler for retinal implant It is very little.The present invention provides the method for improving packing technique.
Therefore, in one embodiment, it is used to manufacture the film-substrate for attachment arrangement the present invention provides a kind of Such as the method for Parylene substrate, including：
The first film layer such as parylene layer is deposited on silicon to form bottom thin film layer；
Metal deposit to bottom parylene layer is electrically connected with being formed；
Second film layer such as parylene layer is deposited into and is adjacent to metal to form top foil layer and film gold Belong to thin film sandwich (sandwich) (for example, Parylene-metal-Parylene interlayer)；
The mask for being adjacent to top foil layer is provided；With
Etching bundle is directed on mask to manufacture the film-substrate for attachment arrangement (for example, Parylene serves as a contrast Bottom).
In another embodiment, the film-substrate the present invention provides the technique manufacture by the present invention is (for example, poly- Paraxylene substrate).The substrate is useful for the IC chip of high lead count implanted device to integrated, connection and packaging.
In order to verify this technology, be designed with 268 connections simulate the chips of the actual IC chip developed by with In measurement connection yield (connection yield).In addition, scraper connection is being carried out by thick Parylene-C coatings After encapsulation, the chip connected undergoes Accelerating immersion test in high temperature saline solution.The result shows that this technology provides High connection yield.
In another embodiment, the present invention provides one kind be used for by integrated circuit be assembled to film-substrate (for example, Parylene substrate) method, including：
Photo-patterned adhesive or epoxy resin are spin-coated to integrated circuit (IC) to form the IC of covering；
Shelter the IC of covering；With
The IC of covering is patterned using photoetching process and pads (bonding with multiple combinations on exposure I C chips Pad) it is integrated into forming patterned IC in film-substrate (for example, Parylene substrate).
In still other embodiment, the present invention provides a kind of non-biocompatible thin film's (example for attachment arrangement Such as, Parylene) substrate, including：
The first film (for example, Parylene) layer；
Metal, it is adjacent to the first film layer；
Second film (for example, Parylene) layer, its be adjacent to metal with formed film metal thin film sandwich (for example, Parylene-metal-Parylene interlayer), wherein the second film layer has opening, which has the table that sets within it At least one electric contact on face, the opening be configured to receive at least one circuit device and at least one electric contact with There is provided between at least one circuit device and be electrically communicated (electrical communication), non-biocompatible thin film (for example, Parylene) substrate is configured to be implanted in living organism after at least one circuit device is received.
In some aspects, the device with least one circuit is integrated circuit (IC) chip.In addition, on the one hand, should Device such as IC chip is electrically connected by conductive epoxy resin scraper and is integrated into substrate.Preferably, the device by as The photo-patterned adhesive or photoresist of machinery glue are integrated into substrate.
In another embodiment, the present invention provides：
A kind of biocompatibility packaging for low-density connection, including：
Feedthrough layer (feedthrough layer)；
In the application-specific integrated circuit (ASIC) of feedthrough layer downwardly over；
The printed circuit board (PCB) (PCB) of ASIC is attached to, the printed circuit board (PCB) is suitable for off-chip components (off-chip Component) and conducting wire is bound to feedthrough layer；
The metallic walls of neighbouring feedthrough layer；And metal cover, the metal cover are used to encasing and manufacturing biocompatibility packaging.
When being read with reference to the detailed description and the accompanying drawings below, these and other aspect, target and embodiment will become Obtain more obvious.
Brief description
Figure 1A-Fig. 1 K show the flexible Parylene-C connection substrates and core of a kind of embodiment according to the present invention The manufacturing process that piece integrates.
Fig. 2A-Fig. 2 E show, be in fig. 2 the manufacture being connected with chip and discrete parts flexible Parylene- The schematic diagram of C substrates.Fig. 2 B show the back side in discrete parts region.Fig. 2 C show the close-up illustration of integrated chip；Fig. 2 D Show retina viscosity；Fig. 2 E show the eyes of the flexible Parylene-C substrates for the manufacture being connected with chip and integrate Schematic diagram.
Fig. 3 A- Fig. 3 B show the customization retainer for chip package technique.
Fig. 4 A- Fig. 4 C are shown, are the virtual chip for assembling yield test in Figure 4 A；Fig. 4 B-4C are shown Pad as alignment mark.
Fig. 5 A- Fig. 5 D are shown, are the AZ4620 not toasted in fig. 5；Fig. 5 B are shown in vacuum drying oven 140 DEG C baking continue 30 minutes AZ4620；Fig. 5 C and Fig. 5 D are shown is conducive to conduction by the slope (slope) formed of flowing back Epoxy resin feedthrough.
Fig. 6 A- Fig. 6 B show that glued area (gluing area) is about 2%, as shown in Figure 6A；Fig. 6 B show logical Crossing the extra photoresist as glue makes glued area increase to about 94% (2%+92%).
Fig. 7 shows the schematic diagram of the fixture as the combination tool in test sample.
Fig. 8 A- Fig. 8 B are shown, are the cross-section SEM images with reference to (2MPa, 130 DEG C) in fig. 8 a；Fig. 8 B are shown Adhesive interface after Parylene stripping.
Fig. 9 A- Fig. 9 C are shown, are the setting for measuring the dynamometer of peeling force in figure 9 a.Fig. 9 B, which are shown, to be tied Actual test sample after conjunction；Fig. 9 C show the schematic diagram of test sample.
Figure 10 shows the peeling force for various photo-patterned adhesives relative to combination temperature.
Figure 11 shows the peeling force for various photo-patterned adhesives relative to combination pressure.
Figure 12 A- Figure 12 B are shown, are the maximum peeling force of different photo-patterned adhesives in fig. 12；Figure 12B shows the peeling force for different photo-patterned adhesives relative to binding time.
Figure 13 A- Figure 13 C are shown, are that the surgical operation use being connected with silicon and discrete parts is poly- to two in figure 13a Toluene-C device；Figure 13 B and Figure 13 C show that metal gasket is exposed together with other regions being covered by adhesive.
Figure 14 shows the setting of measurement, wherein detection electrode array output (being placed in the electrode tip on macula lutea (macula)) To check connection.
Figure 15 shows the connection yield under 4 kinds of different conditions；In scraper connection, pass through Parylene-C coatings Encapsulate and carry out reliability test after Accelerating immersion in 90 DEG C of brine.
Figure 16 A- Figure 16 D are shown, are virtual chips in Figure 16 A, have 40 μm of 40 μ m pad size and 40 μm Interval；Figure 16 B show the connection between Parylene substrate and virtual chip；Figure 16 C show yield relative to lining The interval of pad；Figure 16 D show the length of side of the yield relative to pad.
Figure 17 shows a kind of embodiment of low-density packing technique.
Detailed description of the invention
I. embodiment
In general, the present invention relates to biomedical implants, and more particularly to film is used (for example, poly- to diformazan Benzene) substrate biomedical implants, which allows the biology for including semiconductor chip and/or other prefabricated electric components The whole connections and manufacture of medical implant.In one embodiment, it is used to manufacture the present invention provides one kind and is used to be attached The method of the film-substrate of device such as Parylene substrate, including：
The first film layer such as the first parylene layer is deposited on silicon to form bottom thin film layer；
Metal deposit to bottom thin film (for example, Parylene) layer is electrically connected with being formed；
Second film layer such as the second parylene layer is deposited into and is adjacent to metal, to form top foil layer and thin Film metallic film interlayer (for example, Parylene-metal-Parylene interlayer)；
The mask for being adjacent to top foil layer is provided；With
Etching bundle is directed on mask to manufacture the film-substrate for attachment arrangement (for example, Parylene serves as a contrast Bottom).The first film layer can be identical or different with the second film layer.Although Parylene is preferable substrate, this area Technical staff will be appreciated that the material can be other film polymers, such as polyimides, Teflon (Teflon), card Pu Dun (kapton) or printed circuit board (PCB) (PCB) and the like.The remainder of the application will use Parylene conduct Illustrative example.It can also use other films.
In some aspects, the present invention provides one kind to be used for for example flexible Parylene-C linings of Parylene-substrate The manufacturing process 100 at bottom.In a kind of exemplary, Figure 1A, which is shown, is deposited on such as HMDS processing of silicon substrate 110 Silicon wafer on 5 μm of first deposited parylene-c layer (bottom layer) 120, this contributes to the device to depart from, such as in distilled water Or in deionized water, preferably discharge in deionized water.
Next, as shown in fig. 1b, be adjacent to the first parylene layer 120 (bottom parylene layer) is gold Belong to 130, such as titanium/gold (Ti/Au) alloy for metal-stripping.The metal provides electrical connection.Second parylene layer 150 (top layers) for example thicker Parylene-C (about 40 μm) layers and then it is deposited to complete as is shown in fig. 1C poly- to two Toluene-metal-Parylene sandwich.The technique includes providing such as metal mask (for example, aluminium) of mask 160, it is heavy Product is Parylene-C etching masks to be etched through deposited parylene-c layer thick as shown in Figure 1 D.Finally, electrode Position 170,175 and device profile 180 are by reactive ion etching (for example, 2 step O as shown in fig. 1E2Plasma Etching) define or deep reactive ion etching (DRIE) can be used.Fig. 1 F show the yarn discharged from chip 110 (flex)。
Although foregoing example uses Parylene-C, the technique and embodiment of device herein are not limited to This.It can also use other Parylenes, for example, it is Parylene-N, Parylene-C, Parylene-D, poly- to two Toluene-HT, Parylene-AM, Parylene-A or combinations thereof.Parylene-C is preferable poly- to diformazan Benzene.Although Parylene is preferable substrate, it will be appreciated by those skilled in the art that the material can be other films Polymer, such as polyimides, Teflon, kapton or printed circuit board (PCB) (PCB) and the like.
The other materials designed available for substrate and/or carrier includes but not limited to silicon, glass, steel, G10-FR4 or any Other FR4 families epoxy resin etc..In some embodiments, silicon substrate is used only as carrier and is packing during manufacture Into being correspondingly removed before.In other embodiments, carrier remains the integral part of packaging.
In certain aspects, 1,1,1,3,3,3- hexamethyldisilazane (HMDS) place of the silicon wafer used in this method Reason.It will be appreciated by those skilled in the art that other processing can be used for discharging Parylene structure from silicon wafer.
In certain aspects, the first parylene layer 120 and the second parylene layer 150 pass through chemical vapor deposition (CVD) deposit on a silicon substrate.The first layer has thickness thick between about 0.1 μm to about 100 μm, for example, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm or 100 μm.Preferably, the thickness of the first parylene layer (bottom layer) Spend for thick between about 1 μm and about 10 μm, e.g., from about 1 μm, about 2 μm, about 3 μm, about 4 μm, about 5 μm, about 6 μm, about 7 μm, about 8 μ M, about 9 μm, or about 10 μ m-thicks.
Typically, 150 to the first parylene layer 120 of the second parylene layer (top layers) is thick.In an example In, the second parylene layer be it is thick between 10 μm and 200 μm, such as 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, 190 μm or 200 μm or it is even thicker.Preferably, the second parylene layer is thick between 20 μm and 60 μm, e.g., from about 20 μm, about 21 μm, about 22 μm, about 23 μm, about 24 μm, about 25 μm, about 26 μm, about 27 μm, about 28 μm, about 29 μm, about 30 μm, about 31 μm, about 32 μm, about 33 μm, about 34 μm, about 35 μm, about 36 μm, about 37 μm, about 38 μm, about 39 μm, about 40 μm, about 41 μm, about 42 μm, about 43 μm, about 44 μm, about 45 μm, about 46 μm, about 47 μm, about 48 μm, about 49 μm, about 50 μm, about 51 μm, about 52 μm, about 53 μm, about 54 μm, about 55 μm, about 56 μm, about 57 μm, about 58 μm, about 59 μm or about 60 μ m-thicks.
In certain aspects, the metal 130 for stripping is titanium/gold (Ti/Au) alloy.However, other suitable metals Include, but not limited to Cr/Au, Ni/Au, Ti/Au, Al/Ti, Ag/Ti, Cr/Au/Ti/Ni/Au, Ni/Pd/Au, Ti/ with alloy Ni/Au or combinations thereof.Those skilled in the art will know other metals for use in the present invention.
The technique includes providing mask, such as is deposited as Parylene-C etching masks and is gathered with being etched through second to two The metal mask that-C layers of toluene.In general, etching is the reactive ion etching (RIE) sheltered by metal mask.In addition, Deep reactivity can be used to etch (DRIE).Other suitable mask materials are also useful.RIE can be oxygen plasma erosion Carve.
It will be appreciated by those skilled in the art that the parylene layer of Parylene device described herein is not limited to Two parylene layers.In addition, the metal of Parylene device is not limited to single metal.Parylene device is based on Sandwich.As long as metal is sandwiched between top parylene layer and bottom parylene layer, it is possible to there is stacking Multiple layers on substrate.Furthermore it is possible to there are multiple masks to open electrode and define the profile of device (multiple devices).
In some examples, the technique of description is used to produce multiple Parylene-gold on carrier (for example, silicon wafer) Category-Parylene interlayer (sandwich layer), such as multiple interlayers, including 2,3,4,5,6,7,8 A, 9,10 or more Parylene-metal-Parylene interlayers.Although the technique just described produces 1 folder Layer, it will be understood by those skilled in the art that the technique can be repeated to generate any number of interlayer.
In terms of other are gone back, the present invention includes a kind of Parylene substrate manufactured by processes herein.It is such as following As more detailed description, the present invention provides Parylene substrate is attached a device to, such device includes for example collecting Into circuit and other discrete parts.
On the one hand, after yarn is released, ASIC is integrated with the yarn discharged.For example, Fig. 1 G are shown Previously it was aligned from the yarn of chip release with ASIC 185, wherein photo-patterned adhesive 182 is placed in mould 187. In Fig. 1 H, yarn is combined with PPA182 with ASIC185, and prepares to be used for conductive epoxy resin using 100 technique of scraper 189.As shown in Figure 1 I, after conductive epoxy resin doctor blade process, some conductive epoxy resins are left on the top surface Residue 189, this may cause defect (shortage).As shown in figure iJ, top cleaned with provide clean top surface with Avoid defect.In Fig. 1 J, conductive epoxy resin 183 is maintained in cavity and is connected with being formed between yarn and ASIC.Figure 1K shows release of the assembling device from mould.
In certain aspects, it is for example special integrated to assemble (host) for film of the invention (for example, Parylene) substrate The electronic unit of circuit (ASIC), the electronic unit are mutual via metallization trace e.g., from about 3.7 μm of wide metallization traces Connection.In one embodiment, manufactured flexible Parylene-C substrates are connected with IC chip and other discrete parts. It is some in terms of other in, substrate of the invention or micromodule include a variety of components, which includes, but not limited to one It is a or more integrated circuit, ASIC, interconnection layer, radiator, conductive via, passive device, MEMS device, sensor, prefabricated Electric component, transistor, resistor, capacitor, inductor, Micropump and wave filter.Component is to be permitted various ways cloth Put and be stacked in module.The layer and component of module can use various conventional wafer-level process technology such as spin coatings, photoetching And/or electroplate to deposit and handle.
Parylene packaging can include many other types of device and component in addition to those shown.Should Packaging can also include the active device and/or passive device of substantially any quantity.Such active device and/or passive device Example include resistor, capacitor, oscillator, magnetic core, MEMS device, sensor, battery, communicator, integrated film Battery structure, inductor and the like.These devices can be positioned in various positions within a package and/or be stacked on In various positions in packaging.Component can use the form of prefabricated discrete parts, or can be formed in situ.For producing One advantage of the technique based on photoetching of this packaging is that these components and miscellaneous part can be during the layering of packaging be formed It is formed in situ.That is, when being prefabricated, discrete parts can be placed in substantially any position within a package, and component can also make It is fabricated directly in for example conventional sputtering of any suitable technology and/or plating on the layer of any Photoimageable.
Turning now to Fig. 2A, show and connect with integrated chip 220 and discrete parts such as capacitor 211 and oscillator 217 The schematic diagram 200 of the manufactured flexible Parylene-C substrates 210 connect.In certain aspects, there is the more electric of output 232 Pole array 230 is placed on the macula lutea of human eye or the eyes of another mammal, and can be by retinal nail (retinal Tack) 235 (Fig. 2 D) is fixed.In one example, integrated discrete parts is placed on eyeball or in eyeball.Fig. 2 B are point The back side of vertical component area.Fig. 2 C show the close-up illustration of integrated chip.Fig. 2 E are to show electrod-array 241, integrate The schematic diagram of the eyes of the positioning of ASIC 245 and intraocular RF coils 250.
As shown in Figure 2 A, discrete parts such as capacitor 211 and oscillator 217 is mounted and passes through conductive epoxy Fat connection is electrically connected with being formed.In some examples, two notch or sewing hole are manufactured for device is fixed on eyeball 261st, in 265 (referring to Fig. 2 E).On the one hand, multiple electrode array 230 is placed on macula lutea and is consolidated by retinal nail 235 It is fixed.Fig. 2 E also show the electrod-array 241 in a notch 261 and the application-specific integrated circuit in another notch 265 245 it is integrated.Also show intraocular RF coils 250.Interconnecting parts are preferably about 0.1mm to about 6mm wide, e.g., from about 0.1mm, 0.2mm, 0.3mm, 0.4mm, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm, 2mm, 3mm, 4mm, 5mm or 6mm wide. In some examples, about 2mm wide is mutually linked as.In some examples, interconnection depends on being used for the incision size in epibulbar operation. However, in most of examples, width is about 2mm or 3mm.
In some examples, there is high density and multichannel to combine pad (for example, pad size is less than about 100 μ ms 100 μm；Be smaller than about 200 μm) IC chip can be connected by conductive epoxy resin technique with Parylene substrate. With larger combination pad other discrete parts such as cap and oscillator can use pin by conductive epoxy resin manually It is connected with Parylene substrate.Power supply and data coil with larger combination pad can also pass through conductive epoxy using pin Resin is manually connected with Parylene substrate.Then whole integrating device is fixed on inside eyeball by retinal nail (for example, close to electrod-array).
In another embodiment, the present invention provides for by flexible Parylene substrate and IC chip and other The method that discrete parts integrates.This method includes chip design photoetching, including photoresist rotation, baking, exposure (exposing) and develop and IC chip is integrated into flexible Parylene substrate.As shown in Figure 3A, IC chip component It can be completed in retainer 300 is customized.
In operation, chip 310,315,320 is fixed in retainer 300 first, and it is continuous in the retainer Complete to include photoresist rotation, baking, exposed and developed all chip design photoetching in ground.Passing through conductive epoxy resin After scraper connection is integrated with Parylene-C interface chips, chip 315 can be discharged from the back side of mould, this is conducive to entirely Device is implanted inside eyeball.Chip can be integrated and be packaged into flexible Parylene substrate.Typically, in customization The processing of IC chip is completed on chip design mould to form patterned IC chip.Fig. 3 A, which also show mould, can serve as use In the safety buffer zone of doctor blade process.The size and depth of mould are designed to adapt to the various sizes of chip.Fig. 3 B are shown The enlarged drawing of IC chip.
In an example of the doctor blade process of the present invention, commercially available conductive epoxy resin is mixed simultaneously well first It is applied on the surface at the edge of Parylene substrate.In some examples, Parylene substrate has in manufacturing process The hole being pre-designed and/or trap (well) that period is etched.It is aligned with Parylene substrate in IC chip and ties well After conjunction, hole and/or trap serve as the mesh (screen) for this process.Then epoxy resin is pushed through into table using rubber scraper Face so that hole and/or trap in epoxy resin filling Parylene substrate, Parylene substrate and IC chip are electrically connected Connect.
In some examples, the virtual chip with conductive trace is manufactured to simulate actual chips, and Special pad quilt Connection in advance is for connection yield measurement.For example, Fig. 4 A show the virtual chip for assembling yield test.Fig. 4 B are shown Pad can function as alignment mark.Fig. 4 C are shown to be implemented with the metal gasket of about 5 μm of resolution exposure.
The present invention provides use photo-patterned adhesive in film (for example, Parylene is for example poly- to diformazan Benzene C) method and technique of low temperature bond between silicon.This method may be used to determine with reference to pad, and can also reduce Residual stress in packaging.Advantageously, this low temperature bond allows selective local region to combine, without applying high electric field.Cause This, it is particularly suitable for Parylene substrate in being packed in MEMS and the collection of microelectronic component (microelectronics) Into.
In this way, in another embodiment, it is used to integrated circuit being assembled into film-substrate the present invention provides one kind In method.Although Parylene is preferable substrate, it will be appreciated by those skilled in the art that the material can be it His film polymer, such as polyimides, Teflon, kapton or printed circuit board (PCB) (PCB) and the like.This method bag Include：
Photo-patterned adhesive or epoxy resin are spin-coated to integrated circuit (IC) to form the IC of covering；
Shelter the IC of covering；With
The IC of covering is patterned using photoetching process patterned to be formed with multiple combinations pad on exposure I C IC, for being integrated into film (for example, Parylene) substrate.
Under some examples, the present invention provides low temperature bonding process to promote the various portions as biomedical implants The connection of part and packaging.In some examples, combination technology can be used for promoting Parylene-C substrates and IC and discrete Connection between component, the substrate have the electrical connection of pre-metallization.Chip is preferably incorporated in substrate with appropriate alignment On so that the metal gasket on metal gasket and chip on Parylene substrate is in line.
In some examples, commercially available photo-patterned material, such as photo-patterned adhesive can be used Or epoxy resin.In some aspects, photo-patterned material is photoresist.Suitable photoresist include SU-8, AZ4620, AZ1518, AZ4400, AZ9260, THB-126N, WPR-5100, BCB, polyimides and the like.Processing conditions It is facile in terms of combination temperature, combination pressure, binding time and surface treatment.The result shows that for example, it is based on asphalt mixtures modified by epoxy resin The SU-8 of fat is very effective, peeling force up to 6.3N.
In some examples, due to excellent reflux performance, in process using AZ4620 photoresists (P.J.Chen Et al., J.Microelectromech.Syst, 17 (2008), the 1352-1361 pages).The AZ4620 photoresists that will be patterned into Agent continues 10 minutes to 80 minutes in 100 DEG C to about 180 DEG C such as 140 DEG C bakings, such as about 30 minutes in vacuum drying oven, and And it contributes to conductive epoxy resin to refill by the smooth surface formed that flows back, as shown in figures 5 a-d.The length of side is in baking It is preceding and almost identical afterwards so that the photoresist of reflux influences conduction really by covering whole metal gasket Property.In a kind of specific embodiment, it is in no way intended to limit, Fig. 5 A show the AZ4620 not toasted.Fig. 5 B show 140 DEG C The AZ4620 for continuing 30 minutes is toasted in vacuum drying oven.Fig. 5 C and Fig. 5 D are shown is conducive to conduction by the slope formed of flowing back Epoxy resin feedthrough.Advantageously, the length of side does not show change before baking and afterwards.
In pervious application, conductive epoxy resin is crossed the cavity being embedded in Parylene-C substrates by feedthrough, and And dependent on manufacture electrically and mechanically both.As shown in Figure 6A, conductive epoxy resin is used only in the technique of the prior art 615 connect Parylene substrate and chip 602.Metal gasket is shown as 625.In the technique of the present invention, using leading Electric epoxy resin 615 and photo-patterned adhesive (for example, photoresist) 610, such as AZ4620.In fact, inciting somebody to action AZ4620 (herein as glue) applies to chip 602, total cemented surface between Parylene-C substrates and chip 602 Product increases to 94% from 2%, as shown in Figure 6B.In some examples, it is not necessary to pad be also covered with avoid scraper connect Defect appear below at Parylene-C interfaces during termination process.
High density connection between chip and Parylene-C substrates is completed again by conductive epoxy resin scraper, and Customization retainer provides safety buffer zone for scraper, fully to replace the function of PDMS retainers (referring to Jay H.C.Chang, Ray Huang and 1110-1113 pages of Y.C.Tai, Proc.NEMS2011, the).
II. the low temperature bond between Parylene-C and silicon
In some examples, photo-patterned adhesive is spin-coated on clean silicon wafer first, such as using HMDS and oxygen plasma processing, then carry out standard photolithography process to define with reference to pad.In some preferable aspects, the party Method includes toasting patterned IC to form smooth surface.In some other examples, Parylene substrate uses oxygen first Corona treatment is to strengthen and the combination of photo-patterned adhesive.In also other examples, IC chip by HMDS and/or Oxygen plasma processing is to strengthen and the combination of photo-patterned adhesive.
It is conceived to the application of integrated chip, as the illustrative examples of photo-patterned adhesive, selects (13 μm of SU-8 With 28 μm) and AZ4620 (10 μm and 19 μm) as an example, to create the suitable aspect ratio (aspect of cavity or opening ratio).Other photoresists include AZ1518, AZ4400, AZ9260, THB-126N, WPR-5100, BCB, polyimides And the like.
As shown in fig. 7, by the 30 μm of clean Parylene-C films 730 handled by oxygen plasma then with cutting Chip 740 align, and the structure is sandwiched between two glass slides 715,725.Use the folder with two arms 710,720 Have 750 as combination tool to manufacture good contact and apply constant power to test sample.Heating process is in vacuum drying oven Middle operation, and highest test temperature is set as about 120-180 DEG C, e.g., from about 150 DEG C, to prevent the damage to IC chip.
Fig. 8 A and Fig. 8 B show a reality of the cross-section SEM images of the sample by photo-patterned adhesive combination Example.Desired thickness has been defined well with reference to pad, and during combined process, the shape of micro-structure does not change.And And flexible intermediate adhesive will not cause residual stress after the coupling.
In one aspect, this method includes being tied to strengthen to handle Parylene substrate with oxygen plasma processing first Close.This plasma process conditions include e.g., from about 10W to about 100W e.g., from about 50W；100 millitorrs to about 300 millitorrs are for example About 200 millitorrs；With the duration of 0.1 minute to e.g., from about 1 minute about 5 minutes.
In some examples, each in multiple combination pads is between 1 μm and 10 μm.In some examples, with reference to Pad can be individually different sizes.The thickness of photo-patterned adhesive in IC chip be from 10 μm to 30 μm for example 10μm、11μm、12μm、13μm、14μm、15μm、16μm、17μm、18μm、19μm、20μm、21μm、22μm、23μm、24μm、25 μm, 26 μm, 27 μm, 28 μm, 29 μm or 30 μm.In some examples, patterning is assembled using conductive epoxy resin or paste IC and Parylene substrate.This method is highly dense to manufacture including transmitting conductive epoxy resin by high throughput technique Spend the connection of multichannel IC chip.In some examples, high-density multi-channel IC chip is in 25mm2It is more than 1000 on chip area Passage or even in 36mm2On 10,000 passages or about 5-300 passage per mm2Chip area.
In some aspects, when IC chip has greater than about 200 μm of spacing dimension, apply conductive epoxy resin and use tool The pin for having the diameter less than 100 μm carries out.As explained above, the process for forming patterned IC chip on the ic chip is fixed Completed on coremaking piece pattern mold.Mould serves as the safety buffer zone for doctor blade process.The size and depth of mould are set It is calculated as adapting to the size of chip.
As shown in Figure 9 A, peeling force is measured to study bond strength by Ergometer arrangement.Fig. 9 B, which are shown, to be combined Test sample afterwards；Fig. 9 C show the schematic diagram of test sample.
Each data point represents the average value of five measurement results.Dynamometer is fixed in motorized stage, so that with 100 μ The speed of m/s is by the film being partially stripped with 90 degree of pull-outs.As combination temperature function peeling force figure 10 illustrates.
Figure 11 shows the peeling force of the function as combination pressure.After an analysis, the results showed that combination temperature and knot Resultant pressure is higher, with reference to stronger.
Advantageously, the Parylene-C films handled by oxygen plasma are significantly enhanced for photo-patterned Adhesive such as photoresist (for example, SU-8) combination (referring to, Blanco F J et al., J.Micromech.Microeng.14(2004),1047-1056).Even if the combination pressure of the 2MPa of maximum combined is formed wherein Under power, SU-8 micro-structures will not deform.Figure 12 A show the maximum peeling force of different photo-patterned adhesives.Figure 12B shows the peeling force for different photo-patterned adhesives relative to binding time.Z4620 can be born up to The pressure of 0.5MPa.In some aspects, when sample heats more than one hour, binding time is to bond strength almost without shadow Ring.
As demonstration, which is applied to what is integrated with being used for the Parylene-C operation devices of retinal implant 268- channel conductances chip (Figure 13).After by the pattern of adhesive on chip (referring to, J.H.Chang et al., Proc.MEMS 2012, the 353-356 pages), the spatial resolution padded by the combination of SU-8 structures can be 5 μm.Faying face Product increases to 94% from 2%, and the connection yield measured brings up to 98% from 92%.
The combined process of this low cost and low temperature is proved to be able to the sealing for realizing MEMS structure.
In another embodiment, the present invention provides a kind of non-biocompatible thin film's substrate.Although Parylene It is preferable substrate, but it will be appreciated by those skilled in the art that the material can be other film polymers, such as polyamides is sub- Amine, Teflon, kapton or printed circuit board (PCB) (PCB) and the like.The present invention provides a kind of for the thin of attachment arrangement Film (for example, Parylene) substrate, including：
The first film (for example, Parylene) layer；
Metal, it is adjacent to the first film (for example, Parylene) layer；
Second film (for example, Parylene) layer, it is adjacent to the metal to form film metal film (for example, poly- Paraxylene-metal-Parylene) interlayer, wherein the second parylene layer has opening or cavity, which, which has, sets Put at least one electric contact on its inner surface, the opening be configured to receive at least one circuit device and this at least one Electrical communication is provided between a electric contact and at least one circuit device, the non-biocompatible thin film is (for example, poly- to diformazan Benzene) substrate is configured to be implanted in living organism after at least one circuit device is received.
In certain aspects, the device with least one circuit is integrated circuit (IC) chip.In addition, device such as IC Chip is electrically connected by conductive epoxy resin scraper and is integrated in the substrate.Preferably, device can by be used as machinery glue The adhesive of photo-patterning is integrated into substrate.In one embodiment, total is (for example, have at least one electricity The device on road is integrated circuit (IC) chip) conformally coated and close with Parylene-C (poly- p-xylene-C) Envelope, and if desired, sealed with medical grade epoxy to realize for the fully enclosed of biocompatibility.
In some examples, once device is implanted, it is possible to communicates with the device and external device (ED) of implantation.Communication Percutaneous connector or wireless communications method can be used to carry out.The kind of the signal to communicate between the device and external device (ED) of implantation Some in class include power signal and data-signal.The device that power signal can include from external power supply to implantation provides work( The signal of rate so that the battery being present in the device of implantation may remain in suitable charged state, or make it that battery can To be eliminated from the device of implantation.For some conventional equipments with battery, operation may become desirable for more changing device, because Its battery is expected to the terminal for reaching its service life.Any operation can all cause health risk, and if possible, preferably keep away Exempt from unnecessary operation, particularly in the crowd of unsoundness problem.Therefore, because battery is without the implantable of replacement Device is favourable.
Data-signal can include the data-signal of the device from external detector to implantation (for example, will correspond to by wheat The electric signal for the earcon that gram wind receives is supplied to cochlear implant, for the nervous system communication by people to the big of people Brain)；The control signal of device from external detector to implantation, the control signal are provided and controlled by using such signal Make the ability (for example, the mode of operation of the device of control implantation is to meet Man's Demands) of the device of implantation；And from implantation Device to the data-signal of external device (ED) to monitor the situation of the device of implantation itself and operation, with monitor the situation of people (such as Pulse frequency, heart signal or with other relevant signals of situation being treated) and implantation device near situation (such as Physiological signal, such as temperature, pressure, pH), or the signal given people is applied with the device of monitoring implantation.In some embodiments, Data-signal can be used for the device " adjustment " of implantation or " reprograming ", to be done using due to the situation of people and people In advance, the improvement for the understanding for helping or treating, or provide and the implantable device developed after implanted device is operated and controlled Program or the improvement for operating software.
Other integrated circuit in packaging or module can be arranged in a wide variety of ways, and can be placed on bag Other positions in dress.For example, different integrated circuits can be positioned in the layer of different Photoimageables and/or by It is positioned in same layer.In various embodiments, integrated circuit can be stacked, positioned side by side, and come in close proximity to each other placement And/or it is separated by a significant distance relative to the overall dimensions of packaging.Integrated circuit can also have a variety of different forms Factor, architecture and configuration.For example, they can take the form of relatively exposed bare chip (for example, unpacked naked core Piece, flip-chip etc.) or the bare chip partially and/or fully packed.
III.Device to test
The failtests of the electrical connection of test specification test Parylene substrate is operated below.
Figure 14 shows the setting (setup) 1400 for testing measurement.As shown therein, detection electrode array exports 1410th, 1415 it is electrically connected with checking.In certain aspects, these electrodes are placed on the Huang of the mammal eyes of such as human eye On spot.
Setting 1400 includes patterned chip 1428 and Parylene interface 1433.Photoresist 1420 is sandwiched in Between chip 1428 and Parylene 1430.In addition, between chip 1428 and photoresist 1420 or in conducting ring Include metal 1425 between oxygen tree fat 1418 and chip.Conductive via is provided to be electrically connected the portion at the different layers for residing in packaging Part (for example, IC/ traces/contact/passive component etc.).Via, which is arranged to, extends through each layer.For example, via can be with For the trace from two different interconnection layers to be coupled together；Tube core (die) or another component are coupled to interconnection layer； Contact is coupled to trace, tube core or miscellaneous part etc..
In an experiment, detected by using stimulating electrode 1440 and 1441 good to measure connection just after scraper Rate.Afterwards, other thick Parylene-C is coated in whole device (in addition to output electrode) so that connection insulation and Stablize, and to protect the metal in embedded Parylene-C substrates from the influence of corrosive body fluids.After the coating Record connection yield.Finally, device is soaked in 90 DEG C of saline solution and continues 5 days, and record connection yield again.
Result in Figure 15 shows the operation yield of the device of the invention under four kinds of different conditions.After scraper connection Carry out reliability test；Soaked in the case where not encapsulating；Encapsulated by Parylene-C coatings；And in 90 DEG C of brine Middle Accelerating immersion.The result shows that provided really with the technique that the thick Parylene-C coatings for packaging are combined high Connect yield.
The result shows that new bonding technique is gratifying (~98%), and it is good in the case of no new technology Rate is significantly lower (~88%).Moreover, for the connection in the case of no photoresist bonding technique, it is most of to disconnect Occur wherein to apply on the perimetral gasket of stratification forces.
In addition, it have studied the limitation at the interval between pad size and pad.With different pad intervals and size Chip is designed and manufactured to be used to measure.
Figure 16 A show the pad size with 40 μm of 40 μ m and the chips at 40 μm of intervals.Figure 16 B show poly- to two Connection between toluene substrate and chip.Figure 16 C show interval of the yield relative to pad.Figure 16 D show that yield is opposite In the length of side of pad.The result shows that the pads for as low as 40 μm of 40 μ m and therebetween with 40 μm of intervals, it is possible to achieve High connection yield (>90%).
It is current based on these as a result, realize up to 10 in the area of 6mm × 6mm, 000 connection.This is to current Retina prosthese application is gratifying.
It is some in terms of other in, packing technique is designed to the device that there is low-density to connect.Therefore, another In kind embodiment, the present invention provides：
A kind of biocompatibility packaging for low-density connection, including：
Feedthrough layer；
In the application-specific integrated circuit (ASIC) of the feedthrough layer downwardly over；
The printed circuit board (PCB) (PCB) of ASIC is attached to, the printed circuit board (PCB) is suitable for off-chip components and conducting wire combines To feedthrough layer；
The metallic walls of neighbouring feedthrough layer；And metal cover, the metal cover are used to encasing and manufacturing biocompatibility packaging.
Figure 17 shows a kind of embodiment of low-density packing technique.As shown therein, 1735 placed face downs of ASIC With by flip-chip bonding technique and feedthrough layer 1745 (for example, being made of ceramics or other biological compatibility material) be connected with Manufacture is electrically connected.Off-chip components 1715 are connected to PCB 1720 to manufacture by welding or by using conductive epoxy resin It is electrically connected.Then, the back side that PCB 1720 is attached to ASIC 1735 by non-conductive epoxy is mechanically connected with manufacturing, And conducting wire is combined 1725 to be electrically connected to manufacture to feedthrough layer 1745 (for example, ceramics).Soldered ball 1740 is used by upside-down mounting Chip is incorporated in manufacture between ASIC 1735 and feedthrough layer 1745 and is electrically connected.
Then metallic walls 1730a, 1730b are hermetically encased with metal cover 1710 by using laser welding technology.Such as Shown in it, packaging there are at least two metallic walls 1730a, 1730b, its for example, by soldering tech with feedthrough 1745 hermetically Encase.
Unique packing technique employs all ripe connections and encases technology (purpose is to minimize risk), including Flip-chip combination, conducting wire combination, soldering or laser welding.Advantageously, its implanted device for being designed to that there is circuit To survive in corrosive body fluids.Should be designed for 1-100 connection, such as the pact in small nanometer area or millimeter area 1-50,1-40,1-30,1-20,1-10.This should be used to say that satisfactorily current retina prosthese.
Feedthrough layer 1745 serves as the interface between closed circuit and flexible electrode array.Signal can be sent to electricity from circuit Pole array, and circuit still can be protected well.Ceramic feedthrough includes the via made of biocompatibility metal, and And the layout of via can be designed according to ASIC and miscellaneous part.First by soldering tech by biocompatibility metal wall with Feedthrough layer is encased to form soldered fitting together.Then ASIC placed face downs are attached to ceramic substrate with flip-chip.Its His off-chip components 1715 can also be soldered or flip-chip is attached to ceramic substrate.Selectively, ASIC and chip exterior Part may remain on same plane and will take more areas.
Another preferable option is that off-chip components are attached to by solder (solder) or conductive epoxy resin first PCB.It is then possible to PCB is attached on the top (back side) of ASIC by non-conductive epoxy or any glue.Afterwards, may be used Complete circuit is formed to manufacture extra conducting wire combination connection from PCB to ceramic feedthrough.In this case (such as Figure 17 institutes Show), ASIC and off-chip components are located in different planes to save surface area.Advantageously, design has low profile and small table The closed circuit box of area.Final step is hermetically to surround metallic walls 1730 with metal cover 1710 by laser welding.Herein Before, carry out vacuum bakeout processing and help seal process to remove moisture or other impurities.
It should be appreciated that example described herein and embodiment being merely to illustrate property purpose, and for this area skill Art personnel will suggest the various modifications to it and change, and these modifications and changes will be included in spirit herein and power Within limit and scope of the following claims.For all purposes, all publications, patent and patent cited herein Application is hereby incorporated by reference in its entirety accordingly by reference.

Claims (14)

1. a kind of biocompatibility packaging for low-density connection, the biocompatibility includes：
Feedthrough layer；
In the application-specific integrated circuit (ASIC) of the feedthrough layer downwardly over；
The printed circuit board (PCB) (PCB) of the ASIC is attached to, the printed circuit board (PCB) is suitable for off-chip components and conducting wire combines To the feedthrough layer；
The metallic walls of the neighbouring feedthrough layer；And metal cover, the metal cover are used to encasing and manufacturing the biocompatibility bag Dress.
2. biocompatibility packaging as claimed in claim 1, wherein the feedthrough layer is biocompatible materials.
3. biocompatibility packaging as claimed in claim 2, wherein the biocompatible materials is ceramics.
4. biocompatibility packaging as claimed in claim 1, wherein off-chip components are by welding or by using conducting ring Oxygen tree fat is connected to the PCB.
5. biocompatibility packaging as claimed in claim 1, wherein the PCB is attached to institute by non-conductive epoxy State the back side of ASIC.
6. biocompatibility packaging as claimed in claim 1, wherein the PCB is bound to the feedthrough layer to manufacture by conducting wire It is electrically connected.
7. biocompatibility packaging as claimed in claim 1, wherein soldered ball is used in the ASIC and the feedthrough layer Between manufacture be electrically connected.
8. biocompatibility packaging as claimed in claim 1, wherein the metallic walls are hermetically encased with metal cover.
9. biocompatibility packaging as claimed in claim 1, wherein the packaging is designed to low-density connection.
10. biocompatibility packaging as claimed in claim 1, wherein described be packaged in millimeter area has about 1 to about 100 connections.
11. biocompatibility packaging as claimed in claim 1, wherein the feedthrough layer serves as the closed circuit and flexible electrical Interface between the array of pole.
12. biocompatibility packaging as claimed in claim 4, wherein ASIC and off-chip components are on a different plane.
13. biocompatibility packaging as claimed in claim 4, wherein ASIC and off-chip components are at grade.
14. biocompatibility as claimed in claim 1 packaging, wherein the metal cover and the metallic walls be hermetically laser welded with Hermetically seal.
CN201680049872.4A 2015-08-28 2016-08-26 Implanted device and its manufacture method Pending CN108024851A (en)

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US14/838,788 US10008443B2 (en) 2012-04-30 2015-08-28 Implant device
US14/838,788 2015-08-28
PCT/US2016/049034 WO2017040302A1 (en) 2015-08-28 2016-08-26 Implant device and method of making the same

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112869747A (en) * 2019-11-29 2021-06-01 清华大学 Microelectrode, manufacturing method and using method thereof, plug device and microelectrode system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111588985B (en) * 2020-05-27 2021-02-19 微智医疗器械有限公司 Implant device and method of assembling the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1461227A (en) * 2000-11-16 2003-12-10 波利瓦洛尔公司 Body electronic implant and artificial vision system thereof
CN1961850A (en) * 2006-12-07 2007-05-16 上海交通大学 Implantable vision prosthesis
US20140039588A1 (en) * 2006-08-18 2014-02-06 Second Sight Medical Products, Inc. Package for an Implantable Neural Stimulation Device
CN104271165A (en) * 2012-04-30 2015-01-07 加州理工学院 High-lead count implant device and method of making the same
US20150036302A1 (en) * 2013-08-05 2015-02-05 California Institute Of Technology Long-term packaging for the protection of implant electronics

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5178957A (en) * 1989-05-02 1993-01-12 Minnesota Mining And Manufacturing Company Noble metal-polymer composites and flexible thin-film conductors prepared therefrom
US7211884B1 (en) * 2002-01-28 2007-05-01 Pacesetter, Inc. Implantable medical device construction using a flexible substrate
US7142909B2 (en) * 2002-04-11 2006-11-28 Second Sight Medical Products, Inc. Biocompatible bonding method and electronics package suitable for implantation
US6667215B2 (en) * 2002-05-02 2003-12-23 3M Innovative Properties Method of making transistors
WO2009018172A2 (en) * 2007-07-27 2009-02-05 Second Sight Medical Products Implantable device for the brain

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1461227A (en) * 2000-11-16 2003-12-10 波利瓦洛尔公司 Body electronic implant and artificial vision system thereof
US20140039588A1 (en) * 2006-08-18 2014-02-06 Second Sight Medical Products, Inc. Package for an Implantable Neural Stimulation Device
CN1961850A (en) * 2006-12-07 2007-05-16 上海交通大学 Implantable vision prosthesis
CN104271165A (en) * 2012-04-30 2015-01-07 加州理工学院 High-lead count implant device and method of making the same
US20150036302A1 (en) * 2013-08-05 2015-02-05 California Institute Of Technology Long-term packaging for the protection of implant electronics

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112869747A (en) * 2019-11-29 2021-06-01 清华大学 Microelectrode, manufacturing method and using method thereof, plug device and microelectrode system

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Application publication date: 20180511

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