CN108022625A - MTP storage arrays - Google Patents

MTP storage arrays Download PDF

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Publication number
CN108022625A
CN108022625A CN201610942102.4A CN201610942102A CN108022625A CN 108022625 A CN108022625 A CN 108022625A CN 201610942102 A CN201610942102 A CN 201610942102A CN 108022625 A CN108022625 A CN 108022625A
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CN
China
Prior art keywords
bit line
source line
source
circuit
difference channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610942102.4A
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Chinese (zh)
Inventor
權彞振
倪昊
周耀
王韬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201610942102.4A priority Critical patent/CN108022625A/en
Publication of CN108022625A publication Critical patent/CN108022625A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits

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  • Semiconductor Memories (AREA)

Abstract

MTP storage arrays, the MTP storage arrays include：Multiple storage units, bit line difference channel, source line difference channel, bit line current detection circuit and source line differential switch circuit；The bit line of each storage unit is coupled by corresponding bit line drive circuit and the bit line current detection circuit and the bit line difference channel respectively, and source line is coupled by the source line differential switch circuit and source line difference channel；The bit line current detection circuit, suitable for being detected to the electric current that source line direction is flowed to from bit line；The source line differential switch circuit, suitable for when determining that flowing to the electric current in source line direction from bit line is greater than or equal to default threshold value, voltage input line is disconnected with source line difference channel；When determining that flowing to the electric current in source line direction from bit line is less than the threshold value, voltage input line is turned on source line difference channel.Above-mentioned scheme, can improve MTP storage array operational reliabilitys.

Description

MTP storage arrays
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of MTP storage arrays.
Background technology
Storage array, is made of substantial amounts of storage unit, and each storage unit can store the two-value data 0 or 1 of 1.It is logical Often, the storage unit in storage array is arranged in the matrix form of N*M, the array for forming multiple disks is that is to say, as list One disk uses.
Wherein, multiple programmable (Multi Time Programmable, MTP) storage array is one in storage array Kind, it is a kind of new memory.Compared with other nonvolatile memories, MTP storage arrays have and unique work Mechanism.
But operationally there is the problem of poor reliability for existing MTP storage arrays.
The content of the invention
Technical problems to be solved of the embodiment of the present invention are how to improve MTP storage array reliabilities of operation.
To solve the above-mentioned problems, the embodiment of the present invention provides a kind of MTP storage arrays, and the MTP storage arrays include： Multiple storage units, bit line difference channel, source line difference channel, bit line current detection circuit and source line differential switch circuit；Respectively The bit line of a storage unit passes through corresponding bit line drive circuit and the bit line current detection circuit and institute's rheme respectively Line difference channel couples, and source line is coupled by the source line differential switch circuit and source line difference channel；The bit line current inspection Slowdown monitoring circuit, suitable for being detected to the electric current that source line direction is flowed to from bit line；The source line differential switch circuit, suitable for when definite When flowing to the electric current in source line direction from bit line and being greater than or equal to default threshold value, voltage input line is disconnected with source line difference channel to be connected Connect；When determining that flowing to the electric current in source line direction from bit line is less than the threshold value, voltage input line is turned on source line difference channel.
Alternatively, the bit line current detection circuit includes phase inverter, the first current mirroring circuit and the second current mirroring circuit； The input terminal of first current mirroring circuit is coupled by corresponding bit line drive circuit and bit line, output terminal and the phase inverter Input terminal coupling；The input terminal of second current mirroring circuit is coupled with default reference current, output terminal with it is described anti-phase The input terminal coupling of device；The output terminal of the phase inverter is coupled with the source line differential switch circuit.
Alternatively, first current mirroring circuit includes the first PMOS tube and the second PMOS tube；First PMOS tube The source of source and second PMOS tube couples；The drain terminal of first PMOS tube is defeated as first current mirroring circuit Outlet；The grid end of first PMOS tube and the grid end and drain terminal of second PMOS tube couple, as first current mirror The input terminal of circuit.
Alternatively, second current mirroring circuit includes the first NMOS tube and the second NMOS tube；First NMOS tube Drain terminal and grid end are coupled with the grid end of second NMOS tube and the reference current, as the defeated of second current mirroring circuit Enter end；The source of second NMOS tube and the source of first NMOS tube couple；The drain terminal conduct of second NMOS tube The output terminal of second current mirroring circuit.
Alternatively, the bit line current detection circuit includes first resistor, second resistance and comparator；The first resistor First end and the bit line difference channel couple, and coupled by corresponding bit line drive circuit with corresponding bit line；It is described The second end of first resistor is coupled with the first end of the second resistance and the reverse input end of the comparator, second electricity The second end of resistance is coupled with ground wire；The positive input of the comparator and default reference voltage couple, output terminal with it is described The input terminal coupling of source line differential switch circuit.
Alternatively, the source line differential switch circuit includes level shifting circuit, the 3rd NMOS tube；The level conversion electricity The input terminal on road and the output terminal of the bit line current detection circuit couple, output terminal and the grid end coupling of the 3rd NMOS tube Connect；The drain terminal of 3rd NMOS tube is coupled with the source line difference channel, the 3rd NMOS tube source and the source line coupling Connect；The level shifting circuit is also coupled with the source line difference channel.
Alternatively, the source of the 3rd NMOS tube is also coupled by 3rd resistor and ground wire.
Alternatively, the MTP storage arrays are p-type MTP storage arrays.
Compared with prior art, technical scheme has the advantages that：
Above-mentioned scheme, by when MTP storage arrays are run, using bit line current detection circuit to flowing to source from bit line The electric current in line direction is detected so that source line differential switch circuit determine from bit line flow to source line direction electric current be more than or When person is equal to default threshold value, voltage input line is disconnected with source line difference channel, and the larger electricity of source line can be flowed to avoid bit line Flow the influence to the target voltage of source line difference channel so that source line difference channel can stably export corresponding target electricity Pressure, so as to meet the operation demand of MTP storage arrays, improves MTP storage array reliabilities of operation.
Brief description of the drawings
Fig. 1 is a kind of structure diagram of MTP storage arrays in the embodiment of the present invention；
Fig. 2 is a kind of structure of bit line current detection circuit in the embodiment of the present invention；
Fig. 3 is the structure of another bit line current detection circuit in the embodiment of the present invention；
Fig. 4 is the structure of the introduces a collection line differential switch circuit in the embodiment of the present invention.
Embodiment
As it was previously stated, p-type MTP storage arrays are in a short-circuit situation, there is the electric current that source line direction is flowed to from bit line.When When the electric current is larger, the target voltage of source line difference channel can be impacted, have impact on p-type MTP storage arrays work can By property.
To solve the above problems, the technical solution of the embodiment of the present invention is by when MTP storage arrays are run, using bit line Current detection circuit is detected the electric current that source line direction is flowed to from bit line so that source line differential switch circuit is being determined from position When the electric current that line flows to source line direction is more than or equal to default threshold value, voltage input line is disconnected with source line difference channel, can be with Bit line is avoided to flow to the influence of the larger electric current of source line to the target voltage of source line difference channel so that source line difference channel can Stably to export corresponding target voltage, so as to meet the operation demand of MTP storage arrays, MTP storage arrays are improved Reliability of operation.
It is understandable to enable above-mentioned purpose, feature and the beneficial effect of the present invention to become apparent, below in conjunction with the accompanying drawings to this The specific embodiment of invention is described in detail.
Fig. 1 shows a kind of structure diagram of MTP storage arrays in the embodiment of the present invention.It is as shown in Figure 1, of the invention MTP storage arrays in embodiment, can include：Multiple storage units 101, bit line difference channel 102, source line difference channel 103rd, bit line current detection circuit 104 and source line differential switch circuit 105.
Wherein, the bit line BL of each storage unit 101 passes through corresponding bit line drive circuit 106 and bit line electricity respectively Current detection circuit 104 and bit line difference channel 102 couple, and the source line of each storage unit 101 passes through source line differential switch Circuit 105 is coupled with source line difference channel 103.
In an embodiment of the present invention, the MTP storage arrays are p-type MTP storage arrays.It is understood that having During body is implemented, as needed for N-type MTP storage arrays, when there is the problem of same or like, it can also use similar Mode solved, the present invention details are not described herein.
In specific implementation, the p-type MTP storage arrays in the embodiment of the present invention at work, bit line current detection circuit 104 pairs of electric currents that source line SL directions are flowed to from bit line BL are detected；When definite source line is flowed to from the bit line BL of storage unit 101 Relation between the electric current of SL and default threshold value, exports corresponding signal DET.
With reference to Fig. 1, bit line current detection circuit 104 is in the definite electricity that source line SL is flowed to from the bit line BL of storage unit 101 When stream is greater than or equal to default threshold value with default threshold value, it is high level to export signal DET, voltage input line differential switch circuit 105 close, so that source line SL is disconnected with source line difference channel 103；When the definite bit line BL from storage unit 101 flows When being less than default threshold value to the electric current of source line SL, output signal DET is low level, and voltage input line differential switch circuit 105 is opened Open, so that source line SL is turned on source line difference channel 103.
Adopt in manner just described, source line SL's is flowed to the bit line BL of storage unit 101 by bit line current detection circuit Electric current is detected, and when the electric current for determining to detect is greater than or equal to default threshold value, by source line and source line difference channel 103 disconnect, so that the electric current that bit line BL flows to source line SL will not be to the target operating voltage of source line difference channel 103 Impact, the reliability of the work of source line difference channel 103 can be improved, and then the property of p-type MTP storage arrays can be improved Energy.
Below by the circuit structure of the bit line current detection circuit in the embodiment of the present invention and source line differential switch circuit It is further described in detail with principle.
Fig. 2 shows a kind of structure of bit line sensing circuit in the embodiment of the present invention.Referring to Fig. 2, the embodiment of the present invention In a kind of bit line sensing circuit include phase inverter 201, the first current mirroring circuit 202 and the second current mirroring circuit 203.
Wherein, the input terminal of the first current mirroring circuit 202 is coupled by corresponding bit line drive circuit and bit line, the first electricity The output terminal of current mirror circuit 202 is coupled with the input terminal of phase inverter 201.The input terminal of second current mirroring circuit 203 is pre- with output If the current source 204 of reference current I couple, the output terminal of the second current mirroring circuit 203 and the input terminal coupling of phase inverter 201 Connect, output terminal and the source line differential switch circuit of phase inverter 201 couple.
In an embodiment of the present invention, the first current mirroring circuit 202 includes the first PMOS tube PM1 and the second PMOS tube PM2. Wherein, the source of the first PMOS tube PM1 and the source of the second PMOS tube PM2 are coupled with bit line difference channel 205, the first PMOS Output terminal of the drain terminal of pipe PM1 as the first current mirroring circuit 201, the grid end of the first PMOS tube PM1 is with the second PMOS tube PM2's Grid end and drain terminal coupling, the input terminal as the first current mirroring circuit 201.
In an embodiment of the present invention, the second current mirroring circuit 203 includes the first NMOS tube NM1 and the second NMOS tube NM2. Wherein, the drain terminal of the first NMOS tube NM1 and grid end and the grid end of the second NMOS tube NM2 and the constant-current source 204 of output reference current I Coupling, the input terminal as the second current mirroring circuit 202；The source of the source of second NMOS tube NM2 and the first NMOS tube NM1 with Ground wire VSS is coupled；Output terminal of the drain terminal of second NMOS tube NM2 as second current mirroring circuit 202.
In specific implementation, when p-type MTP storage arrays work, the reference current I that constant-current source 204 exports is by the second electricity After current mirror circuit 202 is changed, corresponding electric current is exported in the source of the second NMOS tube NM2, which passes through first with electric current IBL Current mirroring circuit 201 change after the first PMOS tube PM1 source export current direction on the contrary, absolute value between the two is determined The numerical value of voltage Vdet is determined, so as to determine that the signal DET of the output terminal output of phase inverter 201 is high level signal or low Level signal.Specifically, it is anti-phase when the voltage Vdet of the input terminal of phase inverter 201 is more than the turnover voltage of phase inverter 201 The output terminal of device 201 exports corresponding high level signal；Conversely, the output terminal of phase inverter 201 then exports corresponding low level letter Number.
Fig. 3 shows the structure of another bit line current detection circuit in the embodiment of the present invention.Referring to Fig. 3, the present invention Another bit line circuit detection circuit in embodiment includes first resistor R1, second resistance R2 and comparator 301.Wherein, The first end of one resistance R1 is coupled with bit line difference channel 302, and passes through corresponding bit line drive circuit and corresponding bit line coupling Connect；The second end of first resistor R1 is coupled with the reverse input end of the first end of second resistance R2 and comparator 301, second resistance The second end of R2 is coupled with ground wire VSS；The positive input of comparator 301 is coupled with default reference voltage VREF, comparator The input terminal of the signal input sources line differential switch circuit of 301 output terminal output.
In specific implementation, the target voltage of bit line difference channel 302 carries out partial pressure by resistance R1 and resistance R2 so that The voltage at R2 both ends is compared by the reverse input end input comparator of comparator with the reference voltage VREF of positive input Compared with.
Wherein, the ratio between resistance R1 and resistance R2, the target voltage with bit line difference channel, and reference voltage The numerical value of VREF is related.For example, when the target voltage of bit line difference channel is 4V, the ratio between resistance value between R1 and R2 is arranged to 1：3.At this time, the voltage at R2 both ends is 1V, equal with the magnitude of voltage of reference voltage VREF.When electric current IBL is more than default electric current During threshold value so that the voltage rise at resistance R2 both ends, namely higher than reference voltage VREF so that comparator 301 exports low level Signal, so that voltage input line differential switch circuit disconnects, the connecting path between source line and source line difference channel is disconnected, to keep away Exempt from influence of the larger electric current to the target voltage of source line difference channel.
Fig. 4 shows the structure of the introduces a collection line differential switch circuit in the embodiment of the present invention.It is real referring to Fig. 4, the present invention The one kind applied in example includes 401 and the 3rd NMOS tube NM3 of level shifting circuit.
Wherein, the power input of level shifting circuit 401 is coupled with default power vd D, level shifting circuit 401 Signal input part and the output terminal of bit line current detection circuit couple；The signal output part of level shifting circuit 401 and the 3rd The grid end coupling of NMOS tube NM3；The drain terminal of 3rd NMOS tube NM3 is coupled with source line difference channel 402, the 3rd NMOS tube NM3's The source line SL of source and the storage unit in MTP storage arrays is coupled；Level shifting circuit 401 also with the source line difference channel 402 couplings.
In an embodiment of the present invention, the source of the 3rd NMOS tube NM3 is also coupled by 3rd resistor R3 and ground wire VSS, To realize the purpose of current stabilization.
In specific implementation, level shifting circuit 401 is determined according to the level signal DET that bit line current detection circuit inputs When bit line current is greater than or equal to default threshold value, corresponding low level signal is exported so that the 3rd NMOS tube NM3 is turned off, from And source line SL and source line difference channel are disconnected；Inputted when level shifting circuit 401 according to bit line current detection circuit When level signal determines that bit line current is less than default threshold value, corresponding high level signal is exported, the 3rd NMOS tube NM3 of control is beaten Open, so that source line SL be turned on source line difference channel.
Using the such scheme in the embodiment of the present invention, when MTP storage arrays are run, pass through bit line current detection circuit The electric current that source line direction is flowed to from bit line is detected so that source line differential switch circuit is determining to flow to source line side from bit line To electric current be more than or equal to default threshold value when, voltage input line is disconnected with source line difference channel, can be flowed to avoid bit line Influence of the larger electric current of source line to the target voltage of source line difference channel so that source line difference channel can be exported stably Corresponding target voltage, so as to meet the operation demand of MTP storage arrays, improves MTP storage array reliabilities of operation.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the scope of restriction.

Claims (8)

  1. A kind of 1. MTP storage arrays, it is characterised in that including：Multiple storage units, bit line difference channel, source line difference channel, Bit line current detection circuit and source line differential switch circuit；
    The bit line of each storage unit respectively by corresponding bit line drive circuit and the bit line current detection circuit and The bit line difference channel coupling, source line are coupled by the source line differential switch circuit and source line difference channel；
    The bit line current detection circuit, suitable for being detected to the electric current that source line direction is flowed to from bit line；
    The source line differential switch circuit, suitable for being greater than or equal to default threshold when the electric current for determining to flow to source line direction from bit line During value, voltage input line is disconnected with source line difference channel；When the electric current for determining to flow to source line direction from bit line is less than the threshold During value, voltage input line is turned on source line difference channel.
  2. 2. MTP storage arrays according to claim 1, it is characterised in that the bit line current detection circuit includes anti-phase Device, the first current mirroring circuit and the second current mirroring circuit；
    The input terminal of first current mirroring circuit is coupled by corresponding bit line drive circuit and bit line, output terminal with it is described anti- The input terminal coupling of phase device；
    The input terminal of second current mirroring circuit is coupled with default reference current, the input terminal of output terminal and the phase inverter Coupling；
    The output terminal of the phase inverter is coupled with the source line differential switch circuit.
  3. 3. MTP storage arrays according to claim 2, it is characterised in that first current mirroring circuit includes first PMOS tube and the second PMOS tube；
    The source of first PMOS tube and the source of second PMOS tube couple；Described first
    Output terminal of the drain terminal of PMOS tube as first current mirroring circuit；The grid end of first PMOS tube and described second Grid end and the drain terminal coupling of PMOS tube, the input terminal as first current mirroring circuit.
  4. 4. MTP storage arrays according to claim 2, it is characterised in that second current mirroring circuit includes first NMOS tube and the second NMOS tube；
    The drain terminal and grid end of first NMOS tube are coupled with the grid end of second NMOS tube and the reference current, as institute State the input terminal of the second current mirroring circuit；
    The drain terminal of second NMOS tube and the source of first NMOS tube couple；Described second
    Output terminal of the source of NMOS tube as second current mirroring circuit.
  5. 5. MTP storage arrays according to claim 1, it is characterised in that the bit line current detection circuit includes first Resistance, second resistance and comparator；
    The first end of the first resistor and the bit line difference channel couple, and by corresponding bit line drive circuit with it is corresponding Bit line coupling；The second end of the first resistor and the first end of the second resistance and the reverse input end of the comparator Coupling, second end and the ground wire of the second resistance couple；
    The positive input of the comparator is coupled with default reference voltage, output terminal and the source line differential switch circuit Input terminal couples.
  6. 6. MTP storage arrays according to claim 1, it is characterised in that the source line differential switch circuit includes level Conversion circuit, the 3rd NMOS tube；
    The output terminal of the input terminal of the level shifting circuit and the bit line current detection circuit couples, output terminal and described the The grid end coupling of three NMOS tubes；
    The drain terminal of 3rd NMOS tube is coupled with the source line difference channel, the 3rd NMOS tube source and the source line coupling Connect；
    The level shifting circuit is also coupled with the source line difference channel.
  7. 7. MTP storage arrays according to claim 6, it is characterised in that the source of the 3rd NMOS tube also passes through Three resistance are coupled with ground wire.
  8. 8. according to claim 1-7 any one of them storage arrays, it is characterised in that the MTP storage arrays are p-type MTP Storage array.
CN201610942102.4A 2016-11-01 2016-11-01 MTP storage arrays Pending CN108022625A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610942102.4A CN108022625A (en) 2016-11-01 2016-11-01 MTP storage arrays

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610942102.4A CN108022625A (en) 2016-11-01 2016-11-01 MTP storage arrays

Publications (1)

Publication Number Publication Date
CN108022625A true CN108022625A (en) 2018-05-11

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610942102.4A Pending CN108022625A (en) 2016-11-01 2016-11-01 MTP storage arrays

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020110020A1 (en) * 1999-12-27 2002-08-15 Winbond Electronics Corporation Method for improved programming efficiency in flash memory cells
CN103730160A (en) * 2014-01-07 2014-04-16 上海华虹宏力半导体制造有限公司 Memory and reading method and reading circuit thereof
US20140293684A1 (en) * 2013-04-01 2014-10-02 SK Hynix Inc. Nonvolatile memory apparatus
US9401213B1 (en) * 2015-11-15 2016-07-26 Winbond Electronics Corp. Non-volatile memory apparatus and operation method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020110020A1 (en) * 1999-12-27 2002-08-15 Winbond Electronics Corporation Method for improved programming efficiency in flash memory cells
US20140293684A1 (en) * 2013-04-01 2014-10-02 SK Hynix Inc. Nonvolatile memory apparatus
CN103730160A (en) * 2014-01-07 2014-04-16 上海华虹宏力半导体制造有限公司 Memory and reading method and reading circuit thereof
US9401213B1 (en) * 2015-11-15 2016-07-26 Winbond Electronics Corp. Non-volatile memory apparatus and operation method thereof

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Application publication date: 20180511

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