CN108021724A - The wiring method of standard block - Google Patents

The wiring method of standard block Download PDF

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Publication number
CN108021724A
CN108021724A CN201610958606.5A CN201610958606A CN108021724A CN 108021724 A CN108021724 A CN 108021724A CN 201610958606 A CN201610958606 A CN 201610958606A CN 108021724 A CN108021724 A CN 108021724A
Authority
CN
China
Prior art keywords
standard block
wiring
layers
standard
reserved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610958606.5A
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Chinese (zh)
Inventor
索超
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spreadtrum Communications Shanghai Co Ltd
Original Assignee
Spreadtrum Communications Shanghai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spreadtrum Communications Shanghai Co Ltd filed Critical Spreadtrum Communications Shanghai Co Ltd
Priority to CN201610958606.5A priority Critical patent/CN108021724A/en
Publication of CN108021724A publication Critical patent/CN108021724A/en
Pending legal-status Critical Current

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level

Abstract

The present invention provides a kind of wiring method of standard block.The described method includes:Connected up using Mi layers of standard block wiring channels;If Mi layers of all standard block wiring channel are occupied, in Mi+1 layers of reserved standard block wiring channel, connected up using the Mi+1 layers of standard block wiring channel in addition to reserved.The present invention can simplify wiring, improve the utilization rate of wiring channel, reduce and connect up connected resistance, promote overall digital circuit module area to reduce.

Description

The wiring method of standard block
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of wiring method of standard block.
Background technology
, it is necessary to be carried out to each standard block (Standard Cell) in standard cell lib after the completion of circuit design Layout design, in the layout design of standard block, connects the level for having identical connection relation with metal wire, this company The method for connecing cabling is known as connecting up.There is multiple layer metal articulamentum in a set of technique, first layer metal from the bottom up is connected herein Layer is known as Mi layers, and second layer metal articulamentum is known as Mi+1 layers, and so on.
The usual metal connecting layer for only using minimum two layers of domain wiring of standard block, i.e. Mi layers and Mi+1 layers.Wiring Usually there is specific rule in direction, i.e. Mi layers big by wiring as first layer metal articulamentum (that is, bottom metal connecting layer) Amount uses, so the Mi layers of wiring direction requirement do not fixed when connecting up and connecting;Mi+1 layers are used as second layer metal articulamentum, Be used for connecting up connection in more complex standard block, in order to rationally utilize metal layer routes resource, and with APR (Auto Place and Route, automatic placement and routing) in wiring direction requirement it is consistent, usually preassign Mi+1 layer as transverse direction cloth Line, can include the perforative Mi+1 layers of chance laterally connected up of several levels in the height of each standard block, we claim this cloth Line chance is standard block wiring channel.By taking standard block shown in Fig. 1 as an example, Mi+1 layers i.e. logical comprising 5 standard block wirings Road, wherein VDD are power supply, and VSS is ground.
A kind of situation that Fig. 2 is likely to occur when being existing standard unit wiring, wherein the standard block in left side occupy 1, 3rd, 4 standard block wiring channel, the standard block on right side occupies 2,3,5 standard block wiring channels, when the two standard lists When member is spliced to together, five standard block wiring channels are occupied altogether.When more standard blocks are spliced to together When, the standard block wiring channel of the Mi+1 layers of APR wirings is once occupied full, and just necessary skip floor takes Mi+2 layers of standard block Wiring channel resource, or other standard block wiring channels are taken, as shown in the encircled portion in Fig. 3.
In the implementation of the present invention, inventor has found at least to have the following technical problems in the prior art:Mi+1 layers There is no ad hoc rules in selection criteria unit wiring passage, can so cause the Mi+1 layers in various criterion unit to take a plurality of Different standard block wiring channels, thus can reduce limited metal connecting layer resource, reduce wiring channel utilization rate.
The content of the invention
The wiring method of standard block provided by the invention, can simplify wiring, improve the utilization rate of wiring, reduce wiring Connected resistance, promotes overall digital circuit module area to reduce.
The present invention provides a kind of wiring method of standard block, including:
Connected up using Mi layers of standard block wiring channels;
If Mi layers of all standard block wiring channel are occupied, in Mi+1 layers of reserved standard block wiring channel, Connected up using the Mi+1 layers of standard block wiring channel in addition to reserved.
Alternatively, it is described to include in Mi+1 layers of reserved standard block wiring channel:Each standard block the top will be located at Two standard block wiring channels with bottom are as reserved standard block wiring channel.
The standard block wiring channel wiring using Mi+1 layers in addition to reserved includes:Using laterally or vertically mode Connected up.
Alternatively, a kind of wiring method of standard block further includes:If described Mi+1 layers all standard block cloth Line passage is occupied, then is connected up using Mi+2 layers of standard block wiring channel.
Alternatively, it is described to be included using Mi+2 layers of standard block wiring channel wiring:Using with Mi+1 layers of wiring direction Different modes are connected up.
The wiring method of standard block provided in an embodiment of the present invention, first by Mi layers of standard block wiring channel cloth Line;If Mi layers of all standard block wiring channel are occupied, in Mi+1 layers of reserved standard block wiring channel, Mi is used + 1 layer of standard block wiring channel wiring in addition to reserved.The present invention can simplify wiring, improve the utilization rate of wiring channel, Further, reduce and connect up connected resistance, promote overall digital circuit module area to reduce.
Brief description of the drawings
Fig. 1 is the schematic diagram of Mi+1 layers of wiring channel of a standard block;
Fig. 2 is a kind of schematic diagram for connecting up effect of more Mi+1 layers of standard blocks;
Fig. 3 is that the APR of more standard blocks connects up the schematic diagram of effect;
Fig. 4 is the flow chart of the wiring method for the standard block that one embodiment of the invention provides;
Fig. 5 is to reserve showing for standard block wiring channel in the wiring method for the standard block that one embodiment of the invention provides It is intended to;
APR is connected up in other standard blocks in the wiring method for the standard block that Fig. 6 provides for one embodiment of the invention Schematic diagram;
Fig. 7 is to reserve standard block wiring channel in the wiring method for the standard block that another embodiment of the present invention provides Schematic diagram.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention In attached drawing, the technical solution in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only Only it is part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill Personnel's all other embodiments obtained without making creative work, belong to the scope of protection of the invention.
The present invention provides a kind of wiring method of standard block, as shown in figure 4, the described method includes:
S11, use Mi layers of standard block wiring channels wirings;
It is logical in Mi+1 layers of reserved standard block wiring if S12, Mi layers of all standard block wiring channel are occupied Road, is connected up using the Mi+1 layers of standard block wiring channel in addition to reserved.
Wherein, in standard unit picture design, according to the requirement in technological design rule, each standard block cloth is reserved The principle of line passage is:It is preferential reserve it is easy to this standard unit and other standards unit line, do not increase additional line face Long-pending standard block wiring channel;Or according to APR during standard block upper layer application and some special applications demands, specify some Standard block wiring channel is reserved standard block wiring channel.
Further, it is described to include but not limited in Mi+1 layers of reserved standard block wiring channel:
The first situation, using positioned at two standard block wiring channels of each standard block the top and bottom as Reserved standard block wiring channel.As shown in figure 5, containing left and right two standard blocks in figure, have inside each standard block Five standard block wiring channels, are denoted as 1~passage of passage 5 successively from top to bottom, have selected in each standard block it is most upper and Two standard block wiring channels under most, i.e. passage 1 and passage 5 are used as reserved standard block wiring channel Standard block wiring channel in addition to reserved, i.e. 2~passage of passage 4 connect up.In this case, as shown in fig. 6, APR exists To diagram two standard blocks or outside standard block connect up when, it is possible to the passage 1 reserved using the two standard blocks Connected up with passage 5, wherein the arrow on passage 1 and passage 5 shows a kind of wiring direction.
The second situation, randomly chooses two standard block wiring channels among in each standard block in Mi+1 layers For reserved standard block wiring channel.As shown in fig. 7, contain left and right two standard blocks in figure, inside each standard block There are five standard block wiring channels, randomly choosed passage 2 middle in each standard block and passage 4 as reserved mark Quasi- unit wiring passage, thus use the standard block wiring channel (the standard block wiring channel of i.e. 1,3 and 5) in addition to reserved Wiring.
Further, the standard block wiring channel wiring using Mi+1 layers in addition to reserved includes:Using transverse direction Or vertical mode is connected up.
Further, the method further includes:If described Mi+1 layers all standard block wiring channel is occupied, Connected up using Mi+2 layers of standard block wiring channels.
Further, it is described to be included using Mi+2 layers of standard block wiring channel wiring:Using with Mi+1 layers of wiring side Connected up to different modes.
Wherein, if connected up using Mi+1 layers of standard block wiring channel, horizontal wiring is have selected, then is using Mi+2 During the standard block wiring channel wiring of layer, it can only select vertically to connect up;Accordingly, if being connected up using Mi+1 layers of standard block During channel routing, vertical wiring is have selected, then when being connected up using Mi+2 layers of standard block wiring channel, transverse direction can only be selected Wiring.
The wiring method of standard block provided in an embodiment of the present invention, first by Mi layers of standard block wiring channel cloth Line;If Mi layers of all standard block wiring channel are occupied, in Mi+1 layers of reserved standard block wiring channel, Mi is used + 1 layer of standard block wiring channel wiring in addition to reserved.The present invention can simplify wiring, improve the utilization rate of wiring, reduce Connected resistance is connected up, promotes overall digital circuit module area to reduce.
The above description is merely a specific embodiment, but protection scope of the present invention is not limited thereto, any Those familiar with the art the invention discloses technical scope in, the change or replacement that can readily occur in, all should It is included within the scope of the present invention.Therefore, protection scope of the present invention should be subject to scope of the claims.

Claims (5)

  1. A kind of 1. wiring method of standard block, it is characterised in that including:
    Connected up using Mi layers of standard block wiring channels;
    If Mi layers of all standard block wiring channel are occupied, in Mi+1 layers of reserved standard block wiring channel, use The Mi+1 layers of standard block wiring channel wiring in addition to reserved.
  2. It is 2. according to the method described in claim 1, it is characterized in that, described in Mi+1 layers of reserved standard block wiring channel bag Include:Using positioned at two standard block wiring channels of each standard block the top and bottom as reserved standard block cloth Line passage.
  3. 3. method according to claim 1 or 2, it is characterised in that described to use the Mi+1 layers of standard list in addition to reserved First wiring channel wiring includes:Connected up using laterally or vertically mode.
  4. 4. according to the method described in claim 3, it is characterized in that, the method further includes:If Mi+1 layers of all mark Quasi- unit wiring passage is occupied, then is connected up using Mi+2 layers of standard block wiring channel.
  5. 5. according to the method described in claim 4, it is characterized in that, described connected up using Mi+2 layers of standard block wiring channel Including:Connected up by the way of different from Mi+1 layers of wiring direction.
CN201610958606.5A 2016-11-03 2016-11-03 The wiring method of standard block Pending CN108021724A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610958606.5A CN108021724A (en) 2016-11-03 2016-11-03 The wiring method of standard block

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610958606.5A CN108021724A (en) 2016-11-03 2016-11-03 The wiring method of standard block

Publications (1)

Publication Number Publication Date
CN108021724A true CN108021724A (en) 2018-05-11

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610958606.5A Pending CN108021724A (en) 2016-11-03 2016-11-03 The wiring method of standard block

Country Status (1)

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CN (1) CN108021724A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101114305A (en) * 2006-07-25 2008-01-30 格科微电子(上海)有限公司 Standard unit picture structure used for digital circuit
CN104063558A (en) * 2014-07-08 2014-09-24 领佰思自动化科技(上海)有限公司 Large scale integrated circuit path wiring method based on linear programming
CN104835821A (en) * 2014-02-07 2015-08-12 全视科技有限公司 Integrated circuit chip with global routing channels and application-specific integrated circuits
US20150333008A1 (en) * 2014-05-15 2015-11-19 Qualcomm Incorporated Standard cell architecture with m1 layer unidirectional routing

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101114305A (en) * 2006-07-25 2008-01-30 格科微电子(上海)有限公司 Standard unit picture structure used for digital circuit
CN104835821A (en) * 2014-02-07 2015-08-12 全视科技有限公司 Integrated circuit chip with global routing channels and application-specific integrated circuits
US20150333008A1 (en) * 2014-05-15 2015-11-19 Qualcomm Incorporated Standard cell architecture with m1 layer unidirectional routing
CN104063558A (en) * 2014-07-08 2014-09-24 领佰思自动化科技(上海)有限公司 Large scale integrated circuit path wiring method based on linear programming

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
卢永江: "《基于拓扑分析的多层通道布线算法》", 《电路与系统学报》 *
甘骏人 等: "《一种基于通孔数最小化的多层通道布线算法》", 《计算机学报》 *
陈国威11: "《第二章标准单元设计技术》", 《百度文库》 *

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Application publication date: 20180511