CN108021055B - Small AUV low-power-consumption controller based on reconfigurable strategy and control method - Google Patents

Abstract

The invention relates to a reconfigurable strategy-based small AUV low-power-consumption controller and a control method thereof.A MCU is connected with an FPGA; the FPGA is connected with a peripheral I/O management module; the off-chip FLASH is connected with the MCU, and the output latch is connected with the MCU; the peripheral I/O management module is connected with a plurality of peripheral function modules; the power supply module is connected with the MCU, the FPGA, the off-chip FLASH and the peripheral I/O management module. The power consumption of the controller can be reduced by methods of closing some functions of the controller which are not used any more, reducing the working frequency of the controller, enabling a logic gate in an idle state to enter a sleep mode or be completely closed and the like at different task stages and non-active time periods of the controller through the reconfiguration function, precious power energy is saved for the AUV powered by a battery, and the functional characteristics of long endurance and ultra-long standby of the small AUV can be effectively improved under the condition of not increasing energy.

Description

Small AUV low-power-consumption controller based on reconfigurable strategy and control method

Technical Field

The invention relates to the technical field of underwater robot control, in particular to a small AUV low-power-consumption controller based on a reconfigurable strategy and a control method.

Background

In recent years, with the development of underwater robot technology, the underwater robot is widely applied in various fields, and the carried function types are more and more abundant, one of which is the requirement of long-endurance and ultra-long standby of the underwater robot carrier. For small-sized AUV (autonomous underwater vehicle, abbreviated as AUV), the energy carried by the AUV is limited due to the volume and weight limitations, which puts severe demands on the control of low power consumption of the carrier itself.

The distribution of the small AUV's own energy is used for propulsion and attitude regulation functions, and most of the power consumption is concentrated in the control and communication system. Especially, in some application occasions, when the AUV is required to be able to maintain the standby state or the data processing and transferring state of the control system in the non-navigation state, the power consumption of the controller is particularly significant.

The current mainstream microcontroller manufacturers in the market have low-power consumption series products oriented to portable equipment and a battery power supply system due to the improvement of the low-power consumption microcontroller technology, for example, a PIC series single chip microcomputer of a micro-core company adopts various idle modes, dynamic mode switching, key module low-power consumption and other technologies to reduce the power consumption of the microcontroller to the milliwatt level; atmel company adopts the PicoPower technology with ultra-low power consumption, and creates the lowest ultra-low power consumption of a microcontroller, so that the low power consumption becomes a unique bright point. However, when looking back at the pursuit of high performance by the controller, the FPGA with powerful parallel processing capability is the most power consuming in the microprocessor of the control system, and looking further away at the integrated processor such as ZYNQ, CPU, etc., the power consumption is hundreds or thousands of times that of the ultramicro controller.

In the control field, the high performance and low power consumption of the system are always a pair of spears. At present, the reduction of the power consumption of a control system mainly aims at two aspects: selecting a device with lower power consumption and adopting a low-power-consumption control strategy. The selection of low-power-consumption devices mainly depends on the improvement of processes and technologies in the semiconductor industry, and low-power-consumption control strategies are diversified, and the main modes include a 'sleep-wake-up' mode for discontinuously working functional devices, unified management for system power supplies, continuous optimization of application software, battery control technologies, circuits and system designs and the like. However, each of the methods has advantages and disadvantages, for example, a certain power consumption still exists in the device entering the sleep mode, some core processors cannot completely enter the sleep mode in the system standby state, and the pre-designed functions cannot be increased or decreased at will. When a control system needs both low power consumption characteristics like a microcontroller and high performance quality like an FPGA, no solution can be found between high performance and low power consumption.

Disclosure of Invention

Aiming at the defects of the prior art, the invention provides a small AUV low-power-consumption controller based on a reconfigurable strategy and a control method, wherein an MCU is adopted as a low-end controller with low performance and reconfiguration functions, an FPGA is adopted as a high-end controller with high performance and reconfiguration objects, the work shared by the MCU and the FPGA is adjusted according to different mission, and the power consumption of the FPGA is further reduced by reconfiguring the FPGA, so that the purpose of reducing the power consumption of the whole control system is achieved.

The technical scheme adopted by the invention for realizing the purpose is as follows:

a reconfigurable policy based small AUV low power controller comprising:

the MCU is connected with the FPGA, sends a reconfiguration command to the FPGA and controls the reconfiguration process of the FPGA;

the FPGA is connected with the peripheral I/O management module and reconfigures the peripheral I/O resources of the peripheral I/O management module;

connecting the FLASH outside the chip with the MCU, receiving the reconfiguration file of the MCU, and storing the reconfiguration file

The output latch is connected with the MCU and used for keeping an output state;

the peripheral I/O management module is connected with a plurality of peripheral function modules;

the power supply module is connected with the MCU, the FPGA, the off-chip FLASH and the peripheral I/O management module to provide power for the off-chip FLASH.

The output latch is arranged in the peripheral I/O management module, and keeps high level in the reconfiguration process, so that the input and the output of the FPGA keep a synchronous state.

The peripheral function module comprises a CAN communication module, a serial communication module, an A/D and D/A conversion module and a general I/O module.

When the AUV is in a water surface working mode, the FPGA serves as a main processor, satellite communication and radio station communication are completed through serial port communication, mission downloading and remote control of a wireless network bridge are completed through a network port, and meanwhile the FPGA controls adjustment of a propeller and a stern rudder of the AUV through CAN communication;

when the AUV is transferred from the water surface to an underwater task, the satellite communication in the navigation system, a radio station and a wireless network bridge for short-distance communication are closed, the FPGA is reset by the MCU and is reconfigured through SPI communication, all logic control units in the reconfigured FPGA are released, and only the logic processing function required by the FPGA during underwater navigation of the AUV is reserved;

after the AUV finishes the underwater mission, the FPGA reconfigures, a satellite communication in a navigation system, a radio station and a wireless bridge for short-distance communication are started, and the peripheral functional module performs power failure or dormancy processing according to function reduction after the FPGA is reconfigured;

when the AUV enters a standby mode, the MCU reduces the working main frequency of the FPGA in a reconfiguration mode and only keeps the basic communication and processing functions of the FPGA.

The reconfiguration process comprises the steps of:

step 1: the MCU receives the FPGA configuration file of the upper computer, processes the configuration file and then sequentially stores the configuration file into the off-chip FLASH;

step 2: after the MCU receives the reconfiguration command, the latch latches the output state and sends the configuration file to the FPGA for reconfiguration;

and step 3: and after the FPGA is reconfigured, the latch releases the latch of the output state.

The invention has the following beneficial effects and advantages:

the invention can close some functions of the controller which are not used any more, reduce the working frequency of the controller, and enable the logic gate in an idle state to enter a sleep mode or be completely closed and the like at different task stages and inactive periods of the controller through the reconfiguration function of the FPGA, thereby reducing the power consumption of the controller, saving precious power energy for the AUV powered by the battery, and effectively increasing the functional characteristics of long endurance and ultra-long standby of the small AUV under the condition of not increasing the energy.

Drawings

FIG. 1 is a hardware block diagram of the present invention;

FIG. 2 is a reconfiguration flow diagram of the present invention;

fig. 3 is a reconfiguration mode transition flow diagram of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Fig. 1 shows a hardware configuration diagram of the present invention.

The small AUV low-power consumption controller based on the reconfiguration strategy is composed of two parts: the core control board and the function expansion bottom board are reconfigured. The reconfiguration core control board is composed of a power supply management module, a reconfiguration controller MCU, an off-chip FLASH, a reconfiguration object FPGA and a peripheral I/O management module. The power management module is responsible for completing power supply of the whole controller, the reconfiguration controller MCU is responsible for completing a reconfigurable control function, the off-chip FLASH is responsible for completing storage of a reconfiguration file, the reconfiguration object FPGA is responsible for completing a reconfiguration function of peripheral I/O resources, and the peripheral I/O management module is responsible for completing a control function of the function extension bottom plate. The function external expansion bottom plate comprises a CAN communication module, a serial port communication module, a common I/O module, an A/D and D/A module and other function modules, wherein the other function modules CAN be automatically increased or decreased according to the actual task requirements. The function expansion bottom plate is mainly responsible for finishing peripheral functions after executing reconfiguration.

The reconfiguration core control board can adjust the system peripheral resources and the working mode through reconfiguration according to the current task mission. The low-end controller MCU in the core control panel adopts an Atmega16AVR singlechip of Atmel company, and the singlechip has excellent low-power consumption characteristic; the high-end controller FPGA adopts Spartan6 series which is launched by Xilinx company facing to low-power-consumption markets and has the model of SPARTAN-6XC6SLX 45T. The CAN communication of the function external expansion bottom plate adopts an SJA1000 controller; the serial port RS232 and RS485 adopt MAX2232 and SN75176 communication conversion chips; the general I/O serial-parallel conversion adopts MAX7301 to increase the I/O quantity, and can also directly use the self I/O function of FPGA as fast I/O; 8 paths of A/D conversion chips can be additionally arranged and adopt MAX 1032; the 16 paths can be additionally provided with a D/A conversion chip adopting AD 5360.

Fig. 2 shows a reconfiguration flow chart of the present invention.

And the reconfiguration controller MCU in the core control board receives the FPGA configuration file of the upper computer, processes the configuration file and stores the processed configuration file in the off-chip FLASH in order. When the reconfiguration function needs to be started, the MCU first pulls the "PC 6" pin low from high according to the operation configuration command of the operating system or the upper computer, and at this time, the 8-way output pin of the latch 74HC573 keeps the original output state until the level on the "LE" pin connected to the MCU is pulled high from low. And then the MCU reads the FPGA configuration file matched with the reconfiguration instruction from the off-chip FLASH and transmits the configuration file to the FPGA to realize the reconfiguration of the FPGA. And finally, when the FPGA completes reconfiguration, the MCU pulls the level of a pin connected with a pin of the latch LE high from low, and at the moment, the latch keeps the synchronous state of input and output.

When the AUV is in a water surface working mode due to debugging requirements or mission downloading, recycling and the like, the FPGA serves as a main processor, communication functions such as satellite communication, radio stations and the like are completed through serial port communication, and mission downloading, remote control and the like of the wireless bridge are completed through a network interface. Meanwhile, the FPGA controls the propeller of the AUV and the adjustment of the stern rudder through CAN communication, and due to the parallel processing capacity of the FPGA, delay-free communication among multi-channel and multi-type communication systems CAN be achieved, so that the AUV control system is more real-time and accurate. And at the moment, the MCU completes functions such as AUV system power supply control, load control and the like which have low real-time requirements.

When the AUV is turned into underwater tasks from the water surface, the functions of satellite communication, a radio station and a wireless bridge for short-distance communication and the like in the navigation system are closed. At the moment, the MCU continues to work, the FPGA is reset by the MCU and is reconfigured through SPI communication, the reconfigured FPGA does not have the communication functions of a satellite, a radio station and a wireless bridge, namely all the logic control units in the FPGA are released, and only the logic processing function required by the FPGA during the underwater navigation of the AUV is reserved, so that the power consumption of the FPGA can be greatly reduced.

When the AUV finishes the underwater mission, the underwater is converted into the water surface, the reconfiguration mode is also adopted, and the specific flow is the reverse process of converting the water surface into the water. After the FPGA is reconfigured, part of the functional chips in the function external expansion bottom plate are subjected to power-off processing or dormancy processing by the power supply management and control system along with the reduction of related functions of the FPGA.

When the AUV enters a standby mode, the MCU on the core control board can lower the working main frequency of the FPGA in a reconfiguration mode, and meanwhile, the basic communication and processing functions of the FPGA are kept. Because the AUV only needs to keep basic functions in the standby mode and has lower requirement on timeliness, the power consumption of the system can be further reduced by reducing the working dominant frequency of the FPGA.

In the reconfiguration process, the FPGA does not have a power-down storage function, so that the configuration of the FPGA needs to be completed by a peripheral storage chip. In the invention, the FPGA only receives the configuration instruction of the MCU, so the FPGA enters a configuration waiting state after the FPGA is electrified and initialized. If the MCU is ready to configure the FPGA, the MCU needs to reset the FPGA at first, and the invention adopts the FPGA to reconfigure the slave mode in the serial mode. In this mode, the FPGA and the MCU each need 5 signal pins to complete the SPI communication function with each other. The related pin functions of the FPGA are described as follows:

the reset FPGA automatically receives the configuration file from the MCU, after the configuration is completed, a DONE pin of the FPGA is pulled high from low, and the MCU receives the signal to recognize that the FPGA is configured completely.

And (3) generating a configuration file of the FPGA by applying the Xilinx development environment in the upper computer, and finishing two functions of downloading and reconfiguring the configuration file of the FPGA through a mission downloading and configuration interface. Firstly, the FPGA configuration file needs to be subjected to hardware programming in an ISE development environment, and after simulation synthesis, iMPACT software is called to generate a download file ". BIT". Then, opening a serial port in an mission downloading and configuration interface, clicking a 'BIT' file to be downloaded according to path selection, and clicking 'start downloading' after the file is successfully loaded, thereby completing the downloading function of the FPGA configuration file (the file downloads a code into the MCU through serial port communication); the reconfiguration operation is firstly carried out in a scheme selection control by inputting a scheme code, after specific configuration scheme information is displayed in a lower display interface and manually checked, the 'starting configuration' is clicked, and then one reconfiguration can be finished. The whole operation process, error information and the like are displayed in the lowermost display control.

The reconfiguration operation function can also be completed on the actual MCU function board through key operation: the hardware system has 4 repeatable keys and 2 status indication LED lamps to complete the field reconfiguration of the FPGA. The first key function is a 'start reconfiguration' instruction, and the MCU is awakened from a sleep state at the moment; the second and third key functions are reconfiguration scheme selection, the reconfiguration scheme can support at most 99 types (the quantity of FLASH chips needs to be increased or decreased according to the quantity of codes of the actual reconfiguration scheme), and the two keys respectively correspond to ten bits and one bit of the scheme codes; the fourth key is a confirmation key, and after the reconfiguration scheme is selected, the confirmation is completed through the establishment. When the MCU receives the instruction of the confirmation key, firstly, the FPGA is informed to close related functions such as data processing and noncore communication, and partial important I/O functions are reserved; secondly, the single chip microcomputer latches an output latch to keep the important output signal unchanged until the FPGA completes the reconfiguration function; and finally, the single chip microcomputer resets the FPGA, reads out the reconfiguration code from the FLASH and transmits the reconfiguration code to the FPGA through SPI communication, after an FPGA configuration completion signal is fed back to the MCU, the MCU releases the latching function of the output latch, and the reconfiguration process is finished.

Fig. 3 shows a reconfiguration mode transition flow chart of the present invention.

And starting the system, wherein the MCU in the core controller, which is responsible for the reconfiguration function, firstly receives a task mission from an operating system or an upper computer and judges whether the mission belongs to the water surface or the water. If the water surface mission is the reason, the configuration file called by the MCU comprises functions of opening satellite communication, wireless network bridge, radio station communication and the like, and the configuration work of the FPGA is completed, at the moment, the MCU is responsible for monitoring the operation of the FPGA on one hand and bears the function that the AUV part has low requirement on the time sequence on the other hand. When the mission task starts to enter a low power consumption mode such as standby mode, the MCU starts to reconfigure the FPGA at the moment and latches some important output of the FPGA. The reconfigured FPGA only retains the minimum function required in the standby mode, the working main frequency of the FPGA is reduced according to the required grade, and for the FPGA, the power consumption of the FPGA can be greatly reduced by releasing part of functional logic gate circuits and reducing the main frequency; if the task mission belongs to an underwater mission, the configuration file called by the MCU comprises the functions of closing satellite communication, wireless network bridge, radio station communication and the like, and the configuration work of the FPGA is completed, the MCU monitors the running of the FPGA and simultaneously bears the function that the AUV part has low requirement on the time sequence, and in addition, the power management system closes part of functional chips which do not participate in the running of the system in the function external expansion bottom plate. And if the system enters a standby mode, the MCU reconfigures the FPGA in the same way of water mission so as to finish the low-power operation of the whole control system.

The function external expansion bottom plate circuit comprises CAN communication, serial RS232 and RS485 communication, A/D and D/A conversion, universal I/O and other resources. After the FPGA completes configuration, certain functions are selectively turned on according to the configuration scheme, and the chips which are not turned on with the corresponding functions are turned off through the power management system, so that the power consumption of the system is further reduced. When the function external expansion bottom plate resources can not meet the functions required by the current system, the function external expansion bottom plate can be continued on the basis of a core control plate, the configuration scheme carries out function external expansion through a fast I/O port carried by the FPGA, and if communication ports are increased, the A/D and the D/A are increased or decreased, the functions can be completed by controlling a corresponding conversion chip through the common I/O of the FPGA through SPI communication.

Based on two working states of the small AUV working on the water surface and under the water, the control and navigation system has great difference. When the AUV works in a water surface state, the navigation system mainly depends on a satellite navigation system, and navigation data is used as a reference during underwater navigation, and in addition, the control system can also start functions such as a wireless network bridge, a wireless radio station and the like sometimes so as to facilitate communication, debugging and control of shore-based personnel; when the AUV works in the underwater state, the functions are closed, and navigation mainly depends on a Doppler sound velocity meter, an inertial gyro unit and the like.

To minimize power consumption while maintaining high performance of the controller in both surface and underwater operating conditions of a small AUV, the controller needs to have the capability of function reconfiguration and to be able to automatically, in real time, switch the relevant configuration. Therefore, the MCU is used as a low-end controller with low performance and reconfiguration functions, the FPGA is used as a high-end controller with high performance and reconfiguration objects, the work shared by the MCU and the FPGA is adjusted according to different mission, and the power consumption of the FPGA is further reduced by reconfiguring the FPGA, so that the purpose of reducing the power consumption of the whole control system is achieved.

The MCU and the FPGA adopted by the invention have irreplaceability in similar functional products: the MCU adopts a high-end series singlechip of ATMEL company, the singlechip has the advantages of high performance and low power consumption in the industrial range, and is suitable for being applied to a battery-powered control system, the low power consumption characteristic of the MCU is far superior to the MCU such as a DSP, an ARM, a 51 singlechip and the like, and the MCU belongs to the optimal selection in the low power consumption characteristic range of the invention; the FPGA adopts a middle-low end series of Xilinx company, the series meets the performance required by the core processor of the invention, simultaneously, the power consumption is obviously reduced compared with the similar products, and the special parallel processing capability of the series can not cause the information delay of a communication system in the multi-node communication conversion, and the series is also superior to processors such as DSP, ARM and the like in the aspect of performance.

Claims (2)

1. A small AUV low power controller based on reconfigurable policy, comprising:

the MCU is connected with the FPGA, sends a reconfiguration command to the FPGA and controls the reconfiguration process of the FPGA;

the FPGA is connected with the peripheral I/O management module and reconfigures the peripheral I/O resources of the peripheral I/O management module;

connecting the FLASH outside the chip with the MCU, receiving the reconfiguration file of the MCU, and storing the reconfiguration file

The output latch is connected with the MCU and used for keeping an output state; the output latch is arranged in the peripheral I/O management module and keeps high level in the reconfiguration process, so that the input and the output of the FPGA keep a synchronous state;

the peripheral I/O management module is connected with a plurality of peripheral function modules; the peripheral function module comprises a CAN communication module, a serial communication module, an A/D and D/A conversion module and a general I/O module;

the power supply module is connected with the MCU, the FPGA, the off-chip FLASH and the peripheral I/O management module to provide power for the MCU, the FPGA, the off-chip FLASH and the peripheral I/O management module;

when the AUV is in a water surface working mode, the FPGA serves as a main processor, satellite communication and radio station communication are completed through serial port communication, mission downloading and remote control of a wireless network bridge are completed through a network port, and meanwhile the FPGA controls adjustment of a propeller and a stern rudder of the AUV through CAN communication;

when the AUV is transferred from the water surface to an underwater task, the satellite communication in the navigation system, a radio station and a wireless network bridge for short-distance communication are closed, the FPGA is reset by the MCU and is reconfigured through SPI communication, all logic control units in the reconfigured FPGA are released, and only the logic processing function required by the FPGA during underwater navigation of the AUV is reserved;

after the AUV finishes the underwater mission, the FPGA reconfigures, a satellite communication in a navigation system, a radio station and a wireless bridge for short-distance communication are started, and the peripheral functional module performs power failure or dormancy processing according to function reduction after the FPGA is reconfigured;

when the AUV enters a standby mode, the MCU reduces the working main frequency of the FPGA in a reconfiguration mode and only keeps the basic communication and processing functions of the FPGA;

the reconfiguration process comprises the steps of:

step 1: the MCU receives the FPGA configuration file of the upper computer, processes the configuration file and then sequentially stores the configuration file into the off-chip FLASH;

step 2: after the MCU receives the reconfiguration command, the latch latches the output state and sends the configuration file to the FPGA for reconfiguration;

and step 3: and after the FPGA is reconfigured, the latch releases the latch of the output state.

2. The control method of the controller according to claim 1, characterized in that:

when the AUV is in a water surface working mode, the FPGA serves as a main processor, satellite communication and radio station communication are completed through serial port communication, mission downloading and remote control of a wireless network bridge are completed through a network port, and meanwhile the FPGA controls adjustment of a propeller and a stern rudder of the AUV through CAN communication;

when the AUV is transferred from the water surface to an underwater task, the satellite communication in the navigation system, a radio station and a wireless network bridge for short-distance communication are closed, the FPGA is reset by the MCU and is reconfigured through SPI communication, all logic control units in the reconfigured FPGA are released, and only the logic processing function required by the FPGA during underwater navigation of the AUV is reserved;

after the AUV finishes the underwater mission, the FPGA reconfigures, a satellite communication in a navigation system, a radio station and a wireless bridge for short-distance communication are started, and the peripheral functional module performs power failure or dormancy processing according to function reduction after the FPGA is reconfigured;

when the AUV enters a standby mode, the MCU reduces the working main frequency of the FPGA in a reconfiguration mode and only keeps the basic communication and processing functions of the FPGA;

the reconfiguration process comprises the steps of:

step 1: the MCU receives the FPGA configuration file of the upper computer, processes the configuration file and then sequentially stores the configuration file into the off-chip FLASH;

step 2: after the MCU receives the reconfiguration command, the latch latches the output state and sends the configuration file to the FPGA for reconfiguration;

and step 3: and after the FPGA is reconfigured, the latch releases the latch of the output state.

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