CN108010845A - A kind of semiconductor devices and its manufacture method - Google Patents
A kind of semiconductor devices and its manufacture method Download PDFInfo
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- CN108010845A CN108010845A CN201610933857.8A CN201610933857A CN108010845A CN 108010845 A CN108010845 A CN 108010845A CN 201610933857 A CN201610933857 A CN 201610933857A CN 108010845 A CN108010845 A CN 108010845A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000011248 coating agent Substances 0.000 claims abstract description 52
- 238000000576 coating method Methods 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 47
- 238000002955 isolation Methods 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 13
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract 3
- 238000000151 deposition Methods 0.000 claims description 10
- 239000000463 material Substances 0.000 description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 20
- 238000005516 engineering process Methods 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 11
- 239000012212 insulator Substances 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 239000007789 gas Substances 0.000 description 8
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 8
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 239000000470 constituent Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 230000000873 masking effect Effects 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 6
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 230000002708 enhancing effect Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 4
- 229910003978 SiClx Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000011435 rock Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 125000001153 fluoro group Chemical group F* 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
Abstract
The present invention provides a kind of semiconductor devices and its manufacture method, including：Semiconductor substrate is provided, is fully located in the Semiconductor substrate formed with first grid structure and second grid structure, the first grid structure on active area, the second grid structure division is located on isolation structure；Form the coating for covering the Semiconductor substrate, first grid structure and second grid structure；Mask layer is formed on the coating of the second grid superstructure, and is etched back to not performed by the coating that the mask layer covers；Etching is performed, to form groove in the Semiconductor substrate of the first grid structure both sides；SiGe layer is grown in the groove.Compared with the prior art, the present invention proposes the manufacture method of semiconductor devices, can form complete Σ shapes SiGe layer.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of semiconductor devices and its manufacture method.
Background technology
Embedded germanium silicon technology (embedded SiGe, eSiGe) is a kind of strained silicon skill for being used for improving PMOS performances
Art.It is to increase the hole mobility of PMOS by producing uniaxial compressive stress in channels, so as to improve the electric current of transistor
Driving force is 45nm and following technology for the core technology in high-performance technique.Its principle be formed in PMOS source/drain region it is recessed
Groove, then the epitaxial growth SiGe layer inside source drain recesses, is introduced to ditch using SiGe lattice constants and the mismatch of Si
The compression in road, this stress cause semiconductor crystal lattice to be distorted, and generate the simple stress in channel region
(uniaxial stress), and then the charge transport properties of band arrangement and semiconductor are influenced, by controlling in resulting devices
Stress size and distribution, the mobility in hole is improved, so as to improve the performance of device.
In existing embedded germanium silicon technology, ∑ connected in star is usually formed in the source/drain region of PMOS for wherein
The embedded germanium silicon of selective epitaxial growth, ∑ connected in star can effectively shorten the length of device channel, and enhancing SiGe should to raceway groove
The influence of power, and meet the scaled requirement of device size.However, there is also some challenges for embedded germanium silicon technology.
For example, due to being hindered be subject to fleet plough groove isolation structure, complete ∑ shape SiGe layer cannot be formed in narrow width regions, seriously
The growth of Si cap is influenced, so as to cause the generation of contact hole punch through, reduces PMOS device performance.
Therefore, it is necessary to a kind of semiconductor devices and its manufacture method are proposed, to solve the above problems.
The content of the invention
In view of the deficiencies of the prior art, the present invention provides a kind of manufacture method of semiconductor devices, including：Semiconductor is provided
Substrate, formed with first grid structure and second grid structure, the complete position of first grid structure in the Semiconductor substrate
In on active area, the second grid structure division is located on isolation structure；
Form the coating for covering the Semiconductor substrate, first grid structure and second grid structure；
Mask layer is formed on the coating of the second grid superstructure, and to not covered by what the mask layer covered
Cap rock is performed and is etched back to；
Etching is performed, to form groove in the Semiconductor substrate of the first grid structure both sides；
SiGe layer is grown in the groove.
Exemplarily, the shape of the groove is Σ shapes.
Exemplarily, the coating is SiN layer.
Exemplarily, the mask layer at least covers the part that the coating is located on isolation structure.
Exemplarily, the bottom for the coating being formed on the side wall of the second grid structure is covered to active area.
Exemplarily, it is 1~8nm that the coating, which is covered to the size of active area,.
Exemplarily, the mask layer at least covers the coating on the side wall of the second grid structure.
Exemplarily, also include before depositing the coating between being formed in first grid structure and second grid structure
The step of gap wall.
Exemplarily, also include being formed in first grid structure and second grid structure before depositing the coating inclined
The step of moving side wall.
The present invention also provides a kind of semiconductor devices prepared using the above method.
Compared with the prior art, the present invention proposes the manufacture method of semiconductor devices, can form complete Σ shapes SiGe layer.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 is a kind of schematic cross sectional view of semiconductor devices in the prior art；
Fig. 2 is a kind of indicative flowchart of the manufacture method of semiconductor devices of an alternative embodiment of the invention；
Fig. 3 a- Fig. 3 f are that a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention is formed
Structure sectional view.
Embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then there is no element or layer between two parties.It should be understood that although it can make
Various elements, component, area, floor and/or part are described with term first, second, third, etc., these elements, component, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, component, area, floor or part with it is another
One element, component, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to further include to make
With the different orientation with the device in operation.For example, if the device upset in attached drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
In existing embedded germanium silicon technology, ∑ connected in star is usually formed in the source/drain region of PMOS for wherein
Selective epitaxial growth SiGe layer, ∑ connected in star can effectively shorten the length of device channel, and SiGe is to channel stress for enhancing
Influence, and meet the scaled requirement of device size.As shown in Figure 1, in the prior art using embedded germanium silicon technology
PMOS device includes：Semiconductor substrate 101, fleet plough groove isolation structure 102, SiGe layer 103 and gate structure 104, wherein,
In narrow width regions, due to being subject to the obstruction of fleet plough groove isolation structure 102, it is impossible to form complete ∑ shape SiGe layer, seriously
The growth of Si cap is influenced, so as to cause the generation of contact hole punch through, reduces PMOS device performance.
In view of the deficiencies of the prior art, the present invention provides a kind of manufacture method of semiconductor devices, including：
Semiconductor substrate is provided, it is described formed with first grid structure and second grid structure in the Semiconductor substrate
First grid structure is fully located on active area, and the second grid structure division is located on isolation structure；
Form the coating for covering the Semiconductor substrate, first grid structure and second grid structure；
Mask layer is formed on the coating of the second grid superstructure, and to not covered by what the mask layer covered
Cap rock is performed and is etched back to；
Etching is performed, to form groove in the Semiconductor substrate of the first grid structure both sides；
SiGe layer is grown in the groove.
The shape of the groove is Σ shapes.
The coating is SiN layer.
The mask layer at least covers the part that the coating is located on isolation structure.
The bottom for the coating being formed on the side wall of the second grid structure is covered to active area.The coating covers
The size of lid to active area is 1~8nm.The mask layer at least covers the coating on the side wall of the second grid structure.
Also include the step that clearance wall is formed in first grid structure and second grid structure before depositing the coating
Suddenly.Also include forming the step of deviating side wall in first grid structure and second grid structure before depositing the coating.
Compared with the prior art, the present invention proposes the manufacture method of semiconductor devices, can form complete Σ shapes SiGe layer.
In order to thoroughly understand the present invention, detailed structure and/or step will be proposed in following description, to explain this
Invent the technical solution proposed.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, this hair
It is bright to have other embodiment.
[exemplary embodiment one]
The manufacture method of the semiconductor devices of an embodiment of the present invention is done below with reference to Fig. 2 and Fig. 3 a~Fig. 3 f
It is described in detail.
First, step 201 is performed, as shown in Figure 3a, there is provided Semiconductor substrate 301, forms in the Semiconductor substrate 301
There are first grid structure 303a and second grid structure 303b, the second grid structure 303b parts to be located at isolation structure 302
On.The constituent material of Semiconductor substrate 301 can use undoped monocrystalline silicon, doped with the monocrystalline silicon of impurity, insulator
Silicon (SSOI) is laminated on silicon (SOI), insulator, SiGe (S-SiGeOI), germanium on insulator SiClx are laminated on insulator
(SiGeOI) and germanium on insulator (GeOI) etc..As an example, in the present embodiment, the constituent material of Semiconductor substrate 301
Select monocrystalline silicon.For PMOS, in the Semiconductor substrate 301 can also formed with N trap (not shown)s, and
Formed before gate structure, low dose of boron injection can be carried out once to whole N traps, for adjusting the threshold voltage V of PMOSth。
Formed with isolation structure 302 in Semiconductor substrate 301, as an example, isolation structure 302 is isolated for shallow trench
(STI) structure or selective oxidation silicon (LOCOS) isolation structure.In the present embodiment, the isolation structure 302 is isolated for shallow trench
Structure.Various traps (well) structure is also formed with Semiconductor substrate 301, to put it more simply, being omitted in diagram.
Formed with first grid structure 303a, second grid structure 303b in Semiconductor substrate 301, wherein, described
One gate structure 303a is fully located on active area, and second grid structure 303b parts are on isolation structure 302.As showing
Example, first grid structure 303a, second grid structure 303b include gate dielectric, gate material layers and the grid stacked gradually
Hard masking layer.Gate dielectric includes oxide skin(coating), such as silica (SiO2) layer.Gate material layers include polysilicon layer,
One or more in metal layer, conductive metal nitride layer, conductive metal oxide layer and metal silicide layer, its
In, the constituent material of metal layer can be tungsten (W), nickel (Ni) or titanium (Ti)；Conductive metal nitride layer includes titanium nitride
(TiN) layer；Conductive metal oxide layer includes yttrium oxide (IrO2) layer；Metal silicide layer includes titanium silicide (TiSi) layer.
Grid hard masking layer includes the one or more in oxide skin(coating), nitride layer, oxynitride layer and amorphous carbon.Gate dielectric
The forming method of layer, gate material layers and grid hard masking layer can be familiar with any existing using those skilled in the art
Technology, such as chemical vapour deposition technique (CVD), including low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition
(LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD) etc..
Alternatively, can also first grid structure 303a, second grid structure 303b side wall on formed offset side wall
(offset spacer).Specifically, the offset side wall can be silica, silicon nitride, it is a kind of in silicon oxynitride or they
Combination is formed.The effect of offset side wall is the channel length for improving transistor, reduces short-channel effect and since short channel is imitated
Should caused hot carrier's effect.As an embodiment of the present embodiment, the offset side wall is silica, silicon nitride is common
With composition, concrete technology is：The first silicon oxide layer, the first silicon nitride layer and are formed in Semiconductor substrate and gate structure
Silicon dioxide layer, then forms offset side wall using engraving method.Can also on the top surface and side wall of dummy gate structure equal shape
Into side-wall material layer, in the steps afterwards by the method for planarization, such as chemical mechanical grinding, by the side wall material on top surface
The bed of material removes, and forms the offset side wall being located only within side wall.
Exemplarily, it is additionally included in be formed in the substrate of gate structure either side in the present embodiment and source/drain is lightly doped
(LDD).The method of the formation LDD can be ion implantation technology or diffusion technique.The ionic type of the LDD ion implantings
Determine that the device is PMOS device in the present invention according to by the electrical of semiconductor devices to be formed, then it injects ion
It can be arbitrary p-type Doped ions, include but not limited to boron (B) ion, indium (In) ion.According to required foreign ion
Concentration, ion implantation technology can be completed with one or multi-step, and the energy and dosage of injection can continue to select according to actual needs
Select, details are not described herein.
Then, clearance wall (main spacer) can be also formed on the offset side wall that substrate and above-mentioned steps are formed,
The gap wall material bed of material can be a kind of in silica, silicon nitride, silicon oxynitride or they combine and form.One as the present embodiment
Middle embodiment, spacer material for silica, silicon nitride by collectively constituting.Can silicon oxide layer deposited and nitrogen on substrate
SiClx layer, then forms clearance wall using engraving method, and the clearance wall can have the thickness of 10-30nm.Then, ion is used
Injection technology or diffusion technique heavy doping source electrode and drain electrode (S/D) are formed in the substrate of grid gap wall either side.Can be with
Deposited including annealing steps, formation pouch-shaped injection region, NiSi and etc..
Next, performing step 202, as shown in Figure 3b, formed and cover the Semiconductor substrate 301, first grid structure
The coating 304 of 303a and second grid structure 303b.The coating 304 can be in gate structure, offset side wall or clearance wall
Formed afterwards.It should be noted that the bottom for the coating 304 being formed on second grid structure 303b side walls need to intactly be covered
Lid isolation structure 302, and cover to active area, to make obstruction of the groove that subsequent etching is formed from isolation structure 303, from
And form complete Σ shapes SiGe layer.The preparation method of the coating 304 can be physical vapour deposition (PVD) (PVD), chemical gas
Mutually deposition (CVD), atomic layer deposition (ALD), plasma enhancing ALD (PE-ALD), plasma enhanced CVD (PECVD), electricity
From PVD (I-PVD) or other suitable depositing operations.As an example, coating 204 can be silicon nitride layer, second is formed at
The size of the bottom covering active area of coating on gate structure 303b side walls is 1~8nm, after which can ensure
Continue the Σ connected in stars of etching formation from the obstruction of isolation structure 302.
Then, step 203, as shown in Figure 3c, the shape on the coating 304 above the second grid structure 303b are performed
It is etched back into mask layer 305, and to not performed by the coating 304 that the mask layer 305 covers.The patterned mask layer
305 can be any suitable mask material well known to those skilled in the art, include but not limited to Other substrate materials or hard
Mask material, in the present embodiment, the mask layer is photoresist.The mask layer at least covers the coating and is located at isolation junction
Part on structure.It is preferred that the mask layer at least covers the coating 304 on the side wall of the second grid structure 303b.
Then, as shown in Figure 3d, the coating in the first grid structure is performed and is etched back to (pull back), from
And make the width between the coating on gate structure sidewall define subsequent etching groove opening width.In the present embodiment,
The technique that is etched back to is dry etch process, and exemplarily, etching gas can be CF4；The range of flow of etching gas is
10sccm~100sccm, is, for example, 50sccm, and the time range of etching is 5s~60s, is, for example, 20s；Pass through described time quarter
Erosion, adjusts the thickness of the coating on first grid structure 303a, without changing the second grid structure covered with mask layer 305
The thickness of coating on 303b, makes the width between the blanket layer side wall define the opening width of SiGe grooves, avoids
During relatively narrow region etch SiGe grooves, complete Σ connected in stars cannot be formed due to being subject to the obstruction of STI etc..Performing back
After etching, conventional cineration technics can be used to remove the photoresist.
Next, performing step 204, as shown in Figure 3 e, etching is performed, with the first grid structure 303a both sides
Groove 306 is formed in Semiconductor substrate 301.The groove 306 is Σ shapes.As an example, first lost using anisotropic dry method
It is engraved in the Semiconductor substrate 301 of gate structure both sides and forms bowl-shape groove, etching gas includes HBr, Cl2, He and O2, be free of
There is fluorine base gas.The dry etching can be etched back to carry out in same reaction chamber with above-mentioned.Next, using wet etching work
Skill etches the bowl-shape groove, using the etchant of wet etching on the different crystal orientations of the constituent material of Semiconductor substrate 301
The different characteristic of etch-rate (etch-rate of 200 crystal orientation and 120 crystal orientation is higher than the etch-rate of 111 crystal orientation), extension erosion
The bowl-shape groove is carved to form ∑ shape groove 306.As an example, the corrosive liquid of the wet etching is tetramethylammonium hydroxide
(TMAH) solution, temperature are 30 DEG C -60 DEG C, depending on desired size of the duration according to ∑ shape groove 306, generally 200s-
300s。
Then, step 205 is performed, as illustrated in figure 3f, SiGe layer 306 ' is grown in the groove 306.Exemplarily, it is first
The first epitaxial growth SiGe Seed Layers in groove 306.The lattice constant of the relatively low SiGe Seed Layers of Ge contents is closer in substrate
The lattice constant of silicon, it is alternatively that the cushion during the higher SiGe epitaxial layers of property epitaxial growth Ge contents, is conducive to
To the SiGe epitaxial layers of high quality.Then, epitaxial growth SiGe body layers on the seed layer, the concentration containing Ge in SiGe body layers
Higher than Seed Layer.In order to ensure applying appropriate stress to the channel region of semiconductor devices, the SiGe layer usually can all be higher than
The upper surface of the Semiconductor substrate 301.Then, in one layer of Si cap of body layer Epitaxial growth on the body layer
(Si cap), wherein, the material of cap includes but not limited to SiB, SiGe, SiGeB, SiC, SiCB etc..Exemplarily, seed
The concentration containing Ge of layer is preferably 5-20%, and the concentration containing Ge of body layer is preferably 30-50%.The epitaxial growth technology includes low
Pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD
(UHVCVD), one kind in rapid thermal CVD (RTCVD) and molecular beam epitaxy (MBE).Specifically, using gas source
Molecular beam epitaxial method grows SiGe layer, by the use of silane or disilane as silicon source, while adds a certain amount of germane.For example,
Select GeH4And SiH2Cl2As reacting gas, and select H2As carrier gas, the temperature of deposition is 300-1000 DEG C, gas pressure
For 1-50Torr.
After performing above-mentioned steps, the subsequent step in existing embedded germanium silicon technology can be continued to execute.
So far, the processing step that according to an exemplary embodiment of the present one method is implemented is completed.It is understood that
The present embodiment method, semi-conductor device manufacturing method not only includes above-mentioned steps, before above-mentioned steps, among or may also include afterwards
Other desired step, it is included in the range of this implementation manufacture method.
Compared with the prior art, the present invention proposes the manufacture method of semiconductor devices, can form complete Σ shapes SiGe layer.
[exemplary embodiment two]
With reference to Fig. 3 f, schematically cuing open for the semiconductor devices that the manufacture method provided according to the present invention obtains illustrated therein is
Face figure.The semiconductor devices includes：Semiconductor substrate 301, isolation structure 302, first grid structure 303a, second grid knot
Structure 303b, coating 304, SiGe layer 306 '.
Wherein, the constituent material of Semiconductor substrate 301 can use undoped monocrystalline silicon, the monocrystalline doped with impurity
Silicon, silicon-on-insulator (SOI), be laminated silicon (SSOI) on insulator, SiGe (S-SiGeOI) be laminated on insulator, on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc..As an example, in the present embodiment, the structure of Semiconductor substrate 301
Into material selection monocrystalline silicon., can also be formed with N trap (not shown)s in the Semiconductor substrate 301 for PMOS.
Formed with isolation structure 302 in Semiconductor substrate 301, as an example, isolation structure 302 is isolated for shallow trench
(STI) structure or selective oxidation silicon (LOCOS) isolation structure.In the present embodiment, the isolation structure is shallow trench isolation junction
Structure.Various traps (well) structure is also formed with Semiconductor substrate 301, to put it more simply, being omitted in diagram.
Formed with first grid structure 303a, second grid structure 303b in Semiconductor substrate 301, wherein, described
One gate structure 303a is fully located on active area, and second grid structure 303b parts are on isolation structure 302.As showing
Example, first grid structure 303a, second grid structure 303b include gate dielectric, gate material layers and the grid stacked gradually
Hard masking layer.Gate dielectric includes oxide skin(coating), such as silica (SiO2) layer.Gate material layers include polysilicon layer,
One or more in metal layer, conductive metal nitride layer, conductive metal oxide layer and metal silicide layer, its
In, the constituent material of metal layer can be tungsten (W), nickel (Ni) or titanium (Ti)；Conductive metal nitride layer includes titanium nitride
(TiN) layer；Conductive metal oxide layer includes yttrium oxide (IrO2) layer；Metal silicide layer includes titanium silicide (TiSi) layer.
Grid hard masking layer includes the one or more in oxide skin(coating), nitride layer, oxynitride layer and amorphous carbon.Gate dielectric
The forming method of layer, gate material layers and grid hard masking layer can be familiar with any existing using those skilled in the art
Technology, such as chemical vapour deposition technique (CVD), including low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition
(LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD) etc..
Alternatively, first grid structure 303a, second grid structure 303b side wall on formed offset side wall
(offset spacer).Specifically, the offset side wall can be silica, silicon nitride, it is a kind of in silicon oxynitride or they
Combination is formed.The effect of offset side wall is the channel length for improving transistor, reduces short-channel effect and since short channel is imitated
Should caused hot carrier's effect.As an embodiment of the present embodiment, the offset side wall is silica, silicon nitride is common
With composition.
Alternatively, formed with clearance wall (main spacer) on above-mentioned offset side wall, spacer material layer can be oxygen
A kind of or their combinations are formed in SiClx, silicon nitride, silicon oxynitride.As embodiment in the one of the present embodiment, clearance wall
Material for silica, silicon nitride by collectively constituting.
The coating 304 covers first grid structure 303a and second grid structure the 303b surfaces.As an example,
Coating 204 can be silicon nitride layer, its preparation method can be physical vapour deposition (PVD) (PVD), chemical vapor deposition (CVD),
Atomic layer deposition (ALD), plasma enhancing ALD (PE-ALD), plasma enhanced CVD (PECVD), ionization PVD (I-PVD)
Or other suitable depositing operations.Between coating 304 on first grid structure 303a and second grid structure 303b side walls
Distance definition formed SiGe layer groove opening size.
Formed with SiGe layer 306 ' in the Semiconductor substrate 301 of first grid structure 303a both sides.Exemplarily, it is described
SiGe layer 306 ' is complete ∑ shape.The SiGe layer 306 ' includes SiGe Seed Layers, SiGe body layers and Si cap, its
Lattice constant of the lattice constant of the relatively low SiGe Seed Layers of middle Ge contents closer to silicon in substrate, it is alternatively that property epitaxial growth
Cushion during the higher SiGe epitaxial layers of Ge contents, is conducive to obtain the SiGe epitaxial layers of high quality.Then, in seed
Layer Epitaxial growth SiGe body layers, the concentration containing Ge in SiGe body layers are higher than Seed Layer.In order to ensure to semiconductor devices
Channel region apply appropriate stress, the SiGe layer usually can all be higher than the upper surface of the Semiconductor substrate 301.It is exemplary
Ground, the concentration containing Ge of Seed Layer is preferably 5-20%, and the concentration containing Ge of body layer is preferably 30-50%.The material bag of cap
Include but be not limited to SiB, SiGe, SiGeB, SiC, SiCB etc..The growth technique of the SiGe layer is epitaxial growth technology, such as low
Pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD
(UHVCVD), one kind in rapid thermal CVD (RTCVD) and molecular beam epitaxy (MBE).
Compared with the prior art, the present invention proposes semiconductor devices, its SiGe structure is complete Σ shapes.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, teaching according to the present invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (10)
- A kind of 1. manufacture method of semiconductor devices, it is characterised in that including：Semiconductor substrate is provided, formed with first grid structure and second grid structure in the Semiconductor substrate, described first Gate structure is fully located on active area, and the second grid structure division is located on isolation structure；Form the coating for covering the Semiconductor substrate, first grid structure and second grid structure；Mask layer, and the coating to not covered by the mask layer are formed on the coating of the second grid superstructure Execution is etched back to；Etching is performed, to form groove in the Semiconductor substrate of the first grid structure both sides；SiGe layer is grown in the groove.
- 2. according to the method described in claim 1, it is characterized in that, the shape of the groove is Σ shapes.
- 3. according to the method described in claim 1, it is characterized in that, the coating is SiN layer.
- 4. according to the method described in claim 1, it is characterized in that, the mask layer at least covers the coating positioned at isolation Part in structure.
- 5. according to the method described in claim 1, it is characterized in that, it is formed at the covering on the side wall of the second grid structure The bottom of layer is covered to active area.
- 6. according to the method described in claim 5, it is characterized in that, the coating cover size to active area for 1~ 8nm。
- 7. according to the method described in claim 5, it is characterized in that, the mask layer at least covers the second grid structure Coating on side wall.
- 8. according to the method described in claim 1, it is characterized in that, it is additionally included in first grid knot before depositing the coating The step of clearance wall is formed on structure and second grid structure.
- 9. according to the method described in claim 1, it is characterized in that, it is additionally included in first grid knot before depositing the coating The step of offset side wall is formed on structure and second grid structure.
- A kind of 10. semiconductor devices prepared using one of claim 1-9 the method.
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| CN102456739A (en) * | 2010-10-28 | 2012-05-16 | 中国科学院微电子研究所 | Semiconductor structure and forming method thereof |
| US8350253B1 (en) * | 2010-01-29 | 2013-01-08 | Xilinx, Inc. | Integrated circuit with stress inserts |
| US20130240956A1 (en) * | 2012-03-14 | 2013-09-19 | United Microelectronics Corporation | Semiconductor device and method for fabricating the same |
| CN103681327A (en) * | 2012-09-06 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
| CN105489496A (en) * | 2014-10-01 | 2016-04-13 | 格罗方德半导体公司 | OPC enlarged dummy electrode to eliminate ski slope at eSiGe |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8350253B1 (en) * | 2010-01-29 | 2013-01-08 | Xilinx, Inc. | Integrated circuit with stress inserts |
| CN102456739A (en) * | 2010-10-28 | 2012-05-16 | 中国科学院微电子研究所 | Semiconductor structure and forming method thereof |
| US20130240956A1 (en) * | 2012-03-14 | 2013-09-19 | United Microelectronics Corporation | Semiconductor device and method for fabricating the same |
| CN103681327A (en) * | 2012-09-06 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and formation method thereof |
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