CN108008668A - A kind of method of the large-scale parallel data sampling control sequential based on DSP-FPGA - Google Patents

A kind of method of the large-scale parallel data sampling control sequential based on DSP-FPGA Download PDF

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Publication number
CN108008668A
CN108008668A CN201711073244.2A CN201711073244A CN108008668A CN 108008668 A CN108008668 A CN 108008668A CN 201711073244 A CN201711073244 A CN 201711073244A CN 108008668 A CN108008668 A CN 108008668A
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dsp
sampling
fpga
direct current
voltage
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CN108008668B (en
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范瑞祥
徐宁
辛建波
王文彬
蒙天琪
李琼
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State Grid Corp of China SGCC
Electric Power Research Institute of State Grid Jiangxi Electric Power Co Ltd
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State Grid Corp of China SGCC
Electric Power Research Institute of State Grid Jiangxi Electric Power Co Ltd
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    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems
    • G05B19/02Programme-control systems electric
    • G05B19/04Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423Input/output
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/20Pc systems
    • G05B2219/24Pc safety
    • G05B2219/24215Scada supervisory control and data acquisition

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

A kind of method of the large-scale parallel data sampling control sequential based on DSP FPGA, the method are carried out parallel data by DSP FPGA sampling plates by DSP control system and direct current sampling system and are sampled.DSP control system is transmitted to systematic sampling plate in the form of fiber-optic signal by gathering three-phase system voltage, three-phase output current, threephase load electric current and reference voltage from main circuit;DSP FPGA sampling plates are transferred to by motherboard after converted;Voltage signal is converted into frequency signal by direct current sampling system by the sampling voltage-frequency change-over panel of chain structure, and gives the frequency signal transmission after processing to DSP FPGA sampling plates by optical-fibre communications mode.Large-scale parallel data sampling control sequential of the present invention can greatly improve parallel data acquisition transmission speed and capacity;Using DSP FPGA controlling of sampling sequential large-scale parallel data sampling control technology can be made to have very big lifting in terms of transmission speed, capacity and security.

Description

A kind of method of the large-scale parallel data sampling control sequential based on DSP-FPGA
Technical field
The present invention relates to a kind of method of the large-scale parallel data sampling control sequential based on DSP-FPGA, belongs to electric power number According to acquisition control technical field.
Background technology
Under the historical background that energy Internet technology is grown rapidly, large-scale data sampling control technology seems particularly It is crucial.How safe and reliable, high speed batch capture large-scale data is the difficult point of data sampling techniques.It is common to be based on DSP Sampled-data system there is small, good, inexpensive, the high performance disposal ability of stability, while can be parallel Perform multiple operations;And FPGA has multiple signals parallel processing capability, in addition with speed is fast, flexibility is high, the design cycle The characteristics of short.
The content of the invention
The object of the present invention is to for when early period, DSP was coupled with the information of FPGA by parallel local bus, generally all pass Defeated one group of data, timing control are relatively easy, it is impossible to realize mass rapid data communication;For safe and reliable, realization of High Speed The batch capture of large-scale data, the present invention propose a kind of large-scale parallel data sampling control sequential based on DSP-FPGA Method.
Realize the technical scheme is that, a kind of large-scale parallel data sampling control sequential based on DSP-FPGA Method, carries out parallel data by DSP-FPGA sampling plates by DSP control system and direct current sampling system and samples, DSP controls system System by gathering three-phase system voltage, three-phase output current, threephase load electric current and reference voltage, in the form of fiber-optic signal from Main circuit is transmitted to systematic sampling plate, and by motherboard DSP-FPGA sampling plates are transferred to after converted;Direct current sampling system passes through Voltage signal is converted into frequency signal by the sampling voltage-frequency change-over panel of chain structure, and by optical-fibre communications mode by after processing Frequency signal transmission gives DSP-FPGA sampling plates;The DSP-FPGA sampling plates controlling of sampling sequential is as follows:
(1) dsp chip sends the chip selection signal that CS2 and CS1 is 01, chooses sampling FPGA.
(2) FPGA sends ready signal that Ready2 and Ready1 is 01 to dsp chip, represents that FPGA is idle, can carry out Data sampling;Dsp chip CSFlag puts 1.
(3) FPGA reads and uploads the system voltage voltage-frequency signal pulse number of each CLK_100us clock cycle, is each The DC voltage voltage-frequency signal pulse number of Clk_20ms clock cycle is to dsp chip, and in each DSP_CLK rising edge clocks When, dsp chip reads the data that FPGA is uploaded.
(4) press step (3), FPGA continues 36 road DC voltages, load current, output current, reference voltage send to Dsp chip.
(5) CS2CS1 is put 11 by dsp chip, cancels chip selection signal.
(6) Ready2 and Ready1 are put 11 by FPGA, into busy condition.
(7) sampling terminates.
The DSP control system includes DSP control panels, DSP sampling systems, DSP protection systems and DSP triggering controls system System;The DSP control panels connect DSP sampling systems by controlling bus, DSP protects system and DSP Triggering Control Systems;It is described DSP sampling systems are made of DSP-FPGA sampling plates, direct current sampling plate and systematic sampling plate.
It is described to give the frequency signal transmission after processing to DSP-FPGA sampling plates by optical-fibre communications mode, refer to and adopted from direct current The capacitance voltage that the direct current sampling plate of sample system comes out is connected to Optical fibre sampling plate in the form of fiber-optic signal, and Optical fibre sampling plate will It is converted into electric signal, after line level of going forward side by side conversion, is transferred to the DSP-FPGA sampling plates of direct current sampling system.
The direct current sampling system includes chain link sampling voltage-frequency change-over panel, direct current sampling plate and DSP-FPGA sampling plates;Institute Direct current sampling system is stated per being mutually made of 12 chain structures, every chain structure has 1 piece of chain link sampling voltage-frequency change-over panel, common A, B, C three-phases;Every piece of chain link sampling voltage-frequency change-over panel is located at the inside of chain link, each to export 1 road direct current sampled signal;And pass through optical fiber Reach DSP-FPGA sampling plates.
The direct current sampled signal is respectively outputted to two pieces of direct current sampling plates, i.e. the first direct current sampling plate and the second direct current is adopted Model;First direct current sampling plate and the second direct current sampling plate by direct current sampled signal after level conversion by being sent to DSP-FPGA Sampling plate.
The DSP control panels include electric power management circuit, level shifting circuit, CAN communication module, JTAG debugging interfaces electricity Road, LED display circuit and row's needle interface.
The DSP control panels protect system and DSP Triggering Control Systems to be attached by arranging needle interface with DSP;Wherein, Motherboard CAN bus is connected to by CAN bus;Adopted by 16 bit data bus, 8 bit address buses, 9 controlling bus and DSP The DSP-FPGA of sample system communicates;It is attached by 9 input ports and 9 output ports with DSP I/O plates.
Described device includes voltage to frequency converter, direct current sampling system and DSP control system;The voltage to frequency convert Device connection direct current sampling system connects DSP control system with direct current sampling system;The voltage to frequency converter, for that will input Voltage signal be converted into frequency signal.
The direct current sampling system, by chain link sampling voltage-frequency change-over panel, direct current sampling plate, common group of DSP-FPGA sampling plates Into;Direct current sampling system 12 chain structures per being mutually made of, and every chain structure has 1 piece of chain link sampling voltage-frequency change-over panel, altogether A, B, C three-phase.
The invention has the advantages that the present invention frequency signal is converted electrical signals to by voltage-frequency switch technology (can be with It is considered as digital signal), and carried out data transmission by optical-fibre communications mode.The capacitance voltage come out from direct current sampling plate is with optical fiber The form of signal is connected to Optical fibre sampling plate, and Optical fibre sampling plate is translated into electric signal, after line level of going forward side by side conversion, is transferred to DSP-FPGA sampling plates.When dsp chip sends chip selection signal, FPGA reads and transmits the chip selection signal of corresponding clock cycle, And in each DSP-CLK rising edge clocks, dsp chip reads the data on FPGA.Dsp chip batch reads 636 data 4.24us is only needed, average each data acquisition reading speed is only 6.67ns, and acquisition speed is very fast, while FPGA can It is extensive to complete three-phase voltage current, threephase load electric current, three-phase output current, reference voltage and 36 road d. c. voltage signals To dsp chip, the large-scale parallel data sampling control sequential thus formed can greatly improve parallel data and adopt parallel transmission Collect transmission speed and capacity.Can pass large-scale parallel data sampling control technology using DSP-FPGA controlling of sampling sequential There is very big lifting in terms of defeated speed, capacity and security.
Brief description of the drawings
Fig. 1 is the systematic sampling voltage-frequency flow path switch figure of the present invention;
Fig. 2 is the direct current sampling system flow chart of the present invention;
Fig. 3 is the dsp system schematic diagram of the present invention;
Fig. 4 is the DSP-FPGA sampling time sequence figures of the present invention.
Embodiment
The embodiment of the present invention is as shown in the figure.
A kind of method of the large-scale parallel data sampling control sequential based on DSP-FPGA of the present embodiment, passes through voltage frequency Rate converter, direct current sampling system and DSP control system are realized.The voltage to frequency converter changes the voltage signal of input Systematic sampling voltage-frequency conversion is carried out into frequency signal, and frequency signal is sent to the systematic sampling plate of DSP sampling systems;Controlled from DSP The capacitance voltage that the direct current sampling plate of system processed comes out is connected to Optical fibre sampling plate in the form of fiber-optic signal, and Optical fibre sampling plate will It is converted into electric signal, after line level of going forward side by side conversion, is transferred to DSP-FPGA sampling plates;When dsp chip sends chip selection signal, FPGA reads and transmits the chip selection signal of corresponding clock cycle, and in each DSP-CLK rising edge clocks, dsp chip is read Data on FPGA;At the same time FPGA can complete three-phase voltage current, threephase load electric current, three-phase output current, reference voltage with And 36 road d. c. voltage signal large-scale parallel be transferred to dsp chip, be achieved in large-scale parallel data sampling control sequential.
The large-scale parallel data sampling control sequential of the present embodiment combination DSP and FPGA technology can realize large-scale data Batch parallel sampling, and controlling of sampling security reliability is higher, is relatively adapted to epoch technical need.
Fig. 1 show the systematic sampling voltage-frequency flow path switch figure of the present invention.The voltage signal of input is turned by electric voltage frequency Parallel operation is converted into frequency signal;Systematic sampling plate collection three-phase system voltage, three-phase output current, threephase load electric current and ginseng Examine voltage totally 10 road signal;Through Optical fibre sampling plate, to DSP-FPGA sampling plates.
Fig. 2 is the direct current sampling system flow chart of the present invention.As shown in Fig. 2, direct current sampling system samples voltage-frequency by chain link Change-over panel, direct current sampling plate, DSP-FPGA sampling plates collectively constitute.Direct current sampling system is made of per phase 12 chain structures, Every chain structure has 1 piece of chain link sampling voltage-frequency change-over panel, common A, B, C three-phase.Totally 36 pieces of chain link sampling voltage-frequency change-over panel.Every piece Chain link sampling voltage-frequency change-over panel is located at the inside of chain link, each to export 1 road direct current sampled signal.36 pieces of chain links sample voltage-frequency change-over panel 36 road direct current sampled signals are exported altogether, and master controller is reached by optical fiber.36 road direct current sampled signals are respectively outputted to two pieces directly Flow sampling plate (the first direct current sampling plate and the second direct current sampling plate).First direct current sampling plate and the second direct current sampling plate pass through electricity Flat turn changes 36 road direct current sampled signals of Hou Jiang and is sent to DSP-FPGA sampling plates, is completed certainly after DSP-FPGA sampling plate receive informations Body works.
Fig. 3 is the DSP control system schematic diagram of the present invention.As shown in figure 3, DSP control system is adopted by DSP control panels, DSP Other plate three parts of model, DSP are formed.DSP sampling plates are DSP sampling systems;Other plates of DSP include DSP protection systems and DSP Triggering Control System.The 26S Proteasome Structure and Function of DSP control panels and DSP sampling plates is as follows:
(1) DSP control panels include electric power management circuit, level shifting circuit, CAN communication module, JTAG debugging interfaces electricity Road, DSP control panels LED display circuit and row's needle interface.
DSP control panels are attached by arranging needle interface with other systems, wherein, motherboard CAN is connected to by CAN bus Bus, is communicated with the FPGA of sampling system by 16 bit data bus, 8 bit address buses, 9 controlling bus, passes through 9 Input port and 9 output ports are attached with DSP I/O plates.
(2) DSP sampling plates are made of DSP-FPGA sampling plates, direct current sampling plate and systematic sampling plate.
DSP samplings FPGA is responsible for defeated to 36 road DC voltage Udc, three-phase system voltage US, threephase load electric current IL, three-phase Go out electric current IO and la tension de reference Uref est is sampled, and transfer data to DSP control panels.
Every piece of direct current sampling plate can gather 18 road DC voltages, and two pieces of sampling plates gather 36 road DC voltages altogether.From direct current The capacitance voltage that sampling plate comes out is connected to Optical fibre sampling plate in the form of fiber-optic signal, and Optical fibre sampling plate is translated into telecommunications Number, after line level of going forward side by side conversion, pin is arranged by motherboard and is transferred to DSP-FPGA sampling plates.
Systematic sampling plate collection three-phase system voltage, three-phase output current, threephase load electric current and reference voltage totally 10 Road signal.Systematic sampling plate is transmitted to from main circuit, DSP cores are transferred to by motherboard after converted equally in the form of fiber-optic signal Piece samples FPGA.
Fig. 4 is the DSP-FPGA sampling time sequence figures of the present invention.As shown in figure 4, DSP-FPGA sampling time sequences are described in detail FPGA carries out the process of data sampling and data transfer.
The present embodiment DSP-FPGA data sampling control sequentials are as follows:
(1) dsp chip sends the chip selection signal that CS2 and CS1 is 01, chooses sampling FPGA;
(2) FPGA sends the ready signal that Ready 2 and Ready1 is 01, represents that FPGA is idle, can carry out data sampling; CSFlag puts 1;
(3) FPGA reads and uploads the system voltage voltage-frequency signal pulse number of each CLK_100us clock cycle, is each The DC voltage voltage-frequency signal pulse number of Clk_20ms clock cycle, and in each DSP_CLK rising edge clocks, dsp chip Read the data that FPGA is uploaded;
(4) continue by step 3 by 36 road DC voltages, load current, output current, reference voltage is sent to dsp chip;
(5) CS2CS1 is put 11 by dsp chip, cancels chip selection signal;
(6) Ready2 and Ready1 are put 11 by FPGA, into busy condition;
(7) sampling terminates.
Wherein, CS2, CS1, Ready2, Ready1, CSFlag, Clk, DSP_CLK refer to DSP and FPGA between the two Various pin interfaces.

Claims (8)

  1. A kind of 1. method of the large-scale parallel data sampling control sequential based on DSP-FPGA, it is characterised in that the method Parallel data is carried out by DSP control system and direct current sampling system by DSP-FPGA sampling plates to sample, DSP control system passes through Three-phase system voltage, three-phase output current, threephase load electric current and reference voltage are gathered, from main circuit in the form of fiber-optic signal It is transmitted to systematic sampling plate, DSP-FPGA sampling plates is transferred to by motherboard after converted;Direct current sampling system passes through chain type knot Voltage signal is converted into frequency signal by the sampling voltage-frequency change-over panel of structure, and is believed the frequency after processing by optical-fibre communications mode Number it is transferred to DSP-FPGA sampling plates;The DSP-FPGA sampling plates controlling of sampling sequential is as follows:
    (1) dsp chip sends the chip selection signal that CS2 and CS1 is 01, chooses sampling FPGA;
    (2) FPGA sends ready signal that Ready2 and Ready1 is 01 to dsp chip, represents that FPGA is idle, can carry out data Sampling;Dsp chip CSFlag puts 1;
    (3) FPGA reads and uploads system voltage voltage-frequency signal pulse number, each Clk_ of each CLK_100us clock cycle The DC voltage voltage-frequency signal pulse number of 20ms clock cycle is to dsp chip, and in each DSP_CLK rising edge clocks, DSP Chip reads the data that FPGA is uploaded;
    (4) step (3) is pressed, FPGA continues 36 road DC voltages, load current, output current, and reference voltage is sent to DSP cores Piece;
    (5) CS2CS1 is put 11 by dsp chip, cancels chip selection signal;
    (6) Ready2 and Ready1 are put 11 by FPGA, into busy condition;
    (7) sampling terminates.
  2. 2. a kind of method of large-scale parallel data sampling control sequential based on DSP-FPGA according to claim 1, It is characterized in that, the DSP control system includes DSP control panels, DSP sampling systems, DSP protection systems and DSP triggering controls System;The DSP control panels connect DSP sampling systems by controlling bus, DSP protects system and DSP Triggering Control Systems;Institute DSP sampling systems are stated to be made of DSP-FPGA sampling plates, direct current sampling plate and systematic sampling plate.
  3. 3. a kind of large-scale parallel data sampling control sequential method based on DSP-FPGA according to claim 1, its It is characterized in that, it is described to give the frequency signal transmission after processing to DSP-FPGA sampling plates by optical-fibre communications mode, refer to from direct current The capacitance voltage that the direct current sampling plate of sampling system comes out is connected to Optical fibre sampling plate, Optical fibre sampling plate in the form of fiber-optic signal Electric signal is translated into, after line level of going forward side by side conversion, is transferred to the DSP-FPGA sampling plates of direct current sampling system.
  4. 4. a kind of method of large-scale parallel data sampling control sequential based on DSP-FPGA according to claim 1, It is characterized in that, the direct current sampling system includes chain link sampling voltage-frequency change-over panel, direct current sampling plate and DSP-FPGA sampling plates; The direct current sampling system 12 chain structures per being mutually made of, and every chain structure has 1 piece of chain link sampling voltage-frequency change-over panel, altogether A, B, C three-phase;Every piece of chain link sampling voltage-frequency change-over panel is located at the inside of chain link, each to export 1 road direct current sampled signal;And pass through light Fibre reaches DSP-FPGA sampling plates.
  5. 5. a kind of method of large-scale parallel data sampling control sequential based on DSP-FPGA according to claim 4, It is characterized in that, the direct current sampled signal is respectively outputted to two pieces of direct current sampling plates, i.e. the first direct current sampling plate and second straight Flow sampling plate;First direct current sampling plate and the second direct current sampling plate by direct current sampled signal after level conversion by being sent to DSP- FPGA sampling plates.
  6. 6. a kind of method of large-scale parallel data sampling control sequential based on DSP-FPGA according to claim 2, Debug and connect it is characterized in that, the DSP control panels include electric power management circuit, level shifting circuit, CAN communication module, JTAG Mouth circuit, LED display circuit and row's needle interface;
    The DSP control panels protect system and DSP Triggering Control Systems to be attached by arranging needle interface with DSP;Wherein, pass through CAN bus is connected to motherboard CAN bus;Sampled by 16 bit data bus, 8 bit address buses, 9 controlling bus and DSP and be The DSP-FPGA of system communicates;It is attached by 9 input ports and 9 output ports with DSP I/O plates.
  7. A kind of 7. device of the large-scale parallel data sampling control sequential based on DSP-FPGA, it is characterised in that described device Including voltage to frequency converter, direct current sampling system and DSP control system;The voltage to frequency converter connection direct current sampling system System connects DSP control system with direct current sampling system;The voltage to frequency converter, for the voltage signal of input to be converted into Frequency signal.
  8. 8. a kind of device of large-scale parallel data sampling control sequential based on DSP-FPGA according to claim 7, It is characterized in that, the direct current sampling system, is total to by chain link sampling voltage-frequency change-over panel, direct current sampling plate, DSP-FPGA sampling plates With composition;For direct current sampling system per being mutually made of 12 chain structures, every chain structure has 1 piece of chain link sampling voltage-frequency conversion Plate, common A, B, C three-phase.
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