CN107993954B - Method for detecting bottom defect of hard mask etching - Google Patents
Method for detecting bottom defect of hard mask etching Download PDFInfo
- Publication number
- CN107993954B CN107993954B CN201711184345.7A CN201711184345A CN107993954B CN 107993954 B CN107993954 B CN 107993954B CN 201711184345 A CN201711184345 A CN 201711184345A CN 107993954 B CN107993954 B CN 107993954B
- Authority
- CN
- China
- Prior art keywords
- hard mask
- etching
- medium
- defect
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention relates to a method for detecting bottom defects of hard mask etching, which comprises the following steps: after the hard mask is etched to form a hard mask pore channel, continuously etching the wafer for a period of time, and forming a medium groove on the surface of the lower-layer medium at a position corresponding to the hard mask pore channel so as to ensure that the etching process has a high selection ratio to the hard mask; removing the hard mask, and remaining the lower medium with the medium groove on the upper surface; the upper surface of the lower layer dielectric with the dielectric trench is inspected. The inspection method of the invention can accurately and visually reflect the problems existing in the hard mask etching, is convenient for timely and accurately improving the process conditions, and lays a good foundation for the subsequent processing procedure.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing process, in particular to a method for detecting bottom defects of hard mask etching.
Background
In the preparation process of the 3DNAND flash memory, an upper hard mask needs to be etched before deep hole etching is carried out, after the hard mask is etched, whether a pore channel is completely opened or not, namely whether the bottom of the pore channel is contacted with a lower medium or not, whether subsequent deep hole etching can be carried out or not is determined, and meanwhile, the uniformity of the pore diameter at the bottom of the pore channel of the hard mask and the roundness of the pore can also directly influence the appearance of the deep hole etching. Therefore, the inspection of the defect problem of the etching bottom of the hard mask has important significance for the subsequent deep hole etching.
In the existing deep hole etching process, the scanning and observation of the defect problem of the process are emphasized after the deep hole etching is finished. However, if a defect problem related to etching is found after deep hole etching, it is often impossible to directly determine whether the defect is caused by hard mask etching or subsequent deep hole etching, and the defect needs to be checked gradually from the beginning, thereby slowing down the progress of process development.
The defects existing in the hard mask etching are considered to be important, but some problems exist at the same time. On one hand, although defects existing on the etching surface of the scanning hard mask are easy, whether the subsequent deep hole etching is influenced or not cannot be intuitively reflected, and the reference value of defect results is not high; on the other hand, whether the bottom of the hard mask etching is completely opened or not and the uniformity of the aperture can directly influence the result of deep hole etching, the reference significance of the result of the bottom defect is large, but because the hard mask is used as a barrier layer of deep hole etching, the depth-to-width ratio of the hard mask etching is also high, and therefore certain difficulty exists in directly scanning and observing the bottom defect.
Disclosure of Invention
The invention aims to solve at least one of the problems, and provides a method for detecting the bottom defect of the hard mask etching, which can comprehensively examine the problems and hidden dangers existing after the hard mask etching, provide a good foundation for the subsequent processing and shorten the process research and development period.
The invention provides a method for detecting bottom defects of hard mask etching, which comprises the following steps:
after the hard mask etching is carried out on the wafer to form a hard mask pore channel, the wafer is continuously etched for a period of time, a medium groove is formed on the surface of the lower medium below the hard mask at a position corresponding to the hard mask pore channel, and the high selection ratio of the etching process to the hard mask is ensured;
removing the hard mask, and remaining the lower medium with the medium groove on the upper surface;
the upper surface of the lower layer dielectric with the dielectric trench is inspected.
Wherein in the step of adding etching, the time of adding etching is 1-200 seconds.
Wherein in the etching step, the etching gas is C4F8、C3F6、CH2F2And CF4With O2The flow rate of the etching gas is 1-100 standard milliliters/minute, the etching temperature is 10-200 ℃, and the pressure is 1-100 millitorr.
The method also comprises a step of removing impurities from the lower medium by peracid after the step of removing the hard mask and before the step of testing, so as to ensure that the acid has a high selection ratio to the lower medium.
Wherein the time for removing impurities by peracid is 1-10 hours.
The inspection step comprises the steps of measuring the aperture of the medium groove by using a measuring machine, and inspecting the defect of the surface with the medium groove by using a defect scanning table.
The invention has the following beneficial effects:
1. the method for detecting the bottom defect of the hard mask etching can accurately and visually reflect the problems of the hard mask etching, and is simple and convenient to operate.
2. The method for detecting the bottom defect of the hard mask etching can find the problems of the hard mask etching in time, is convenient for improving the process conditions in time and lays a good foundation for the subsequent processing procedure.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 shows a flow chart of a method for inspecting a hard mask etched bottom defect according to an embodiment of the invention.
FIG. 2 illustrates a cross-section of a wafer before hard mask etching according to an embodiment of the present invention;
FIG. 3 illustrates a cross-section of a wafer after hard mask etching according to an embodiment of the present invention;
FIGS. 4 a-4 b are structure flow diagrams illustrating a method for inspecting a hard mask etched bottom defect according to an embodiment of the present invention;
wherein, 1, lower layer medium; 2. a hard mask; 3. photoresist; 20. a hard mask tunnel; 10 dielectric trenches.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The basic idea of the invention is that after the hard mask etching is finished, the wafer is continuously etched for a period of time, so that a medium groove corresponding to the position of the hard mask pore passage is formed on the upper surface of the lower medium. The etching of the hard mask is stopped due to factors such as blockage, namely, if the hard mask pore channel cannot be completely opened, the etching cannot be carried out, so that the upper surface of the lower medium cannot form a pattern; and if the etching bottom of the hard mask is completely opened but the aperture is smaller, the aperture of the graph formed on the upper surface of the lower medium by etching is correspondingly smaller, so that the medium groove formed on the upper surface of the lower medium by etching can basically and truly reflect the bottom appearance of the hard mask pore channel, and the bottom appearance defect of the hard mask pore channel can be known by inspecting the upper surface of the lower medium with the medium groove.
In deep hole etching, in order to ensure that an enough mask can image a photoresist pattern on a bottom silicon wafer, a mask with a certain thickness and strong hardness can be grown before the photoresist is laid to serve as a barrier layer for subsequent deep hole etching, and generally, in order to effectively control the aperture size and the cross-sectional morphology of a deep hole, the hard mask etching and the deep hole etching are carried out in two steps. As shown in fig. 2 and fig. 3, the etching of the hard mask specifically includes laying a photoresist layer 3 on the surface of the hard mask layer 2 on the underlying dielectric 1, performing hard mask etching, and forming hard mask channels 20.
Since the shape of the hard mask pore canal 20 is crucial to the subsequent deep hole etching process, the bottom of the hard mask pore canal 20 needs to be inspected, and the technical scheme of the invention is a novel process for the inspection.
As shown in fig. 1, a method for inspecting a bottom defect of a hard mask etching includes the following steps: after the hard mask etching is carried out on the wafer to form a hard mask pore channel, the wafer is continuously etched for a period of time, a medium groove is formed on the surface of the lower medium below the hard mask at a position corresponding to the hard mask pore channel, and the high selection ratio of the etching process to the hard mask is ensured; removing the hard mask, and remaining the lower medium with the medium groove on the upper surface; the upper surface of the lower layer dielectric with the dielectric trench is inspected.
The technical solution provided by this embodiment will be specifically explained by way of specific examples with reference to fig. 4a to 4b, where fig. 4a and 4b are partial structural flow charts of the inspection method of the present application, and fig. 4a and 4b respectively correspond to structural changes of different steps.
As shown in fig. 4a, which corresponds to the step of etching in fig. 1. The method comprises the following steps: after the hard mask etching is carried out on the wafer, the wafer is continuously etched for a period of time, a medium groove 10 is formed on the upper surface of the lower-layer medium 1, and in the etching process, the high selection ratio of the etching process to the hard mask 2 is ensured, namely, the etching effect on the hard mask 2 is not obvious, and the etching effect on the lower-layer medium 1 is obvious. Due to the high selectivity and the short time of the etching process used, the top and the sidewalls of the hard mask via are not substantially damaged when forming the dielectric trench 10.
The hard mask is typically a hard material selected from carbon-based materials and the underlying dielectric is silicon dioxide, in which case the etching gas used may be C4F8、C3F6、CH2F2And CF4With O2The flow range of the etching gas of the doped mixed gas is 1-100 standard milliliters per minute, the etching temperature is 10-200 ℃, the pressure is 1-100 millitorr, the adding etching time is 1-200 seconds, and the adding etching conditions can ensure that the hard mask channel is not damaged to a large extent on the premise of forming a sufficiently clear medium groove. The optimum etching time in the above embodiment is 60 seconds.
After the etching is completed, the hard mask 2 is removed to expose the dielectric trench 10, as shown in fig. 4b, which corresponds to the step of removing the hard mask in fig. 1. The present invention uses oxygen atoms generated by a remote plasma to strip a hard mask from an underlying dielectric.
In addition, the inspection method also comprises a step of inspecting the upper surface of the lower medium with the medium groove, and the step specifically comprises the steps of observing the upper surface of the lower medium on a scanning electron microscope measuring machine (CD-SEM), measuring the size of the aperture, establishing a required defect scanning program by using a defect scanning machine (BFI ﹠ Revie-SEM), and comprehensively inspecting the defect problem existing after the hard mask of the wafer is etched.
By utilizing the defect scanning machine, different scanning programs can be established according to needs, defect types (such as large and small holes, figure loss and the like) are classified, and respective occupation ratios are output, so that the defect scanning machine is the most accurate and effective means for inspecting the defect problem.
The method for detecting the low-temperature oxidation-resistant lower layer dielectric further comprises a step of removing impurities from the lower layer dielectric by peracid after the step of removing the hard mask and before the step of detecting, wherein the acid used in the step has high selection ratio to the lower layer dielectric, namely the acid has strong corrosion action on the hard mask and has no or slight corrosion action on the lower layer dielectric.
Taking a hard material with a hard mask as a carbon element as a main part and a silicon dioxide wafer as a material of a lower medium as an example, selecting a composite acid of sulfuric acid and hydrogen peroxide to clean the upper surface of the lower medium, wherein the use concentration of the composite acid is 5:1, and the composite acid with the concentration can ensure that the hard mask residues are removed completely while the upper surface appearance of the lower medium is not damaged, namely, the interference of the residues is reduced to the minimum on the premise of not influencing the scanning result, so that the scanning result is more accurate.
According to the invention, the pattern at the bottom of the hard mask is transferred to the lower-layer medium, and then the defect problem existing in the pattern on the upper surface of the lower-layer medium is inspected by using the measuring machine and the defect scanning machine, so that the bottom defect problem of hard mask etching is reflected more intuitively. The invention provides a simple, convenient and effective method for detecting the bottom defect problem, which is convenient for improving the process conditions in time and lays a good foundation for the subsequent process.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (4)
1. The method for detecting the bottom defect of the hard mask etching is characterized by comprising the following steps of:
after the hard mask etching is carried out on the wafer to form a hard mask pore channel, the wafer is continuously etched for a period of time, a medium groove is formed on the surface of the lower medium below the hard mask at a position corresponding to the hard mask pore channel, and the high selection ratio of the etching process to the hard mask is ensured;
removing the hard mask, and remaining the lower medium with the medium groove on the upper surface;
inspecting the upper surface of the lower layer medium with the medium grooves;
in the etching step, the etching gas is C4F8、C3F6、CH2F2And CF4With O2The flow rate of the etching gas is 1-100 standard milliliters per minute, the etching temperature is 10-200 ℃, and the pressure is 1-100 millitorr;
the inspection step comprises the steps of measuring the aperture of the medium groove by using a measuring machine, and inspecting the defect of the surface with the medium groove by using a defect scanning platform.
2. The inspection method of claim 1,
in the step of adding etching, the time of adding etching is 1-200 seconds.
3. The inspection method of claim 1,
the method also includes a step of acid stripping the underlying dielectric after the step of removing the hard mask and before the step of inspecting the underlying dielectric, the acid used having a high selectivity ratio to the underlying dielectric.
4. The inspection method of claim 3,
the time for removing impurities by peracid is 1-10 hours.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711184345.7A CN107993954B (en) | 2017-11-23 | 2017-11-23 | Method for detecting bottom defect of hard mask etching |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711184345.7A CN107993954B (en) | 2017-11-23 | 2017-11-23 | Method for detecting bottom defect of hard mask etching |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107993954A CN107993954A (en) | 2018-05-04 |
| CN107993954B true CN107993954B (en) | 2020-03-13 |
Family
ID=62032931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711184345.7A Active CN107993954B (en) | 2017-11-23 | 2017-11-23 | Method for detecting bottom defect of hard mask etching |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107993954B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101441996A (en) * | 2007-11-21 | 2009-05-27 | 中芯国际集成电路制造(上海)有限公司 | Method for forming and etching hard mask layer |
| CN102339747A (en) * | 2010-07-22 | 2012-02-01 | 上海华虹Nec电子有限公司 | Zero scale forming method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3698904B2 (en) * | 1999-01-11 | 2005-09-21 | 沖電気工業株式会社 | Semiconductor evaluation method and defect position specifying apparatus |
-
2017
- 2017-11-23 CN CN201711184345.7A patent/CN107993954B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101441996A (en) * | 2007-11-21 | 2009-05-27 | 中芯国际集成电路制造(上海)有限公司 | Method for forming and etching hard mask layer |
| CN102339747A (en) * | 2010-07-22 | 2012-02-01 | 上海华虹Nec电子有限公司 | Zero scale forming method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107993954A (en) | 2018-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104078343A (en) | Failure analysis method for gate oxide defect original appearance | |
| JP2011124354A (en) | Inspection method of soi wafer | |
| CN110211919B (en) | Method for forming shallow trench isolation structure and method for forming semiconductor device | |
| US7115426B2 (en) | Method and apparatus for addressing thickness variations of a trench floor formed in a semiconductor substrate | |
| CN107968058B (en) | Measuring and representing method for deep hole etching bottom silicon substrate appearance | |
| US20200066538A1 (en) | Methods of enhancing surface topography on a substrate for inspection | |
| JP3753382B2 (en) | Method for measuring crystal defects in thin Si / SiGe bilayers | |
| CN107993954B (en) | Method for detecting bottom defect of hard mask etching | |
| US6645781B1 (en) | Method to determine a complete etch in integrated devices | |
| CN100499037C (en) | Through-hole etching method | |
| JP2008028178A (en) | Evaluation method of single crystal substrate | |
| US7745236B2 (en) | Floating gate process methodology | |
| CN103822812B (en) | The method for making of semiconducter device testing sample | |
| JP5518637B2 (en) | How to identify the depth of occurrence of dislocations | |
| CN111323443B (en) | SONO etching sample preparation and detection method | |
| JP2007194422A (en) | Test pattern wafer for defect inspecting device, its manufacturing method, and evaluation method of defect inspection apparatus using it | |
| TWI276832B (en) | Method of sample preparation for scanning capacitance microscope and measuring method thereby | |
| JP2001208531A (en) | Method of measuring film thickness distribution | |
| US20140234993A1 (en) | Sti cmp under polish monitoring | |
| CN109560002A (en) | The monitoring method of silicon wafer warpage degree | |
| CN101752286B (en) | Method for making shallow groove | |
| US20240105523A1 (en) | Method for testing the stress robustness of a semiconductor substrate | |
| US20070004152A1 (en) | Method for fabricating semiconductor device with step gated asymmetric recess | |
| CN108807399B (en) | Preparation method of flash memory | |
| Gong et al. | Failure Analysis of Single-Bit Charge Loss after Stress and Studies on Silicon Dopant Profile |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |