CN107993614B

CN107993614B - Method and system for extracting circuit parameters from pixel circuits

Info

Publication number: CN107993614B
Application number: CN201711164105.0A
Authority: CN
Inventors: 戈尔拉玛瑞扎·恰吉; 里基·依克·黑·奈根; 尼诺·扎西洛维奇; 亚沙尔·阿齐兹
Original assignee: Ignis Innovation Inc
Current assignee: Ignis Innovation Inc
Priority date: 2013-03-15
Filing date: 2014-03-13
Publication date: 2020-01-17
Anticipated expiration: 2034-03-13
Also published as: CN105210139B; CN105210139A; WO2014141156A1; CN107993614A; DE112014001424T5

Abstract

The invention discloses a method for extracting circuit parameters from a pixel circuit, the pixel circuit comprising a light emitting device, a drive device for providing a programmable drive current to the light emitting device, a programming input and a storage device for storing a programming signal, the method comprising: turning on the driving device so that a voltage of the light emitting device rises to a level higher than an on voltage of the light emitting device, turning off the driving device so that the voltage of the light emitting device is discharged through the light emitting device until the light emitting device is turned off, and reading the voltage across the light emitting device while the light emitting device is turned off. With the method and system of the present invention, parameters in the pixel drive circuit can be extracted with as few components as possible to maximize the pixel aperture.

Description

Method and system for extracting circuit parameters from pixel circuits

The present application is a divisional application of the '201480027893.7 patent application having an application date of 2014, 3/13/10 entitled system and method for extracting parameters in an active matrix organic light emitting device display'.

Technical Field

The present invention relates generally to Active Matrix Organic Light Emitting Device (AMOLED) displays and in particular to extraction of parameters of threshold and mobility factors in pixel circuits and light emitting devices in drivers for such displays.

Background

Currently, the advantages of active matrix organic light emitting device ("AMOLED") displays are being introduced. Advantages of such displays over conventional liquid crystal displays include low power consumption, flexibility of manufacture, and faster refresh rates. Compared to conventional liquid crystal displays, AMOLED displays have no backlight, and thus each pixel is composed of different color OLEDs that emit light independently. OLEDs emit light based on current supplied through respective drive transistors that are controlled by respective programming voltages. The power consumption of each pixel is related to the amount of light generated in that pixel.

The quality of the output in OLED-based pixels is affected by the performance of the drive transistor, which is typically made of materials including, but not limited to, amorphous silicon, polysilicon, or metal oxides, as well as the OLED itself. In particular, as the pixel ages, both the threshold voltage and the mobility of the drive transistor change. In order to maintain image quality, variations in these parameters must be compensated for by adjusting the programming voltage. In order to implement this process, these parameters must be extracted from the drive circuit. The added components to extract these parameters in a simple drive circuit require more space on the display substrate for the drive circuit, thus reducing the size of the aperture or area from which light is emitted from the OLED.

When biased at saturation, the I-V characteristics of a thin film drive transistor depend on the mobility and threshold voltage, which are functions of the materials used to fabricate the transistor. Thus, different thin film transistor devices disposed across the display panel may exhibit inconsistent behavior due to aging and process variations in mobility and threshold voltage. Thus, for a constant voltage, each device may have a different drain current. In an extreme example, one device may have a low threshold voltage and low mobility, and conversely, a second device may have a high threshold voltage and high mobility.

Thus, the non-uniformity parameter (i.e., threshold voltage V) for the drive TFT and OLED while using only few electronic components to maintain the desired aperture_thAnd mobility μ) becomes challenging. It is desirable to extract such parameters in the drive circuitry of an OLED pixel with as few components as possible to maximize the pixel aperture.

Disclosure of Invention

A method for extracting a circuit parameter from a pixel circuit, the pixel circuit comprising a light emitting device, a drive device for providing a programmable drive current to the light emitting device, a programming input, and a storage device for storing a programming signal, the method comprising: turning on the driving device such that a voltage of the light emitting device rises to a level higher than an on voltage of the light emitting device; turning off the driving device so that a voltage of the light emitting device is discharged through the light emitting device until the light emitting device is turned off; and reading a voltage across the light emitting device while the light emitting device is off.

A system for extracting a circuit parameter from a pixel circuit, the pixel circuit including a light emitting device, a drive device for providing a programmable drive current to the light emitting device, a programming input, and a storage device for storing a programming signal, the system comprising: a controller connected to the pixel circuit and providing control input signals to the pixel circuit in a predetermined sequence to produce output voltage values that are a function of parameters of the pixel circuit, the sequence comprising: turning off the driving device and supplying a predetermined voltage from an external source to the light emitting device; discharging the light emitting device until the light emitting device is turned off; and reading a voltage across the light emitting device while the light emitting device is off.

A system for extracting a circuit parameter from a pixel circuit, the pixel circuit including a light emitting device, a drive device for providing a programmable drive current to the light emitting device, a programming input, and a storage device for storing a programming signal, the system comprising: a controller connected to the pixel circuit and providing control input signals to the pixel circuit in a predetermined sequence to produce output voltage values that are a function of parameters of the pixel circuit, the sequence comprising: turning on the driving device such that a voltage of the light emitting device rises to a level higher than an on voltage of the light emitting device; turning off the driving device so that a voltage across the light emitting device is discharged through the light emitting device until the light emitting device is turned off; and reading a voltage across the light emitting device while the light emitting device is off.

A system for extracting a circuit parameter from a pixel circuit, the pixel circuit including a light emitting device, a drive transistor having a gate terminal, a source terminal, and a drain terminal for providing a programmable drive current to the light emitting device, a programming input, and a storage device for storing a programming signal, the system comprising: a controller connected to the pixel circuit and providing control input signals to the pixel circuit in a predetermined sequence to produce output voltage values that are a function of parameters of the pixel circuit, the sequence comprising: turning on the drive device and measuring a current and a voltage of the drive transistor while changing a voltage between a gate and a source or between a gate and a drain of the drive transistor to operate the drive transistor in a linear region during a first time interval and in a saturation region during a second time interval; and extracting a parameter of the light emitting device according to a relationship of current and voltage measured from the driving transistor operated in the above two regions.

A method for extracting a circuit parameter from a pixel circuit, the pixel circuit comprising: a light emitting device, a drive transistor having a gate terminal, a source terminal and a drain terminal for providing a programmable drive current to the light emitting device, a programming input and a storage device for storing a programming signal, the method comprising: turning on the drive device and measuring a current and a voltage of the drive transistor while changing a voltage between a gate and a source or between a gate and a drain of the drive transistor to operate the drive transistor in a linear region during a first time interval and in a saturation region during a second time interval; and extracting a parameter of the light emitting device according to a relationship of current and voltage measured from the driving transistor operated in the above two regions.

The foregoing and other aspects and embodiments of the present invention will become apparent to those skilled in the art from the following detailed description of the various embodiments and/or aspects, which is to be read in connection with the accompanying drawings. The drawings will be briefly described below.

Drawings

The above and other advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings.

FIG. 1 is a block diagram of an AMOLED display with compensation control.

FIG. 2 is a circuit diagram of a data extraction circuit for a two transistor pixel in the AMOLED display in FIG. 1.

Fig. 3A is a signal timing diagram of signals applied to a data extraction circuit to extract the threshold voltage and mobility of the n-type drive transistor in fig. 2.

Fig. 3B is a signal timing diagram of signals applied to a data extraction circuit to extract a characteristic voltage of the OLED having the n-type driving transistor in fig. 2.

Fig. 3C is a signal timing diagram of signals applied to a data extraction circuit for direct reading to extract the threshold voltage of the n-type drive transistor in fig. 2.

Fig. 4A is a signal timing diagram of signals applied to a data extraction circuit to extract the threshold voltage and mobility of the p-type drive transistor in fig. 2.

Fig. 4B is a signal timing diagram of signals applied to a data extraction circuit to extract a characteristic voltage of the OLED in fig. 2 using a p-type driving transistor.

Fig. 4C is a signal timing diagram of signals applied to a data extraction circuit for direct reading to extract the threshold voltage of the p-type drive transistor in fig. 2.

Fig. 4D is a signal timing diagram of signals applied to a data extraction circuit to directly read the turn-on voltage of the OLED by using the n-type or p-type driving transistor in fig. 2.

Fig. 5 is a circuit diagram of a data extraction circuit for extracting parameters of the three-transistor drive circuit of one pixel in the AMOLED display in fig. 1.

Fig. 6A is a signal timing diagram of signals applied to a data extraction circuit to extract the threshold voltage and mobility of the driving transistor in fig. 5.

Fig. 6B is a signal timing diagram of signals applied to the data extraction circuit to extract the characteristic voltage of the OLED in fig. 5.

Fig. 6C is a signal timing diagram of signals applied to a data extraction circuit for direct reading to extract the threshold voltage of the driving transistor in fig. 5.

Fig. 6D is a signal timing diagram of signals applied to a data extraction circuit for direct reading to extract a characteristic voltage of the OLED in fig. 5.

FIG. 7 is a flow chart of an extraction cycle to read the characteristics of the drive transistors and OLEDs of the pixel circuits in an AMOLED display.

Fig. 8 is a flow chart of different parameter extraction cycles and final applications.

FIG. 9 is a block diagram and diagram of components of a data extraction system.

Fig. 10 is a signal timing chart of signals applied to a data extraction circuit to extract the threshold voltage and mobility of the drive transistor in the modification of the circuit in fig. 5.

Fig. 11 is a signal timing diagram of signals applied to the data extraction circuit to extract the characteristic voltage of the OLED in the modification of the circuit in fig. 5.

FIG. 12 is a circuit diagram of a data extraction circuit for reading pixel charge from the drive circuit of a pixel in the AMOLED display in FIG. 1, which is a schematic of a pixel circuit with current measurement capability.

Fig. 13 is a signal timing diagram of signals applied to the data extraction circuit in fig. 12 to read a pixel state by initializing a node from the outside.

Fig. 14 is a flowchart for reading the pixel state of the circuit in fig. 12 by initializing a node from the outside.

Fig. 15 is a signal timing chart of signals applied to the data extraction circuit in fig. 12 to read a pixel state by initializing a node from inside.

Fig. 16 is a flowchart for reading the pixel state of the circuit in fig. 12 by initializing the node from inside.

FIG. 17 is a circuit diagram of a pair of circuits used with a common monitor line for reading pixel charge from two different pixels in the AMOLED display in FIG. 1 and similar to the circuit in FIG. 12.

Fig. 18 is a signal timing chart of signals applied to the data extraction circuit in fig. 17 to read pixel charges when the monitor line is shared.

FIG. 19 is a flow chart for reading the pixel state of a pair of circuits similar to the circuit in FIG. 17 using a common monitor line.

Fig. 20A is a schematic circuit diagram of a deformed pixel circuit that provides access to internal nodes.

Fig. 20B is a timing diagram illustrating the operation of 14, which is a schematic diagram of the OLED display pixel circuit in fig. 20A with charge-based compensation readout capability.

Fig. 21 is a timing chart illustrating an operation of the pixel circuit in fig. 20A for realizing readout of parameters of the driving transistor.

Fig. 22 is a timing chart illustrating an operation of the pixel circuit in fig. 20A for achieving readout of parameters of the OLED.

Fig. 23 is a timing chart illustrating a deforming operation of the pixel circuit in fig. 20A for achieving readout of parameters of the OLED.

Fig. 24 is a schematic diagram of a pixel circuit with current measurement capability.

Fig. 25 is a schematic circuit diagram of a pixel circuit providing access to an internal node.

FIG. 26 is a schematic diagram of an OLED display pixel circuit with charge readout capability.

While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Detailed Description

Fig. 1 is an electronic display system 100, the system 100 having an active matrix area of a pixel array 102, wherein an n x m array of pixels 104 is arranged in rows and columns. For ease of illustration, only two rows and two columns are shown. Outside the active matrix area of the pixel array 102 is a peripheral area 106, and peripheral circuits for driving and controlling the pixel array 102 are disposed in the peripheral area 106. The peripheral circuits include an address or gate drive circuit 108, a data or source drive circuit 110, a controller 112, and an optional supply voltage (e.g., Vdd) driver 114. Controller 112 controls gate, source and

supply voltage drivers

108, 110 and 114. The gate driver 108 operates address or selection lines SEL [ i ], SEL [ i +1], etc., which correspond one-to-one to each row of pixels 104 in the pixel array 102, under the control of the controller 112. In the pixel sharing configuration described below, the gate or address drive circuit 108 may also selectively operate on global select lines GSEL [ j ] and/[ GSEL [ j ], which operate on multiple rows of pixels 104 of the pixel array 102 (e.g., every two rows of pixels 104). The source driving circuit 110 operates, under the control of the controller 112, voltage data lines Vdata [ k ] and Vdata [ k +1], etc., which correspond one-to-one to each column of pixels 104 in the pixel array 102. The voltage data line transmits voltage programming information indicating the luminance of each light emitting device in the pixel 104 to each pixel 104. The storage element (e.g., capacitor) in each pixel 104 stores the voltage programming information until the light emitting device is turned on for a light emitting or driving period. An optional supply voltage driver 114, under the control of controller 112, controls supply voltage (EL Vdd) lines that correspond one-to-one with rows or columns of pixels 104 in pixel array 102.

The display system 100 further includes a current supply and readout circuit 120 for reading out output data from data output lines VD [ k ] and VD [ k +1], etc., which correspond one-to-one to each column of pixels 104 in the pixel array 102.

It is well known that each pixel 104 in the display system 100 needs to be programmed with information indicative of the brightness of the light emitting device in the pixel 104. The frame defines a time period that includes: (i) a programming period or phase during which each pixel in the display system 100 is programmed with a programming voltage indicative of the brightness, and (ii) a driving or light-emitting period or phase during which the respective light-emitting devices in the respective pixels are turned on to emit light at a brightness commensurate with the programming voltage stored in the storage elements. Thus, a frame is one of many still images that make up a complete moving picture for display on the display system 100. The scheme for programming or driving the pixels has at least: line by line or frame by frame. In row-by-row programming, one row of pixels is programmed and then driven, and then the next row of pixels is programmed and driven. In frame-by-frame programming, the pixels of all rows in the display system 100 are programmed first and then immediately driven. Both schemes may employ a brief vertical blanking time at the beginning or end of each frame during which the pixels are neither programmed nor driven.

Components located outside of the pixel array 102 may be disposed in a peripheral region 106 around the pixel array 102 and on the same physical substrate as the pixel array 102. These components include a gate driver 108, a source driver 110, an optional supply voltage driver 114, and a current supply and sense circuit 120. Alternatively, some components in the peripheral region 106 may be disposed on the same substrate as the pixel array 102 and other components disposed on a different substrate, or all components in the peripheral region may be disposed on a different substrate than the substrate on which the pixel array 102 is disposed. The gate driver 108, the source driver 110, and the supply voltage driver 114 together constitute a display driving circuit. In some configurations, the display drive circuitry may include the gate driver 108 and the source driver 110, but not the supply voltage control 114.

When the bias is in saturation, the first order I-V characteristics of a Metal Oxide Semiconductor (MOS) transistor (thin film transistor in this example) are modeled as:

wherein, I_DIs a drain current, and V_GSIs the voltage difference applied between the gate and source terminals of the transistor. The thin film transistor devices provided throughout the display system 100 have mobility (μ) and threshold voltage (V) due to aging and process variations_th) The aspects exhibit inconsistent behavior. Thus, for a constant voltage difference V applied between the gate and the source_GSThe various transistors on the pixel array 102 may have different drain currents based on uncertain mobility and threshold voltage:

I_D(i,j)＝f(μ_i,j,V_thi,j)

where i and j are the coordinates (rows and columns) of the pixels in an n x m pixel array, such as pixel array 102 in fig. 1.

Fig. 2 illustrates a data extraction system 200 that includes a two transistor (2T) drive circuit 202 and a readout circuit 204. In a display system having 2T pixel circuits 104, supply voltage control 114 is optional. As shown in fig. 1, readout circuitry 204 is part of current supply and readout circuitry 120 and collects data from the columns of pixels 104. The readout circuit 204 includes a charge pump circuit 206 and a switch box circuit 208. The voltage source 210 provides a supply voltage to the drive circuit 202 through the switch box circuitry 208. The charge pump circuitry 206 and switch box circuitry 208 are disposed on the top or bottom side of the array 102, such as in the voltage driver 114 and current supply and sense circuitry 120 shown in FIG. 1. This is achieved either by direct fabrication on the same substrate as the pixel array 102 or by incorporating a microchip on the substrate or on a wire (flex) as a hybrid solution.

The driving circuit 202 includes a driving transistor 220, an organic light emitting device 222, a drain storage capacitor 224, a source storage capacitor 226, and a selection transistor 228. Supply line 212 provides the source voltage and a monitoring path (for readout circuit 204) to the columns of drive circuits, such as drive circuit 202. The select line input 230 is connected to the gate of the select transistor 228. The program data input 232 is connected to the gate of the drive transistor 220 through the select transistor 228. The drain of the driving transistor 220 is connected to the supply voltage line 212, and the source of the driving transistor 220 is connected to the OLED 222. Select transistor 228 controls the connection of program input 230 to the gate of drive transistor 220. The source storage capacitor 226 is connected between the gate and source of the driving transistor 220. The drain storage capacitor 224 is connected between the gate and the drain of the driving transistor 220. The OLED222 has a parasitic capacitance modeled as a capacitor 240. The supply voltage line 212 also has a parasitic capacitance modeled as a capacitor 242. The driving transistor 220 in this example is a thin film transistor made of amorphous silicon. Of course, other materials such as polysilicon or metal oxide may be used. Node 244 is a circuit node at which the source of drive transistor 220 and the anode of OLED222 are connected together. In this example, the driving transistor 220 is an n-type transistor. The system 200 may also replace the n-type drive transistor 220 with a p-type drive transistor, as will be explained below.

The readout circuit 204 includes a charge pump circuit 206 and a switch box circuit 208. The charge pump circuit 206 includes an amplifier 250 having a positive input and a negative input. The negative input of amplifier 250 is connected to capacitor 252 (C) in parallel with switch 254_int) The switch 254 is connected to the output of the amplifier 250 in a negative feedback loop. The switch 254(S4) is used to enable the capacitor 252C_intIn the pre-chargingAnd (5) stage discharge. The positive input of amplifier 250 is connected to a common mode voltage input 258 (VCM). The output 256 of the amplifier 250 indicates a number of extracted parameters of the drive transistor 220 and the OLED222, as will be explained below.

The switch box circuit 208 includes

several switches

260, 262, and 264(S1, S2, and S3) for conducting current to and from the pixel drive circuit 202. The switch 260(S1) is used to provide a discharge path to ground during the reset phase. The switch 262(S2) is used to provide a power supply connection during normal operation of the pixel 104 and during the integration phase of readout. The switch 264(S3) is used to isolate the charge pump circuit 206 from the supply line voltage 212 (VD).

As shown in fig. 2, the overall readout idea for the two transistor pixel drive circuit 202 for each pixel 104 comes from the fact that: the charge stored in the parasitic capacitance represented by capacitor 240 across OLED222 has useful information of the threshold voltage and mobility of drive transistor 220 and the turn-on voltage of OLED 222. Extracting these parameters can be used for a variety of applications. For example, these parameters may be used to modify the programming data for the pixels 104 to compensate for pixel variations and maintain image quality. These parameters may also be used to pre-age the pixel array 102. These parameters may also be used to evaluate the process yield of fabricating the pixel array 102.

Assume capacitor 240 (C)_OLED) Is initially discharged, capacitor 240 (C)_OLED) It takes time to charge to a voltage level that turns off the driving transistor 220. The voltage level is a function of the threshold voltage of drive transistor 220. Applied to the program data input 232 (V)_Data) Must be low enough to enable the OLED222 (V)_OLED) Is less than the turn-on threshold voltage of the OLED222 itself. Under such conditions, V_Data-V_OLEDIs the threshold voltage (V) of the driving transistor 220_th) Is a linear function of (a). To extract the mobility of a thin film transistor device such as drive transistor 220, the transient stability of the device, which is a function of threshold voltage and mobility, is considered. Assume a threshold between TFT devices such as drive transistor 220The voltage deviation is compensated for and the voltage at node 244 sampled at constant time intervals after the integration begins is only a function of the mobility of the TFT device, such as drive transistor 220.

Fig. 3A-3C are signal timing diagrams of control signals applied to the components shown in fig. 2 to extract parameters such as voltage threshold and mobility from the driving transistor 220 in the driving circuit 200 and to extract the turn-on voltage of the OLED222, assuming that the driving transistor 220 is an n-type transistor. These control signals may be applied by the controller 112 to the source driver 110, the gate driver 108, and the current supply and sensing circuit 120 in fig. 1. Fig. 3A shows a timing diagram of signals applied to the extraction circuit 200 to extract the threshold voltage and mobility from the driving transistor 220. FIG. 3A includes a signal 302 for the select input 230 of FIG. 2, a signal 304(φ) applied to the switch 260₁) Signal 306 (phi) for switch 262₂) Signal 308 (phi) for switch 264₃) Signal 310 (phi) for switch 254₄) A program voltage signal 312 for the program data input 232 of fig. 2, a voltage 314 at node 244 of fig. 2, and an output voltage signal 316 for the output 256 of amplifier 250 of fig. 2.

Fig. 3A shows four stages of the readout process: reset phase 320, integration phase 322, precharge phase 324, and read phase 326. The process begins by applying a high select signal 302 to the select input 230. The select signal 302 will remain high throughout the read-out process as shown in figure 3A.

During the reset phase 320, the input signal 304(φ) applied to the switch 260₁) Remains high to provide a discharge path to ground. During this phase, signals 306, 308, and 310(φ) applied to

switches

262, 264, and 250₂、φ₃φ 4) are kept low. Applying a sufficiently high level (V)_{RST_TFT}) To the programming voltage input 232 (V)_Data) To maximize the current flowing through the drive transistor 220. Thus, the voltage at node 244 in FIG. 2 is discharged to ground in preparation for the next cycle.

During integration phase 322, signal 304 applied to switch 262(φ₂) Held high, which provides a charging path from voltage source 210 through switch 262. During this phase, the

signals

304, 308, and 310(φ) applied to the

switches

260, 264, and 250₁、φ₃、φ₄) Are kept low. Programming voltage input 232 (V)_Data) Is set to the level (V)_{INT_TFT}) So that at the capacitor 240 (C)_oled) When fully charged, the voltage at node 244 is less than the turn-on voltage of the OLED 222. This condition minimizes interference from the OLED222 during reading of the drive transistor 220. Applied to the programming voltage input 232 (V) immediately before the integration time ends_Data) Signal 312 decreases to V_OFFSo that the capacitor 240 (C)_oled) The charge on is isolated from other circuits.

When the integration time is sufficiently long, it is stored in the capacitor 240 (C)_oled) Will be a function of the threshold voltage of the drive transistor 220. For a shortened integration time, the voltage at node 244 will experience incomplete stabilization and capacitor 240 (C)_oled) Will be a function of the threshold voltage and mobility of the drive transistor 220. Thus, the two parameters can be extracted by two independent reading processes with long and short integration stages.

During the precharge phase 324, the signals 304 and 306(φ) applied to the

switches

260 and 262₁、φ₂) Set to low. Upon application of the input signal 310 (phi) to the switch 254₄) Set high, the amplifier 250 is set to unity feedback. To protect the output stage of the amplifier 250 from short circuit current from the voltage source 210, when the signal 306(φ) is applied to the switch 262₂) Set low, signal 308(φ) applied to switch 264₃) Becomes high. When switch 264 is closed, parasitic capacitance 242 of the supply line is precharged to the common mode voltage VCM. The common mode voltage VCM is a level that must be lower than the turn-on voltage of the OLED 222. Immediately before the end of the precharge phase, a signal 310(φ) is applied to the switch 254₄) Set low to prepare the charge pump amplifier 250 for a read cycle.

During the read phase 336,

applySignals

304, 306, and 310 (phi) to

switches

260, 262, and 254₁、φ₂、φ₄) Set to low. Signal 308 (phi) applied to switch 264₃) Remains high to provide a charge transfer path from the driver circuit 202 to the charge pump amplifier 250. Will be a sufficiently high voltage 312 (V)_{RD_TFT}) Applied to the programming voltage input 232 (V)_Data) To minimize the channel resistance of the driving transistor 220. If the integration period is long enough, then capacitor 252 (C)_int) The accumulated charge on is no longer a function of the integration time. Thus, the output voltage of the charge pump amplifier 250 in this example is equal to:

for a shortened integration time, at capacitor 252 (C)_int) The charge accumulated above is given by the following equation:

thus, the output voltage 256 of the charge pump amplifier 250 at the end of the read cycle is equal to:

thus, the threshold voltage and mobility of the drive transistor 220 can be extracted by the output voltage 256 of the sense amplifier 250 in the middle and at the end of the read phase 326.

Fig. 3B is a timing diagram illustrating a reading process of the threshold turn-on voltage parameter of the OLED222 in fig. 2. The read process of the OLED222 also includes four phases: a reset phase 340, an integration phase 342, a precharge phase 344, and a read phase 346. As with the read process of the drive transistor 220 in fig. 3A, the read process of the OLED starts by applying a high select signal 302 to the select input 230.

Signals

304, 306, 308, and 310(φ) applied to

switches

260, 262, 264, and 254₁、φ₂、φ₃、φ₄) And the drawingsThe read process of the driving transistor 220 in 3A is the same. The programming signal 332 at the programming input 232, the signal 334 at the node 244, and the output signal 336 at the output of the amplifier 250 differ from those of fig. 3A.

During the reset phase 340, a sufficiently high level 332 (V) is applied_{RST_OLED}) To the program data input 232 (V)_Data) To maximize the current flowing through the drive transistor 220. Finally, the voltage at node 244 in fig. 2 is discharged through switch 260 to ground in preparation for the next cycle.

During the integration phase 342, the signal 306(φ) applied to the switch 262₂) Held high, provides a charging path from voltage source 210 through switch 262. Programming voltage input 232 (V)_Data) Set to level 332 (V)_{INT_OLED}) So that at the capacitor 240 (C)_oled) When fully charged, the voltage at node 244 is greater than the turn-on voltage of OLED 222. In this case, by the end of the integration phase 342, the drive transistor 220 is driving a constant current through the OLED 222.

During the precharge phase 344, the signal 332 applied to the program input 232 turns off the drive transistor 220. Capacitor 240 (C)_oled) The discharge may be allowed until it reaches the turn-on voltage of the OLED222 at the end of the precharge phase 344.

During the read phase 346, a sufficiently high voltage 332 (V) is applied_{RD_OLED}) To the programming voltage input 232 (V)_Data) To minimize the channel resistance of the driving transistor 220. If the precharge phase is long enough, then capacitor 252 (C)_int) The stabilized voltage on will not be a function of the precharge time. Thus, the output voltage 256 of the charge pump amplifier 250 at the end of the read phase is determined by:

signal 308 (phi) applied to switch 264₃) Held high to provide a charge transfer path from the driver circuit 202 to the charge pump amplifier 250. Thus, the output voltage signal 336 may be used to determine the OLED220 on voltage.

Fig. 3C is a timing diagram for directly reading the drive transistor 220 using the extraction circuit 200 in fig. 2. The direct read process has a reset phase 350, a precharge phase 352, and an integration/read phase 354. The read-out process is initiated by asserting the select input 230 in fig. 2. The select signal 302 applied to the select input 230 remains high throughout the read process shown in figure 3C. Signals 364 and 366 (phi) for

switches

260 and 262₁、φ₂) And is not valid during this read-out process.

During the reset phase 350, the signals 368 and 370(φ) for the

switches

264 and 254₃、φ₄) Set high to provide a discharge path to virtual ground. Applying a sufficiently high voltage 372 (V)_{RST_TFT}) To the programming input 232 (V)_Data) To maximize the current flowing through the drive transistor 220. As a result, node 244 discharges to common-mode voltage 374 (VCM)_RST) In preparation for the next cycle.

During the precharge phase 354, the program is programmed by applying an off voltage 372 (V) to the program input 232 in FIG. 2_OFF) Turning off the drive transistor 220. The common mode voltage input 258 applied to the positive input of amplifier 250 is raised to VCM_RDTo precharge the line capacitance. At the end of the precharge phase 354, the signal 370(φ) applied to the switch 254₄) Off to prepare the charge pump amplifier 250 for the next cycle.

At the beginning of the read/integrate phase 356, the program voltage input 232 (V)_Data) Is raised to V _{INT_TFT}372 to turn on the driving transistor 220. Capacitor 240 (C)_OLED) Begin to accumulate charge up to V_DataThe voltage at node 244 is subtracted until it equals the threshold voltage of drive transistor 220. At the same time, a proportional charge is also accumulated in the capacitor 252 (C)_INT) In (1). Thus, at the end of the read cycle 356, the output voltage 376 at the output 256 of the amplifier 250 is a function of the threshold voltage, which is given by:

as shown in the above equation, in the case of direct reading, the output voltage has a positive polarity. Thus, the threshold voltage of the driving transistor 220 may be determined by the output voltage of the amplifier 250.

As described above, the driving transistor 220 in fig. 2 may be a p-type transistor. Fig. 4A-4C are signal timing diagrams of signals applied to the components of fig. 2 to extract voltage threshold and mobility from the driving transistor 220 and the OLED222 when the driving transistor 220 is a p-type transistor. In an example in which the driving transistor 220 is a p-type transistor, a source of the driving transistor 220 is connected to the supply line 212(VD), and a drain of the driving transistor 220 is connected to the OLED 222. Fig. 4A is a timing diagram representing signals applied to the extraction circuit 200 when the driving transistor 220 is a p-type transistor, the extraction circuit 200 being used to extract the threshold voltage and mobility from the driving transistor 220. FIG. 4A shows the voltage signals 402 and 416 of the select input 232, switches 260, 262, 264, and 254, the program data input 230, the voltage at node 244, and the output voltage 256 of FIG. 2. The data extraction is divided into three stages: a reset phase 420, an integrate/precharge phase 422, and a read phase 424.

As shown in fig. 4A, the select signal 402 is active low and remains low throughout the sensing phases 420, 422, and 424. During read-out, signals 404 and 406(φ) applied to

switches

260 and 262₁、φ₂) Remains low (inactive). Signals 408 and 410 (phi) at

switches

264 and 254 during the reset phase₃、φ₄) Set high to charge node 244 to reset common-mode level VCM_rst. Charge pump input 258(VCM)_rst) The upper common voltage input 258 should be low enough to keep the OLED222 off. Programming data input 232V_DataSet to a sufficiently low value 412 (V)_{RST_TFT}) To provide the maximum charging current through the driving transistor 220.

During the integration/precharge phase 422, the common mode voltage on the common mode voltage input 258 is reduced to VCM_intAnd program input 232 (V)_Data) Increases to a level 412 (V)_{INT_TFT}) To make the driving transistor 220 conduct in the reverse directionThe method is simple. If the time allotted for this phase is long enough, the voltage at node 244 will decrease until the gate-source voltage of drive transistor 220 reaches the threshold voltage of drive transistor 220. Before the end of this phase, the signal 410(φ) applied to the switch 254₄) Goes low to prepare the charge pump amplifier 250 for the read phase 424.

By programming input 232 (V)_Data) The signal 412 is reduced to V_{RD_TFT}And turns on the drive transistor 220 to initiate the read phase 424. Is stored in the capacitor 240 (C)_OLED) The charge on is now transferred to the capacitor 254 (C)_INT). At the end of the read phase 424, the signal 408(φ) applied to the switch 264₃) Set low to isolate the charge pump amplifier 250 from the driver circuit 202. Output voltage signal 416V from amplifier output 256_outNow a function of the threshold voltage of the drive transistor 220, which is given by:

fig. 4B is a timing diagram for extracting the threshold voltage of the OLED22 of fig. 2 within a pixel assuming that the drive transistor 220 is a p-type transistor. This extraction process is very similar to the signal timing for the extraction circuit 200 for the n-type drive transistor in fig. 3A. FIG. 4B illustrates the select input 230, switches 260, 262, 264, and 254, program data input 232, the voltage at node 244, and the voltage signal 432-. The fetch process includes a reset phase 450, an integration phase 452, a precharge phase 454, and a read phase 456. The main difference between this read cycle and the read cycle in FIG. 4A is the application to the program data input 232 (V)_Data) Are applied to the drive transistor 210 during each readout phase. For a p-type thin film transistor that may be used for the drive transistor 220, the select signal 430 applied to the select input 232 is active low. The select input 232 remains low throughout the readout process as shown in fig. 4B.

The read process first resets the power in the reset phase 450Container 240 (C)_OLED). Signal 434 (phi) applied to switch 260₁) Set high to provide a discharge path to ground. Applied to the program input 232 (V)_Data) Signal 442 is reduced to V_{RST_OLED}To turn on the driving transistor 220.

During the integration phase 452, signals 434 and 436(φ) are applied to

switches

260 and 262₁、φ₂) Set to an off and on state, respectively, to provide a charging path to the OLED 222. Capacitor 240 (C)_OLED) Charging may be allowed until the voltage 444 at node 244 exceeds the threshold voltage at which the OLED222 is turned on. Applied to the program input 232 (V) before the integration phase 452 ends_Data) Voltage signal 442 rises to V_OFFTo turn off the driving transistor 220.

During the precharge phase 454, the capacitor 240 (C)_OLED) The upper accumulated charge is discharged into the OLED222 until the voltage 444 at node 244 reaches the threshold voltage of the OLED. Also, during the precharge phase 454, the signals 434 and 436(φ) applied to the

switches

260 and 262₁、φ₂) Off and signals 438 and 440 (phi) applied to

switches

264 and 254₃、φ₄) And (4) switching on. This provides the condition for the amplifier 250 to precharge the supply line 212(VD) to the common mode voltage input 258(VCM) provided at the positive input of the amplifier 250. At the end of the precharge phase, the signal 430(φ) applied to the switch 254₄) Off to prepare charge pump amplifier 250 for read phase 456.

When applied to the programming input 232 (V)_Data) Voltage 442 is reduced to V_RD__OLEDRead phase 456 is initiated by turning on drive transistor 229. Is stored in the capacitor 240 (C)_OLED) The charge on is now transferred to the capacitor 254 (C)_INT) Capacitor 254 (C)_INT) An output voltage 446 is created at the output 256 of the amplifier 250 as a function of the threshold voltage of the OLED 220.

Fig. 4C is a signal timing diagram for directly extracting the threshold voltage of the driving transistor 220 in the extraction system 200 shown in fig. 2 when the driving transistor 220 is a p-type transistor. FIG. 4C shows the voltage signal 462-. The extraction process includes a precharge phase 480 and an integration phase 482. However, in the timing diagram of fig. 4C, a special final read phase 484 is shown, which special read phase 484 may be eliminated if the output of the charge pump amplifier 250 is sampled at the end of the integration phase 482.

The extraction process is performed by simultaneously applying the drain storage capacitor 224, the source storage capacitor 226, and the capacitor 240 (C) in FIG. 2_OLED) And capacitor 242 are precharged. To this end, as shown in FIG. 4C, the

signals

462, 468, and 470 applied to the select line input 230 and the

switches

264 and 254 become active. The signals 404 and 406 (phi) applied to the

switches

260 and 262 throughout the readout process₁、φ₂) Are kept low. The level of common mode voltage input 258(VCM) determines the voltage on supply line 212 and the voltage at node 244. The common mode Voltage (VCM) should be low enough so that the OLED222 does not conduct. Applied to the program input 232 (V)_Data) Voltage 472 is set to a sufficiently low level (V)_{RST_TFT}) To turn on transistor 220.

At the beginning of the integration phase 482, the signal 470(φ) applied to the switch 254₄) Off to allow the charge pump amplifier 250 to integrate the current through the drive transistor 220. The output voltage 256 of the charge pump amplifier 250 will ramp at a constant rate that is a function of the threshold voltage of the drive transistor 220 and its gate-source voltage. The signal 468(φ) applied to the switch 264 before the integration phase 482 ends₃) Off to isolate the charge pump amplifier 250 from the driver circuit 220. Thus, the output voltage 256 of the amplifier 250 is given by:

wherein, I_TFTIs the drain current of the driving transistor 220, which is the mobility sum (V)_CM-V_Data-|V_th|)). T is_intIs the integration time duration. At an optional read stageIn segment 484, the signal 468(φ) applied to the switch 264₃) Held low to isolate the charge pump amplifier 250 from the drive transistor 202. The output voltage 256 is a function of the mobility and threshold voltage of the drive transistor 220, and the output voltage 256 can be sampled at any time during the read phase 484.

Fig. 4D is a timing diagram for directly reading the OLED222 in fig. 2. When the drive transistor 220 is turned on using a sufficiently high gate-to-source voltage, the drive transistor 220 may be used as an analog switch to turn on the anode terminal of the OLED 222. In this case, the voltage at node 244 is substantially equal to the voltage on supply line 212 (VD). Therefore, the drive current through the drive transistor 220 is only a function of the turn-on voltage of the OLED222 and the voltage set on the supply line 212. The drive current may be provided by a charge pump amplifier 250. The output voltage 256 of the integrator circuit 206 is a measure of the age of the OLED222 when integrated over a certain period of time.

Fig. 4D is a timing diagram showing signals applied to the extraction circuit 200 to extract the turn-on voltage of the OLED222 by direct reading. Fig. 4D shows three phases of the readout process: precharge phase 486, integration phase 487, and read phase 488. Fig. 4D includes: the

signal

489n or 489p used to select the input 230 in FIG. 2, the signal 490(φ) applied to the switch 260₁) Signal 491 (phi) for switch 262₂) Signal 492 (phi) for switch 264₃) Signal 493 (phi) for switch 254₄) A

program voltage signal

494n or 494p for program data input 232 of fig. 2, a voltage 495 at node 244 of fig. 2, and an output voltage signal 496 at output 256 of amplifier 250 of fig. 2.

The process begins by asserting the select signal corresponding to the desired row of pixels in the array 102. As shown in fig. 4D, the selection signal 489n is active high for an n-type selection transistor and active low for a p-type selection transistor. In the n-type driving transistor, a high-level selection signal 489n is applied to the selection input terminal 230. When the driving transistor 220 is a p-type driving transistor, a low-level signal 489p is applied to the selection input terminal 230.

During precharge period 486 and integrationDuring period 487,

select signal

489n or 489p will remain active. In the readout method, [ phi ]₁And phi₂Inputs 490 and 491 are not active. During the precharge period, the switching signal 492 φ₃And 493 phi₄Set to high level to provide signal path so that supply line (C)_p) And the voltage at node 244 is precharged to the common mode Voltage (VCM) provided at the non-inverting terminal of amplifier 250_OLED). Sufficiently high

drive voltage signal

494n or 494p (V)_{ON_nTFT}Or V_{ON_pTFT}) Applied to the data input 232 (V)_Data) So that the driving transistor 220 operates as an analog switch. Thus, supply voltage 212VD and node 244 are precharged to the common-mode Voltage (VCM)_OLED) In preparation for the next cycle. At the beginning of the integration phase 487, the switch inputs 493 φ₄Off to allow the charge pump module 206 to integrate the current of the OLED 222. The output voltage 496 of the charge pump module 206 will ramp at a constant rate that is the turn-on voltage of the OLED222 and the voltage 495 set at node 244 (i.e., VCM)_OLE) As a function of (c). Before the end of the integration phase 487, the switching signal 492 φ₃Off to isolate the charge pump module 206 from the pixel circuit 202. After this time, the output voltage remains constant until the charge pump amplifier 206 is reset for another read. After a period of integration, the output voltage of the integrator is given by:

this is a measure of the degree of aging of the OLED. T in this equation_intIs a switching signal 493 (phi)₄) Falling edge of and switching signal 492 (phi)₃) Time interval between falling edges.

A similar extraction process as for the two transistor drive circuit in fig. 2 can be used to extract parameters of non-uniformity and aging, such as the threshold voltage and mobility of the three transistor drive circuit as part of the data extraction system 500 shown in fig. 5. The data extraction system 500 includes a drive circuit 502 and a readout circuit 504. Readout circuitry 504 is part of current supply and readout circuitry 120 and collects data from the columns of pixels 104 shown in fig. 1, with readout circuitry 504 including charge pump circuitry 506 and switch box circuitry 508. The voltage source 510 provides a supply Voltage (VDD) to the driver circuit 502. Like the voltage driver 114 and current supply and sense circuitry 120 of fig. 1, the charge pump circuitry 506 and switch box circuitry 508 are disposed on the top or bottom side of the array 102. This is achieved either by direct fabrication on the same substrate as the array 102 or by incorporating microchips on the substrate or on the wires as a hybrid solution.

The driving circuit 502 includes a driving transistor 520, an organic light emitting device 522, a drain storage capacitor 524, a source storage capacitor 526, and a selection transistor 528. Select line input 530 is connected to the gate of select transistor 528. The program input 532 is connected to the gate of the drive transistor 220 through the select transistor 528. Select line input 530 is also connected to the gate of output transistor 534. The output transistor 534 is connected to the source of the drive transistor 520 and a voltage monitoring output line 536. The drain of the driving transistor 520 is connected to the supply voltage source 510, and the source of the driving transistor 520 is connected to the OLED 522. The source storage capacitor 526 is connected between the gate and the source of the driving transistor 520. The drain storage capacitor 524 is connected between the gate and the drain of the driving transistor 520. OLED522 has a parasitic capacitance that can be modeled as capacitor 540. The monitor output voltage line 536 also has a parasitic capacitance that can be modeled as a capacitor 542. The driving transistor 520 in this example is a thin film transistor made of amorphous silicon. The voltage node 544 is the point between the source terminal of the driving transistor 520 and the OLED 522. In this example, the driving transistor 520 is an n-type transistor. System 500 may be implemented with a p-type drive transistor instead of drive transistor 520.

The readout circuit 504 includes a charge pump circuit 506 and a switch box circuit 508. The charge pump circuit 506 includes an amplifier 550 having a capacitor 552 (C) in a negative feedback loop for the amplifier 550_int). Switch 554(S4) is used to enable capacitor 552C during the precharge phase_intAnd (4) discharging. Amplifier 550 has a negative input connected to capacitor 552 and switch 554 and a common mode voltage input 558(VCM)The positive input end is connected. The output 556 of the amplifier 550 may indicate a number of extracted factors that drive the transistor 520 and the OLED222, as will be explained below.

The switch box circuit 508 includes

several switches

560, 562, and 564 for conducting current to and from the drive circuit 502. The switch 560 is used to provide a discharge path to ground during the reset phase. The switch 562 is used to provide a power supply connection during normal operation of the pixel 104 and during the integration phase of the readout process. The switch 564 is used to isolate the charge pump circuit 506 from the supply line voltage source 510.

In three-transistor drive circuit 502, sensing is typically performed through monitor line 536. Readout may also be performed through voltage supply lines from supply voltage source 510, similar to the timing signal process in fig. 3A-3 CA. Input signal (phi) applied to

switches

560, 562, 564, and 554₁-φ₄) Select input 530 and program voltage input 532 (V)_Data) Is used to control the performance of the sensing circuit 500. During various stages of the read process, program data is input 532 (V)_Data) And a common mode voltage input 558(VCM) to apply a particular level.

Three-transistor drive circuit 502 may be differentially programmed by programming voltage input 532 and monitoring output 536. Thus, the reset phase and the precharge phase may be combined together to form the reset/precharge phase, followed by the integration phase and the read phase.

Fig. 6A is a timing diagram of signals involved in extracting the threshold voltage and mobility of the driving transistor 520 in fig. 5. The timing diagram includes the voltage signals 602- > 618 of the select input 530, switches 560, 562, 564, 554, the program voltage input 532, the voltage at the gate of the drive transistor 520, the voltage at node 544, and the output voltage 556 in FIG. 5. The sensing process in fig. 6A has a precharge phase 620, an integration phase 622, and a read phase 624. The sensing process is initiated by simultaneously precharging the drain capacitor 524, the source capacitor 526, and the

parasitic capacitors

540 and 542. To this end, the line voltage 602 and signals 608 and 610(φ) applied to

switches

564 and 554 are selected₃、φ₄) Becomes effective as shown in fig. 6A. Signals 604 and 606 (phi) applied to

switches

560 and 562₁、φ₂) Remains low throughout the readout period.

The level of the common mode input 558(VCM) determines the voltage on the output monitor line 536 and the voltage at node 544. Applied to common mode output 558(VCM)_TFT) Should be low enough so that the OLED222 does not conduct. In the precharge phase 620, applied to the program voltage input 532 (V)_Data) Voltage signal 612 is sufficiently high (V)_{RST_TFT}) To turn on the drive transistor 520 and also low enough that the OLED522 always remains off.

At the beginning of the integration phase 622, the voltage 602 applied to the select input 530 becomes inactive to allow charge to be stored in the capacitor 540 (C)_OLED) In (1). The voltage at node 544 begins to rise and the gate voltage of drive transistor 520 rises at a rate that is the ratio of the capacitance of source capacitor 526 to the sum of the capacitance of source capacitor 526 plus the capacitance of drain capacitor 524 [ C ]_S1/(C_S1+C_S2)]. Once the difference between the gate voltage of the drive transistor 520 and the voltage at node 544 equals the threshold voltage of the drive transistor 520, the charging is ended. The signal 610(φ) applied to the switch 554 before the integration phase 622 ends₄) Off to prepare the charge pump amplifier 550 for the read phase 624.

To perform the read phase 624, the signal 602 applied to the select input 530 becomes active again. Programming input 532 (V)_{RD_TFT}) The voltage on signal 612 is low enough to keep the drive transistor 520 off. Is stored in the capacitor 240 (C)_OLED) The charge on is now transferred to the capacitor 254 (C)_INT) And creates an output voltage 618, the output voltage 618 being proportional to the threshold voltage of the drive transistor 520:

the signal 608(φ) applied to the switch 564 before the end of the read phase 624₃) Is turned off to connect the charge pump circuit 506 and the driving circuit 502 are spaced apart.

Fig. 6B is a timing diagram of input signals for extracting the turn-on voltage of the OLED522 in fig. 5. FIG. 6B includes the select input 530, switches 560, 562, 564, and 554 of FIG. 5, the program voltage input 532, the voltage at the gate of the drive transistor 520, the voltage at node 544, the common mode voltage input 558, and the voltage signal 632- > 650 of the output voltage 556. The sensing process in fig. 6B has a precharge phase 652, an integration phase 654, and a read phase 656. Similar to the sensing of drive transistor 220 in fig. 6A, the sensing process is initiated by simultaneously precharging drain capacitor 524, source capacitor 526, and

parasitic capacitors

540 and 542 in precharge phase 652. To this end, signal 632 applied to select input 530 and signals 638 and 640(φ) applied to

switches

564 and 554₃、φ₄) Becomes active as shown in fig. 6B. Signals 634 and 636 (phi)₁、φ₂) Remains low throughout the readout period. Input voltage 648 (VCM) applied to common mode voltage input 258_Pre) Should be high enough to turn on the OLED 522. Applied to programming input 532 (V)_Data) Voltage 642 (V)_{Pre_OLED}) Low enough to keep the drive transistor 520 off.

At the beginning of the integration phase 654, the signal 632 applied to the select input 530 becomes inactive to allow charge to be stored in the capacitor 540 (C)_OLED) In (1). The voltage at node 544 begins to decrease and the gate voltage of drive transistor 520 decreases, at a rate that the gate voltage of drive transistor 520 decreases by the ratio C of the capacitance of source capacitor 526 to the sum of the capacitance of source capacitor 526 plus the capacitance of drain capacitor 524_S1/(C_S1+C_S2)]. Once the voltage at node 544 reaches the turn-on voltage (V) of OLED522_OLED) The discharge is complete. Signal 640(φ) applied to switch 554 before the end of integration phase 654₄) Off to prepare the charge pump circuit 506 for the read phase 656.

To perform the read phase 656, the signal 632 applied to the select input 530 becomes active again. Programming input 532 (V)_{RD_OLED}) The upper voltage 642 should be low enough to keep the drive transistor 520 off. Stored in a capacitor 540(C_OLED) The charge on is then transferred to capacitor 552 (C)_INT) To create an output voltage 650 at the amplifier output 556 that is proportional to the turn-on voltage of the OLED 522.

Before the end of the read phase 656, the signal 638(φ)₃) Off to isolate the charge pump circuit 508 from the drive transistor 502.

As shown, the monitor output transistor 534 provides a direct path for the linear integral of the current of the drive transistor 520 or OLED 522. The readout can be done during the precharge and integration periods. However, fig. 6C illustrates a timing diagram of the input signals for an additional final read phase that may be removed if the output of the charge pump circuit 508 is sampled in the integration phase. FIG. 6C includes the select input 530, switches 560, 562, 564, and 554 of FIG. 5, the program voltage input 532, the voltage at node 544, and the voltage signal 660- 674 of the output voltage 556. The sensing process in fig. 6C thus has a precharge phase 676, an integration phase 678, and an optional read phase 680.

As shown in fig. 6C, the direct integration readout process of the n-type transistor 520 of fig. 5 is initiated by simultaneously precharging the drain capacitor 524, the source capacitor 526, and the

parasitic capacitors

540 and 542. To this end, signal 660 applied to select input 530 and signals 666 and 668(φ) applied to

switches

564 and 554₃、φ₄) Becomes effective as shown in fig. 6C. Signals 662 and 664 (phi) applied to

switches

560 and 562₁、φ₂) Remains low throughout the readout period. The level of the common mode voltage input 558(VCM) determines the voltage on the monitor output line 536 and the voltage at node 544. Voltage signal (VCM) of common mode voltage output 558_TFT) Low enough so that the OLED522 does not conduct. Applied to programming input 532 (V)_Data) Signal 670 (V)_{ON_TFT}) High enough to turn on the drive transistor 520.

At the beginning of the integration phase 678, the signal 668(φ) applied to switch 554₄) Off to allow the charge pump amplifier 550 to integrate the current from the drive transistor 520. The output voltage 674 of the charge pump amplifier 550 decreases at a constant rate that is a function of the threshold voltage, mobility, and gate-source voltage of the drive transistor 520. Before the end of the integration phase, signal 666(φ) applied to switch 564₃) Off to isolate the charge pump circuit 508 from the driver circuit 502. Thus, the output voltage is given by:

wherein, I_TFTIs the drain current of the driving transistor 520, which is the mobility sum (V)_Data-V_CM-V_th) As a function of (c). T is_intIs the integration time duration. The output voltage 674 is a function of the mobility and threshold voltage of the drive transistor 520, which can be sampled at any time during the read phase 680.

Fig. 6D shows a timing diagram of input signals for directly reading the turn-on (threshold) voltage of the OLED522 in fig. 5. Fig. 6D includes the select input 530, switches 560, 562, 564, and 554, programming voltage input 532, voltage at node 544, and voltage signal 682- & 696 of output voltage 556 of fig. 5. The sensing process in fig. 6C has a precharge phase 697, an integration phase 698, and an optional read phase 699.

The sensing process as in fig. 6D is initiated by simultaneously precharging drain capacitor 524, source capacitor 526 and

parasitic capacitors

540 and 542. To this end, signal 682 applied to select input 530 and signals 688 and 690(φ) applied to

switches

564 and 554₃、φ₄) Becomes active as shown in fig. 6D. Signals 684 and 686 (phi)₁、φ₂) Remains low throughout the readout period. The level of the common mode voltage input 558(VCM) determines the voltage on the monitor output line 536 and the voltage at node 544. Voltage signal (VCM) of common mode voltage input 558_OLED) High enough to turn on the OLED 522. Programming input 532 (V)_Data) Signal 692 (V)_{OFF_TFT}) Low enough to keep the drive transistor 520 off.

At the beginning of integration phase 698, signal 690(φ) applied to switch 552₄) Off to allow the charge pump amplifier 550 to integrate the current from the OLED 522. The output voltage 696 of the charge pump amplifier 550 will ramp at a constant rate that is a function of the threshold voltage and the voltage across the OLED 522.

Signal 668(φ) applied to switch 564 before the end of integration phase 698₃) Off to isolate the charge pump circuit 508 from the driver circuit 502. Thus, the output voltage is given by:

wherein, I_OLEDIs the OLED current, which is (V)_CM-V_th) Function of, T_intIs the integration time duration. The output voltage is a function of the threshold voltage of the OLED522, which can be sampled at any time during the read phase 699.

Those skilled in the computer, software, and networking arts will appreciate that the controller 112 of fig. 1 may generally be implemented using one or more general purpose computer systems, microprocessors, digital signal processors, microcontrollers, Application Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), Field Programmable Logic Devices (FPLDs), Field Programmable Gate Arrays (FPGAs), programmed according to the teachings described and illustrated herein.

Further, two or more computing systems or devices may be substituted for any of the controllers described herein. Accordingly, principles and advantages of distributed processing, such as redundancy, repetition, etc., may also be implemented as desired to increase the robustness and performance of the controller described herein. The controller may also be implemented on a computer system or system that extends across any network environment using any suitable interface mechanisms and communication techniques, including, for example: any suitable form of telecommunications (e.g., voice, modem, etc.), the Public Switched Telephone Network (PSTN), the Packet Data Network (PDN), the internet, intranets, combinations thereof, and the like.

The operation of the exemplary data extraction process will now be described with reference to the flow chart shown in fig. 7. The flow chart in fig. 7 represents machine readable instructions for determining an example of threshold voltage and mobility for a simple drive circuit that can implement the maximum aperture of the pixel 104 in fig. 1. In this example, the machine-readable instructions comprise an algorithm executed by: (a) a processor, (b) a controller, and/or (c) one or more other suitable processing devices. The algorithm may be embodied in software stored on a tangible medium such as a flash memory, a CD-ROM, a floppy disk, a hard drive, a digital video (versatile) disk (DVD), or other memory. Those skilled in the art will readily appreciate that the entire algorithm and/or portions of the algorithm(s) can be performed by devices other than processors and/or embodied in firmware or dedicated hardware in a well-known manner (e.g., as may be implemented using Application Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), Field Programmable Logic Devices (FPLDs), Field Programmable Gate Arrays (FPGAs), discrete logic, etc.). For example, any or all of the components in the extraction sequence may be implemented by software, hardware, and/or firmware. Also, some or all of the machine readable instructions represented by the flow chart of FIG. 7 may be implemented manually. Further, although the example algorithm is described with reference to the flowchart illustrated in FIG. 7, persons of ordinary skill in the art will readily appreciate that many other methods of implementing the example machine readable instructions may be used. For example, the order of execution of the modules may be changed and/or some of the modules described may be changed, eliminated, or combined.

The pixel under study 104 is selected by turning on the corresponding select and program lines (700). Once the pixel 104 is selected, readout is performed through four stages. The readout process begins by first applying a parasitic capacitance (C) to the OLED during a reset phase (702)_oled) And discharging is performed. Then, the driving transistor is turned on for a certain period of time, which causes some charge to be accumulated in the capacitance (C) of the OLED_oled) And (704). During this integration phase, the select transistor is turned off to isolate the capacitance C of the OLED_oledCharge on, followed by line parasitic capacitance (C)_P) Is precharged to a known level 706. Finally, in the read phase (708), the driveThe moving transistor is turned on again to allow the capacitance C of the OLED_oledThe charge on is transferred to the charge pump amplifier output. The output of the amplifier represents a quantity that is a function of mobility and threshold voltage. The readout process is completed by deselecting pixels, thereby preventing interference when calibrating other pixels.

Fig. 8 is a flow chart of different extraction periods and parameter applications for a pixel circuit such as the two transistor circuit of fig. 2 and the three transistor circuit of fig. 5. One flow is in-pixel integration associated with charge transfer (800). Charge associated with a desired parameter is accumulated in the internal capacitance of the pixel (802). The charge is then transferred to an external readout circuit (such as a charge pump circuit or integrator) to create a scaled voltage (804). Another flow is off-pixel integration or direct integration (810). The device current is directly integrated 812 by an external readout circuit, such as a charge pump circuit or integrator.

In both procedures, the generated voltages are post-processed to find the desired parameters, such as the threshold voltage or mobility of the drive transistor and the turn-on voltage of the OLED (820). The extracted parameters may then be used for a variety of applications (822). Examples of usage parameters include: the programming data is modified to compensate for pixel variations based on the extracted parameters (824). Another example is pre-aging (826) the pixel panel. Another example is: the processing yield of the pixel panel is estimated after the manufacture.

Fig. 9 is a block diagram and diagram of components of a data extraction system that includes a pixel circuit 900, a switch box 902, and a readout circuit 904, which may be a charge pump/integrator. The constituent components (910) of the pixel circuit 900 include: light emitting devices such as OLEDs, driving means such as driving transistors, storage means such as capacitors, and access switches such as selection switches. The components 912 of switch box 902 include: a set of electronic switches controllable by an external control signal. The components 914 of the readout circuit 904 include: an amplifier, a capacitor, and a reset switch.

The desired parameters may be stored as represented by block 920. The parameters desired in this example may include: the threshold voltage of the driving transistor, the mobility of the driving transistor, and the turn-on voltage of the OLED. The function of the switch box 902 is represented by block 922. These functions may include: the current is directed into and out of the pixel circuit 900, a discharge path is provided between the pixel circuit 900 and the charge pump of the readout circuit 904, and the charge pump of the readout circuit 904 is isolated from the pixel circuit 900. The function of the sensing circuit 904 is represented by block 924. One of the functions includes: charge is transferred from the internal capacitance of the pixel circuit 900 to the capacitor of the readout circuit 904 to generate a voltage proportional to the charge with the integration within the pixel (step 800-804 in fig. 8). Another function includes: the current of the driving transistor or OLED in the pixel circuit 900 is integrated for a certain time to generate a voltage proportional to the current (step 810-814 in fig. 8).

Fig. 10 is a timing chart of signals involved in the extraction of the threshold voltage and mobility of the driving transistor 520 in the modification of the circuit in fig. 5 in which the gate of the output transistor 534 is connected to the separate control signal line RD instead of the SEL line. The sensing process in fig. 10 has a precharge phase 1001, an integration phase 1002 and a read phase 1003. During the precharge phase 1001, the voltage V at the gate and source of the drive transistor 520_AAnd V_BReset to the initial voltage by making both the SEL signal and the RD signal high.

During integration phase 1002, signal RD goes low and gate voltage V_AHolding V_initAnd the voltage V at the source (node 544)_BIs charged back to a voltage that is a function of TFT characteristics, including mobility and threshold voltage, e.g., (V)_init–V_T). If the integration phase 1002 is long enough, the voltage V_BWill be only the threshold voltage (V)_T) As a function of (c).

During read phase 1003, signal SEL is low, V_ADown to (V)_init+ Vb-Vt) and V_BDown to Vb. Total capacitance C of charge at slave node 544_TTo an integrating capacitor (C) in the readout circuit 504_int)552. The output voltage V can be read at the output of the charge amplifier 550 using an analog-to-digital converter (ADC)_out. Alternatively, a comparator can be used to compare the output voltage to a reference voltage and simultaneously adjust V_initUntil the two voltages become the same. The reference voltage may be created by sampling the line that is not connected to any pixel during one phase and sampling the pixel charge during another phase.

Fig. 11 is a timing chart of input signals for extraction of the on voltage of the OLED522 in the modified example of the circuit in fig. 5.

Fig. 12 is a circuit diagram of a pixel circuit which reads a pixel state by initializing a node from the outside. The driving transistor T1 has a drain connected to the supply voltage Vdd, a source connected to the OLED D1, and a gate connected to the Vdata line via the switching transistor T2. The gate of transistor T2 is connected to the write line WR. The storage capacitor Cs is connected between a node a (between the gate of the driving transistor T1 and the transistor T2) and a node B (between the source of the driving transistor T1 and the OLED). Read transistor T3 connects node B to the monitor line and is controlled by a signal on read line RD.

Fig. 13 is a timing chart illustrating an operation of the circuit in fig. 12 for initializing a node from the outside. During the first phase P1, the driving transistor T1 is programmed with the off voltage V0, and the voltage of the OLED is set to Vrst from the outside via the monitor line. During the second phase P2, the read signal RD turns off the transistor T3 and thus discharges the voltage of the OLED through the OLED D1 until the OLED is turned off (creating an OLED on voltage threshold). During the third phase P3, the turn-off voltage of the OLED is transmitted to an external readout circuit (e.g., using a charge amplifier) via the monitor line.

Fig. 14 is a flowchart illustrating reading of a pixel state by initializing a node from the outside. In a first step, the internal node is reset such that at least one pixel component is conductive. The second step provides time for the internal/external nodes to settle to a desired state (e.g., an off state). The third step reads the off-state value of the internal node.

Fig. 15 is a timing diagram illustrating a modified operation of the circuit in fig. 12 to initialize a node from inside. During the first phase P1, the driving transistor T1 is programmed with a turn-on voltage V1. Therefore, the voltage of the OLED rises to a voltage higher than its on-voltage threshold. During the second phase P2, the drive transistor T1 is programmed with the off voltage V0, and thus the voltage of the OLED is discharged by the OLEDD1 until the OLED is turned off (creating an OLED on voltage threshold). During the third phase P3, the turn-on threshold voltage of the OLED is transferred to an external readout circuit (e.g., using a charge amplifier).

Fig. 16 is a flowchart illustrating reading of a pixel state by initializing a node from inside. The first step turns on the selected pixel for measurement so that the internal/external node settles to the on state. The second step turns off the select pixel so that the internal/external nodes settle to the off state. The third step reads the off-state value of the internal node.

Fig. 17 is a circuit diagram illustrating two pixel circuits connected to a common monitor line via respective read transistors T3 among the pixel circuits shown in fig. 12, and fig. 18 is a timing chart illustrating an operation of a combining circuit that reads pixel charges using the common monitor line. During the first phase P1, the pixel is programmed with off voltages V01 and V03, and the voltage of the OLED is reset to VB 0. During the second phase P2, the read signal RD is OFF and the pixel for measurement is programmed with the turn-on voltage V1, and at the same time another pixel stays in the OFF state. Thus, the voltage of the OLED in the pixel selected for measurement is above the turn-on voltage threshold while another pixel connected to the monitor line stays in the reset state. During the third phase P3, the pixel programmed with the on voltage is programmed with an off voltage V02 such that it is also off. During this phase, the voltage of the OLED in the selected pixel discharges to its turn-on threshold voltage. During the fourth phase P4, the voltage of the OLED is read back.

FIG. 19 is a flow chart illustrating reading of pixel states using a common monitor line. The first step turns off all pixels and resets the internal/external nodes. The second step turns on the selected pixel for measurement, thereby setting the internal/external node to the on state. The third step turns off the select pixel so that the internal/external nodes settle to the off state. The fourth step reads the off-state value of the internal node.

FIG. 20A illustrates a pixel circuit with the Vdata line connected to node A via switch transistor T2 and the Monitor/Vref line connected to node B via readout transistor T3. The node a is connected to the gate of the driving transistor T1 and one side of the storage capacitor Cs. FIG. 20B is a timing diagram of the operation of the circuit in FIG. 20A using charge-based compensation. The node B is connected to the source of the driving transistor T1 and the other side of the capacitor Cs and the drain of the switching transistor T4, wherein the drain of the switching transistor T4 is connected between the source of the driving transistor and the supply voltage source Vdd. The operation in this case is as follows:

1. during the programming cycle, a programming voltage V is utilized which is supplied to node A from the Vdata line via transistor T2_PThe pixel is programmed and node B is connected to a reference voltage Vref from the VMonitor/Vref line via transistor T3.

2. During the discharge period, the read signal RD turns off the transistor T3, and thus adjusts the voltage at the node B to partially compensate for the variation (or aging) of the driving transistor T1.

3. During the driving phase, the write signal WR turns off the transistor T2, and after a delay (can be 0), the signal EM turns on the transistor T4 to connect the supply voltage Vdd to the driving transistor T1. Therefore, the current of the driving transistor T1 is stored in the capacitor C_SAnd the same current flows to the OLED.

In another construction, the reference voltage Vref is provided from the Vdata line to node A via switch transistor T2, and the programming voltage Vp from the Monitor/Vdata line is provided to node B via read transistor T3. The operation in this case is as follows:

1. during the programming cycle, node A is charged to the reference voltage Vref provided from the Vdata line via transistor T2, and the programming voltage Vp from the Monitor/Vref line is provided to node B via transistor T3.

Fig. 21 is a timing chart of an operation for reading out the current and/or voltage of the driving transistor T1 of the circuit in fig. 20A. The pixels may be programmed with or without a discharge period. If there is a discharge period, the discharge period may be a short time such that the capacitor C_SPartially discharged, or the discharge period may be long enough for the capacitor C_SAnd discharged until the driving transistor T1 is turned off. In the case of a short discharge time, the current of the driving transistor T1 can be read by applying a fixed voltage during the readout time, or the voltage created by the driving transistor T1 acting as an amplifier can be read by applying a fixed current from the Monitor/Vref line via the reading transistor T3. In the case of a long discharge time, the voltage created at node B as a result of the discharge can be read back. This voltage represents the threshold voltage of the driving transistor T1.

Fig. 22 is a timing diagram of an operation of the circuit in fig. 20A for reading out the voltage of the OLED. In the case depicted in fig. 22, the pixel circuit is programmed (with a high turn-on voltage) so that the drive transistor T1 acts as a switch and the current or voltage of the OLED is measured through transistors T1 and T3. In another case, a plurality of current/voltage points are measured by changing the voltages at the node a and the node B, and the voltage of the OLED can be extracted according to an equation between the current and the voltage. For example, if the driving transistor T1 operates in the linear region, the voltage of the OLED more affects the current of this transistor; therefore, by having current points in the linear operation region and the saturation operation region of the driving transistor T1, the voltage of the OLED can be extracted according to the voltage-current relationship of the transistor T1.

If more than two pixels share the same monitor line, they are turned off by applying an off voltage to their drive transistor T1 for pixels that are not selected for OLED measurement.

FIG. 23 is a timing diagram of a deformation operation of the circuit of FIG. 20A for reading out the voltage of the OLED, as follows:

1. during the reset phase, the OLED is charged with a turn-on voltage.

2. During the discharge phase, the signal Vdata turns off the drive transistor T1, and thus discharges the voltage of the OLED to an off voltage through the OLED.

3. During the readout phase, the off voltage of the OLED is read back through the drive transistor T1 and the read transistor T3.

Fig. 24 illustrates a circuit for extracting parasitic capacitance from a pixel circuit using external compensation. In most external compensation systems for OLED displays, the internal nodes in the pixels are different during the measurement and drive periods. Therefore, the effect of the parasitic capacitance is not properly extracted.

The following is the procedure for compensating parasitic parameters:

1. the pixel in state 1 is measured with one set of voltages/currents (external or internal).

2. The pixel in state 2 is measured with a different set of voltages/currents (external or internal).

3. The parasitic parameters are extracted from the previous two measurements based on a pixel model comprising the parasitic parameters (step 2 is repeated for a number of different sets of voltages/currents if the model requires more measurements).

In another technique, parasitics are extracted experimentally. For example, the two sets of measurements can be subtracted and the difference added to the other measurements by using a gain. The gain can be extracted experimentally. For example, the scaled difference can be added to the set of measurements made for a panel of a particular gray level. The scaling factor can be adjusted experimentally until the image on the panel meets specifications. This scaling factor can then be used as a fixed parameter for all other panels.

One method of external measurement of parasitic parameters is current sensing. In this case, in order to extract the parasitic parameter, the external voltage set by the measurement circuit can be changed for two sets of measurements. Fig. 24 shows a pixel with a readout line for measuring the pixel current. The voltage of the sense line is measured by the cell bias voltage (V)_B) And (5) controlling.

Fig. 25 illustrates a pixel circuit that can be used for current measurement. Using calibrated programming voltage V_calProgramming the pixel and setting the monitor line to the reference voltage V_ref. Then, the current of the driving transistor T1 is measured by turning on the transistor T3 with the control signal RD. During the driving period, the voltage at the node B is at V_oledAnd the voltage at node A is from V_calChange to V_cal+(V_oled-V_ref)C_S/(C_P+C_S) In which V is_calIs a calibrated programming voltage, C_PIs the total parasitic capacitance at node A, and V_refIs the monitor voltage during programming). Gate-source voltage V of driving transistor_GSDuring a programming cycle (V)_P-V_ref) And during the drive period [ (V)_P-V_ref)C_S/(C_P+C_S)-V_oledC_P/(C_P+C_S)]Is different. Therefore, the current during programming and measurement is different from the drive current due to parasitic capacitance that will affect the compensation, especially in the presence of significant mobility variations in the drive transistor T1.

To extract the parasitic effects during the measurement, the voltage V at the monitor line can be made to be_BThe voltage during the measurement being different from V_BVoltage during programming cycle (V)_ref). Thus, the gate-source voltage V during measurement_GSWill be [ (V)_P-V_ref)C_S/(C_P+C_S)-V_BC_P/(C_P+C_S)]. Capable of using two different V_B(V_B1And V_B2) To extract the parasitic capacitance C_PThe value of (c). In one case, the voltage V_PIs the same, but the current in both cases will be different. Parasitic capacitance C can be extracted using the pixel current equation and from the difference of these two currents_P. In another case, one of V can be adjusted_PTo obtain the same current as in the other case. In this case, the difference will be (V)_B1-V_B2)C_P/(C_P+C_S). Thus, C can be extracted_PSince all parameters are known.

Fig. 26 illustrates a pixel having charge readout capability. Here, the internal capacitor is charged and then the charge is transferred to the charge integrator, or the current is integrated by the charge readout circuit. In the case of integrated current, the parasitic capacitance can be extracted using the above method.

When it is desired to read the charge integrated in the internal capacitor, in addition to directly adjusting the voltage, it is also possible to use two different integration times to extract the parasitic capacitance. For example, in the pixel circuit shown in fig. 25, the OLED capacitance can be used to integrate the pixel current from the inside, and then the integrated value can be transmitted to the outside using the charge pump amplifier. In order to extract the parasitic parameters, the above-described method of changing the voltage can be used. However, due to the nature of charge integration, two different integration times can be used when integrating the current in the OLED capacitor.

As the voltage of the node B increases, the influence of the parasitic parameter on the pixel current becomes large. Thus, a measurement with a longer integration time results in a larger voltage at node B, and thus the measurement is more affected by parasitic parameters. A method can use charge values and can use pixel equations to extract parasitic parameters. Another method ensures that the measured charge normalized by the integration time is the same in both cases by adjusting the programming voltage. Then, as described above, the parasitic capacitance can be extracted using the difference between the two voltages.

While particular embodiments and applications of the present invention have been illustrated and described, it is to be understood that the invention is not limited to the precise construction and compositions disclosed herein and that various modifications, changes, and variations may be apparent from the foregoing descriptions without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for extracting a circuit parameter from a pixel circuit, the pixel circuit comprising a light emitting device, a drive device for providing a programmable drive current to the light emitting device, a programming input, and a storage device for storing a programming signal, the method comprising:

turning on the driving device such that a voltage of the light emitting device rises to a level higher than an on voltage of the light emitting device;

turning off the driving device so that a voltage across the light emitting device is discharged through the light emitting device until the light emitting device is turned off; and

reading a voltage across the light emitting device while the light emitting device is off.

2. A system for extracting a circuit parameter from a pixel circuit, the pixel circuit including a light emitting device, a drive device for providing a programmable drive current to the light emitting device, a programming input, and a storage device for storing a programming signal, the system comprising:

a controller connected to the pixel circuit and providing control input signals to the pixel circuit in a predetermined sequence to produce output voltage values that are a function of parameters of the pixel circuit, the sequence comprising:

turning off the driving device and supplying a predetermined voltage from an external source to the light emitting device;

discharging the light emitting device until the light emitting device is turned off; and

3. The system of claim 2, comprising a plurality of the pixel circuits connected to the external source via a common external line, and reading of voltages on the light emitting devices in the plurality of pixel circuits is accomplished at different times via the common external line.

4. The system of claim 3, comprising:

a charge pump amplifier having a current input and a voltage output, the charge pump amplifier comprising an operational amplifier in a negative feedback configuration, wherein feedback is provided by a capacitor connected between the output and an inverting input of the operational amplifier, a common mode voltage source for driving a non-inverting input of the operational amplifier, and an electronic switch connected across the capacitor to reset the capacitor, and

a switching module including an input connected to the output of the pixel circuit and an output connected to the input of the charge pump amplifier, the switching module including a plurality of electronic switches for directing current into and out of the pixel circuit, providing a discharge path between the pixel circuit and the charge pump amplifier, and isolating the charge pump amplifier from the pixel circuit.

5. A system for extracting a circuit parameter from a pixel circuit, the pixel circuit including a light emitting device, a drive device for providing a programmable drive current to the light emitting device, a programming input, and a storage device for storing a programming signal, the system comprising: