CN107977038B - Solar array voltage compensation device - Google Patents
Solar array voltage compensation device Download PDFInfo
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- CN107977038B CN107977038B CN201711452557.9A CN201711452557A CN107977038B CN 107977038 B CN107977038 B CN 107977038B CN 201711452557 A CN201711452557 A CN 201711452557A CN 107977038 B CN107977038 B CN 107977038B
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- 238000005070 sampling Methods 0.000 claims abstract description 28
- 239000003990 capacitor Substances 0.000 claims description 53
- 239000013078 crystal Substances 0.000 claims description 17
- 230000008054 signal transmission Effects 0.000 claims description 9
- 238000004088 simulation Methods 0.000 claims description 9
- 238000007689 inspection Methods 0.000 claims description 8
- 239000004973 liquid crystal related substance Substances 0.000 claims description 7
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 230000001105 regulatory effect Effects 0.000 claims description 5
- 230000003287 optical effect Effects 0.000 claims description 2
- 238000010248 power generation Methods 0.000 abstract description 5
- 230000005669 field effect Effects 0.000 description 26
- 238000000034 method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005265 energy consumption Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/625—Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is ac or dc
Abstract
A solar array voltage compensation device belongs to the technical field of solar photovoltaic power generation, and particularly relates to a solar array voltage compensation device. The invention provides a solar array voltage compensation device. The invention comprises a string voltage sampling circuit, a PWM control voltage compensation circuit, a switching value output control circuit, a keyboard circuit, an LCD display screen circuit and a main control CPU circuit, and is structurally characterized in that a sampling signal output port of the string voltage sampling circuit is connected with a sampling signal input port of the main control CPU circuit, a control signal output port of the main control CPU circuit is respectively connected with a control signal input port of the PWM control voltage compensation circuit and a control signal input port of the switching value output control circuit, and a control signal output port of the keyboard circuit is connected with a control signal input port of the main control CPU circuit.
Description
Technical Field
The invention belongs to the technical field of solar photovoltaic power generation, and particularly relates to a solar array voltage compensation device.
Background
The combination of the panels in the photovoltaic array is connected in various forms, and the essence of the combination is that the output voltage of the direct-current end can be improved through the serial connection of the panels, and the output current of the direct-current end can be improved through the parallel connection of the panels. In most photovoltaic power generation systems, photovoltaic panels are connected in series to a higher voltage, and then each series of series branches are connected in parallel to output a larger current. Because the photovoltaic array power generation has a wooden barrel effect, if the voltage of one branch is reduced, the output voltage of all other branches connected in parallel is reduced, so that the output power of the whole array is greatly reduced. The reasons for the drop in the branch voltage mainly include two: the first is a randomness reason, including shadow shielding caused by surrounding obstacles, snow coverage in winter, hidden cracks in the photovoltaic cell panels and the like, which cause irregularity and contingency of the magnitude of the reduction of the string voltage, can cause one or more cell panels to generate no power, pull down the branch voltage and further influence the output power of the whole array; the second is the stationary reason, which, in some cases, due to objective condition constraints, does not allow to keep the number of panels of each series branch uniform, or the different panel specifications, although the number of series is the same, will cause each series branch connected in parallel to have a different operating voltage, the voltage of each branch being pulled down by the branch with the lowest operating voltage. Either cause of voltage drop across the series-connected branches results in each string in the array not being able to operate at the maximum power point, directly resulting in a drop in the overall photovoltaic array power generation. The existing methods for preventing the wooden barrel effect of the photovoltaic array mainly comprise two methods: (1) The loss of power mismatch is reduced by adding the bypass diode and the blocking diode, the method can only work when the voltage of the photovoltaic string is greatly reduced, a plurality of power peak points of the photovoltaic array are caused, MPPT tracking is often caused to fall into a local optimal point, and the array cannot output maximum power; (2) The method solves the problems of high cost, complex installation, high failure rate, high energy consumption of the operation of the optimizers and the like by installing the optimizers on each battery plate.
Disclosure of Invention
The present invention is directed to the above-mentioned problems, and provides a solar array voltage compensation device.
In order to achieve the above purpose, the invention adopts the following technical scheme that the invention comprises a string voltage sampling circuit, a PWM control voltage compensation circuit, a switching value output control circuit, a keyboard circuit, an LCD display screen circuit and a main control CPU circuit, and is structurally characterized in that a sampling signal output port of the string voltage sampling circuit is connected with a sampling signal input port of the main control CPU circuit, a control signal output port of the main control CPU circuit is respectively connected with a control signal input port of the PWM control voltage compensation circuit and a control signal input port of the switching value output control circuit, a control signal output port of the keyboard circuit is connected with a control signal input port of the main control CPU circuit, and a signal transmission port of the LCD display screen circuit is respectively connected with a signal transmission port of the main control CPU circuit and a signal transmission port of the LCD display screen; the control signal input port of the keyboard circuit is connected with the control signal output port of the keyboard.
As a preferable scheme, the string voltage sampling circuit samples the input voltage and the output voltage of each string branch according to a proportion, and analog signals obtained by sampling are changed into digital signals through an AD conversion module in a main control CPU after passing through a voltage follower circuit;
the PWM control voltage compensation circuit is a boost chopper circuit, the output voltage is regulated according to the duty ratio of PWM waveforms, and PWM signals are output by a PWM module in the main control CPU;
the switching value output control circuit outputs a switching value control signal from an IO port of the main control CPU, and controls the intermediate relay after being isolated by the optocoupler, so as to control the working mode of the string branch circuit.
As another preferable scheme, the keyboard circuit and the LCD display screen circuit have the functions of setting control parameters of the compensation device, including inspection interval time, PI regulation parameters and voltage compensation threshold values, and checking the working states of each group of strings and the historical data of each parameter on line through the LCD screen;
the main control CPU circuit diagnoses the working state of each group of strings, calculates the voltage compensation value and performs real-time closed-loop control.
As another preferable scheme, the main control CPU circuit comprises a system clock circuit, a program downloading and on-line simulation circuit and a main control CPU, wherein the main control CPU port is respectively connected with the system clock circuit port and the program downloading and on-line simulation circuit port.
As another preferable scheme, the main control CPU acquires the string voltage signal and outputs a PWM control signal and a switching value control signal.
As another preferable scheme, the main control CPU adopts a PIC18F6520 chip U1.
As another preferable scheme, the system clock circuit comprises a capacitor C5, a capacitor C6 and a crystal oscillator X1, wherein one end of the crystal oscillator X1 is respectively connected with one end of the capacitor C5 and a pin 39 of the crystal oscillator U1, the other end of the capacitor C5 is respectively connected with one end of a ground wire and one end of the capacitor C6, and the other end of the capacitor C6 is respectively connected with the other end of the crystal oscillator X1 and a pin 40 of the crystal oscillator U1.
As another preferable scheme, the capacitors C5 and C6 adopt 18pF capacitors, and the crystal oscillator X1 adopts 20MHz/50PPM crystal oscillator.
As another preferable scheme, the program downloading and online simulation circuit comprises a resistor R22, a resistor R23, a diode D4, a capacitor C4 and a socket J1, wherein one end of the resistor R22 is respectively connected with a power supply VCC and the cathode of the diode D4, the other end of the resistor R22 is respectively connected with one end of the capacitor C4, the anode of the diode D4 and one end of the resistor R23, the other end of the capacitor C4 is grounded, and the other end of the resistor R23 is connected with the 1 pin of the socket J1.
As another preferable scheme, the resistor R22 adopts a 10K ohm resistor, the resistor R23 adopts a 1K ohm resistor, the diode D4 adopts a 1N4181 type diode, and the capacitor C4 adopts a 0.1 mu F capacitor.
As another preferred scheme, the keyboard circuit comprises resistors R28-R32, a resistor RA1 and a socket J2, wherein pins 1-5 of the socket J2 are respectively connected with pins 2-6 of the resistor RA1 and pins 64-60 of the U1, pin 6 of the socket J2 is connected with pin 16 of the U1 through resistor R28, pin 7 of the socket J2 is connected with pin 15 of the U1 through resistor R29, pin 8 of the socket J2 is connected with pin 14 of the U1 through resistor R30, pin 9 of the socket J2 is connected with pin 13 of the U1 through resistor R31, pin 10 of the socket J2 is connected with pin 12 of the U1 through resistor R32, and pin 1 of the resistor RA1 is connected with a power supply VCC.
As another preferable scheme, the resistors R28-R32 adopt 20 ohm resistors, and the resistor RA1 adopts 1K 5 rows.
As another preferable scheme, the LCD display screen circuit comprises resistors R24-R27, an NPN triode Q4 and an LM24064DFC chip J3, wherein pins 12-18 of the J3 are respectively connected with pins 55-49 of U1 correspondingly, pin 19 of the J3 is connected with pin 33 of U1, pin 20 of the J3 is respectively connected with one end of the resistor R26 and pin 4 of the J3 through the resistor R27, and the other end of the resistor R26 is respectively connected with pins 3 of power VCC and J3;
the 21 pin of J3 is connected with the emitter of NPN triode Q4, the collector of NPN triode Q4 is connected with power VCC and one end of resistor R24 respectively, the other end of resistor R24 is connected with one end of resistor R25 and 36 pin of U1 respectively, the other end of resistor R25 is connected with the base of NPN triode Q4;
the pins 22, 1 and 2 of the J3 are grounded, the pin 11 of the J3 is connected with the pin 58 of the U1, the pin 10 of the J3 is connected with the pin 30 of the U1, and the pins 8-5 of the J3 are respectively connected with the pins 32, 31, 34 and 35 of the U1 correspondingly.
As another preferable scheme, the resistors R24 and R25 adopt 820 ohm resistors, the resistor R26 adopts 51K ohm resistor, the resistor R27 adopts 6K ohm resistor, and the NPN triode Q4 adopts a 9014 triode.
As another preferred embodiment, the keyboard of the present invention adopts a5×5 keyboard.
As another preferable mode, the LCD liquid crystal display screen adopts an LCD liquid crystal display screen with 240 multiplied by 64 pixels.
As another preferable scheme, the boost chopper circuit comprises inductors L1-L3, diodes D1-D3, resistors R1-R6, field effect transistors Q1-Q3, capacitors C1-C3 and TLP250F chips U3-U5;
the 3 pin of the U1 is connected with the 2 pin of the U3 through a resistor R1, the 3 pin of the U3 is grounded, the 8 pin of the U3 is connected with a power supply V, the 6 pin of the U3 is respectively connected with the 7 pin of the U3 and one end of a resistor R2, the other end of the resistor R2 is connected with the grid electrode of a field effect tube Q1, the source electrode of the field effect tube Q1 is respectively connected with an AGND end and one end of a capacitor C1, the other end of the capacitor C1 is respectively connected with the Uo1 end, the cathode of a diode D1 and one end of a normally open switch of a relay K1, the other end of the normally open switch of the relay K1 is respectively connected with the Ui1 end and one end of an inductor L1, and the other end of the inductor L1 is respectively connected with the anode of the diode D1 and the drain electrode of the field effect tube Q1;
the 6 pin of U1 is connected with the 2 pin of U4 through a resistor R3, the 3 pin of U4 is grounded, the 8 pin of U4 is connected with a power supply V, the 6 pin of U4 is respectively connected with the 7 pin of U4 and one end of a resistor R4, the other end of the resistor R4 is connected with the grid electrode of a field effect tube Q2, the source electrode of the field effect tube Q2 is respectively connected with an AGND end and one end of a capacitor C2, the other end of the capacitor C2 is respectively connected with the Uo2 end, the cathode of a diode D2 and one end of a normally open switch of a relay K2, the other end of the normally open switch of the relay K2 is respectively connected with the Ui2 end and one end of an inductor L2, and the other end of the inductor L2 is respectively connected with the anode of the diode D2 and the drain electrode of the field effect tube Q2;
the 8 feet of U1 link to each other with the 2 feet of U5 through resistance R5, the 3 feet of U5 are grounded, the 8 feet of U5 connect power V, the 6 feet of U5 link to each other with 7 feet of U5, resistance R6 one end respectively, the other end of resistance R6 links to each other with the grid of field effect tube Q3, the source electrode of field effect tube Q3 links to each other with AGND end respectively, electric capacity C3 one end, the electric capacity C3 other end links to each other with Uo3 end respectively, diode D3's negative pole, relay K3's normally open switch one end, relay K3's normally open switch other end links to each other with Ui3 end respectively, inductance L3 one end, the inductance L3 other end links to each other with diode D3's positive pole, field effect tube Q3's drain electrode respectively.
As another preferable scheme, the inductors L1-L3 adopt 330 mu H inductors, the diodes D1-D3 adopt MUR30100 diodes, the resistors R1, R3 and R5 adopt 300 ohm resistors, the resistors R2, R4 and R6 adopt 1K ohm resistors, the field effect transistors Q1-Q3 adopt KIA12N60H type field effect transistors, and the capacitors C1-C3 adopt 33 mu F capacitors.
As another preferable scheme, the switching value output control circuit comprises a TLP521-4 chip U2, relays K1-K3 and resistors R7-R9, wherein pins 46, 47 and 48 of U1 are respectively and correspondingly connected with pins 6, 4 and 2 of U2, pin 1 of U2 is connected with a power supply VCC through a resistor R7, pin 3 of U2 is connected with the power supply VCC through a resistor R8, and pin 5 of U2 is connected with the power supply VCC through a resistor R9;
the pins 16, 14 and 12 of the U2 are connected with the power supply V, and the pins 15, 13 and 11 of the U2 are respectively connected with one end of the control end of the relay K1, one end of the control end of the relay K2 and one end of the control end of the relay K3, and the other ends of the control end of the relay K1, the control end of the relay K2 and the control end of the relay K3 are connected with the AGND end.
As another preferable scheme, the relays K1-K3 adopt HFE18V-20 type relays, and the resistors R7-R9 adopt 300 ohm resistors.
As another preferable scheme, the string voltage sampling circuit comprises resistors R10-R21 and AD8541 chips CA 1-CA 6, wherein one end of the resistor R10 is connected with the Ui1 end, the other end of the resistor R10 is respectively connected with one end of the resistor R11 and 3 pins of the resistor CA1, the other end of the resistor R11 is connected with the AGND end, and 2 pins of the resistor CA1 are respectively connected with 6 pins of the resistor CA1 and 24 pins of the resistor U1;
one end of a resistor R14 is connected with a Ui2 end, the other end of the resistor R14 is respectively connected with one end of a resistor R15 and the 3 pin of a CA3, the other end of the resistor R15 is connected with an AGND end, and the 2 pin of the CA3 is respectively connected with the 6 pin of the CA3 and the 22 pin of the U1;
one end of a resistor R18 is connected with the Ui3 end, the other end of the resistor R18 is respectively connected with one end of a resistor R19 and the 3 pin of a CA5, the other end of the resistor R19 is connected with the AGND end, and the 2 pin of the CA5 is respectively connected with the 6 pin of the CA5 and the 18 pin of the U1;
one end of a resistor R12 is connected with the Uo1 end, the other end of the resistor R12 is respectively connected with one end of a resistor R13 and the 3 pin of a CA2, the other end of the resistor R13 is connected with the AGND end, and the 2 pin of the CA2 is respectively connected with the 6 pin of the CA2 and the 23 pin of the U1;
one end of a resistor R16 is connected with the Uo2 end, the other end of the resistor R16 is respectively connected with one end of a resistor R17 and the 3 pin of a CA4, the other end of the resistor R17 is connected with the AGND end, and the 2 pin of the CA4 is respectively connected with the 6 pin of the CA4 and the 21 pin of the U1;
one end of the resistor R20 is connected with the Uo3 end, the other end of the resistor R20 is respectively connected with one end of the resistor R21 and the 3 pin of the CA6, the other end of the resistor R21 is connected with the AGND end, and the 2 pin of the CA6 is respectively connected with the 6 pin of the CA6 and the 17 pin of the U1.
In addition, the resistors R10, R14, R18, R12, R16 and R20 adopt 200K ohm resistors, and the resistors R11, R15, R19, R13, R17 and R21 adopt 1K ohm resistors.
In addition, when the invention starts to work, the keyboard is used for setting initial parameters of the system, including the inspection interval time, PI adjusting parameters and voltage compensation threshold U th1 、U th2 K1 is closed, K2-Kn are opened, only the output power of the first path of photovoltaic string is output, and the voltage value U of the first path of string is acquired i1 The method comprises the steps of carrying out a first treatment on the surface of the The voltage value U of each branch when working independently is collected in turn i1 ～U in Selecting the maximum value as a reference value U pref The method comprises the steps of carrying out a first treatment on the surface of the The voltage value U of each group of string branches i And U pref The comparison is made, and for the coincidence (U pref —U i ）<U th1 The corresponding intermediate relay Ki is closed by the branch circuit, so that the voltage compensation circuit does not work, and the power loss is reduced; for non-conforming (U pref —U i ）<U th1 The branch circuit of (1) opens the corresponding intermediate relay Ki, starts the voltage compensation function, and outputs the voltage U of the series branch circuit i And U pref Comparing with U pref PI regulation is carried out for a control target, and the compared regulating quantity is converted into PWM square wave signal with the duty ratio alpha to drive a field effect tube Qi, so that U o Lifting to U pref The method comprises the steps of carrying out a first treatment on the surface of the Acquisition U out Calculate U pref And U out Is a difference in (2); if the difference is greater than U th2 Indicating that the branch still needs compensation voltage, and returning to the beginning of the program for re-execution; if the difference is smaller than U th2 The voltage of each branch of the array is recovered to a normal state, the array enters a timing inspection state, and U is detected at regular intervals pref And U out Whether the difference is greater than a threshold value U th2 If it is greater than threshold U th2 Repeating the above stepsAnd (5) row voltage compensation.
The invention has the beneficial effects that.
The invention comprises a string voltage sampling circuit, a PWM control voltage compensation circuit, a switching value output control circuit, a keyboard circuit, an LCD display screen circuit and a main control CPU circuit, wherein the working state of each string of the photovoltaic array can be detected in real time through the string voltage sampling circuit, and the voltage compensation can be carried out on the photovoltaic string with reduced voltage through the PWM control voltage compensation circuit and the switching value output control circuit, so that the voltage of each string is kept in a normal state, and the wooden barrel effect is avoided.
The invention has simple and convenient installation, low cost, safety and reliability.
When the compensation device is used, the compensation device is connected in series in the branch of the conventional photovoltaic array, the system structure is simple, and the compensation device has good applicability to the series-parallel photovoltaic array. The compensation device has low cost and has great practical value for the operation of the photovoltaic system.
Drawings
The invention is further described below with reference to the drawings and the detailed description. The scope of the present invention is not limited to the following description.
FIG. 1 is a schematic block diagram of a circuit of the present invention;
FIG. 2 is a schematic illustration of the connection of the present invention to a photovoltaic array;
FIGS. 3-1 and 3-2 are schematic diagrams of specific circuits of the present invention;
FIGS. 4-1 and 4-2 are schematic diagrams b of specific circuits of the present invention;
FIG. 5 is a schematic diagram of intelligent voltage compensation according to the present invention;
fig. 6 is a control flow diagram of the present invention.
Detailed Description
As shown in the figure, the invention comprises a string voltage sampling circuit, a PWM control voltage compensation circuit, a switching value output control circuit, a keyboard circuit, an LCD display screen circuit and a main control CPU circuit, wherein a sampling signal output port of the string voltage sampling circuit is connected with a sampling signal input port of the main control CPU circuit, a control signal output port of the main control CPU circuit is respectively connected with a control signal input port of the PWM control voltage compensation circuit and a control signal input port of the switching value output control circuit, a control signal output port of the keyboard circuit is connected with a control signal input port of the main control CPU circuit, and a signal transmission port of the LCD display screen circuit is respectively connected with a signal transmission port of the main control CPU circuit and a signal transmission port of the LCD liquid crystal display screen; the control signal input port of the keyboard circuit is connected with the control signal output port of the keyboard.
The string voltage sampling circuit samples the input voltage and the output voltage of each string branch according to a proportion, and analog signals obtained by sampling are converted into digital signals through an AD conversion module in the main control CPU after passing through the voltage follower circuit;
the PWM control voltage compensation circuit is a boost chopper circuit, the output voltage is regulated according to the duty ratio of PWM waveforms, and PWM signals are output by a PWM module in the main control CPU;
the switching value output control circuit outputs a switching value control signal from an IO port of the main control CPU, and controls the intermediate relay after being isolated by the optical coupler so as to control the working mode of the string branch circuit;
the functions of the keyboard circuit and the LCD display screen circuit are used for setting control parameters of the compensation device, including inspection interval time, PI regulation parameters and voltage compensation threshold values, and checking the working states of each group of strings and the history data of each parameter on line through the LCD screen;
the main control CPU circuit diagnoses the working state of each group of strings, calculates the voltage compensation value and performs real-time closed-loop control.
The compensation device can enable the photovoltaic array to be in a maximum power output state all the time, cannot enable the array output to generate a plurality of power peak points, and cannot influence the tracking performance of the rear end to the maximum power point.
Detecting voltage mismatch by adopting a timing inspection method; determining whether to start a voltage compensation function by judging whether the string voltage drop value exceeds a set threshold value; the switching value output control circuit does not start a voltage compensation function for the branch circuit which does not need voltage regulation, so that the power consumption is reduced. .
The main control CPU circuit comprises a system clock circuit, a program downloading and online simulation circuit and a main control CPU, wherein the main control CPU port is respectively connected with the system clock circuit port and the program downloading and online simulation circuit port.
And the main control CPU collects the string voltage signals and outputs PWM control signals and switching value control signals.
The main control CPU adopts a PIC18F6520 chip U1. The PIC18F6520 chip collects the string voltage signals and outputs PWM control signals and switching value control signals. The PIC18F6520 is adopted as a CPU for signal acquisition, data processing and real-time control, and the internal hardware resources of the chip can meet the intelligent voltage compensation of 6-path strings at most, and if voltage compensation is required to be carried out on more paths of photovoltaic strings at the same time, peripheral circuits can be added or chips with more internal hardware resources can be selected.
The system clock circuit comprises a capacitor C5, a capacitor C6 and a crystal oscillator X1, wherein one end of the crystal oscillator X1 is respectively connected with one end of the capacitor C5 and a pin 39 of the U1, the other end of the capacitor C5 is respectively connected with one end of a ground wire and one end of the capacitor C6, and the other end of the capacitor C6 is respectively connected with the other end of the crystal oscillator X1 and a pin 40 of the U1.
The capacitors C5 and C6 adopt 18pF capacitors, and the crystal oscillator X1 adopts 20MHz/50PPM crystal oscillator.
The program downloading and online simulation circuit comprises a resistor R22, a resistor R23, a diode D4, a capacitor C4 and a socket J1, wherein one end of the resistor R22 is connected with a power supply VCC and the cathode of the diode D4 respectively, the other end of the resistor R22 is connected with one end of the capacitor C4, the anode of the diode D4 and one end of the resistor R23 respectively, the other end of the capacitor C4 is grounded, and the other end of the resistor R23 is connected with the 1 pin of the socket J1.
The resistor R22 adopts a 10K ohm resistor, the resistor R23 adopts a 1K ohm resistor, the diode D4 adopts a 1N4181 type diode, and the capacitor C4 adopts a 0.1 mu F capacitor.
The keyboard circuit comprises resistors R28-R32, a resistor RA1 and a socket J2, wherein pins 1-5 of the socket J2 are respectively connected with pins 2-6 of the resistor RA1 and pins 64-60 of the U1, pin 6 of the socket J2 is connected with pin 16 of the U1 through resistor R28, pin 7 of the socket J2 is connected with pin 15 of the U1 through resistor R29, pin 8 of the socket J2 is connected with pin 14 of the U1 through resistor R30, pin 9 of the socket J2 is connected with pin 13 of the U1 through resistor R31, pin 10 of the socket J2 is connected with pin 12 of the U1 through resistor R32, and pin 1 of the resistor RA1 is connected with a power supply VCC. The keyboard circuit is connected with a5×5 keyboard through a jack J2. The resistors R28-R32 play a role in key anti-shake.
The resistors R28-R32 adopt 20 ohm resistors, and the resistor RA1 adopts 1K 5 rows of resistors.
The LCD display screen circuit comprises resistors R24-R27, NPN triode Q4 and LM24064DFC chip J3, wherein pins 12-18 of the J3 are respectively and correspondingly connected with pins 55-49 of the U1, pin 19 of the J3 is connected with pin 33 of the U1, pin 20 of the J3 is respectively connected with one end of the resistor R26 and pin 4 of the J3 through the resistor R27, and the other end of the resistor R26 is respectively connected with pins 3 of the power sources VCC and J3;
the 21 pin of J3 is connected with the emitter of NPN triode Q4, the collector of NPN triode Q4 is connected with power VCC and one end of resistor R24 respectively, the other end of resistor R24 is connected with one end of resistor R25 and 36 pin of U1 respectively, the other end of resistor R25 is connected with the base of NPN triode Q4;
the pins 22, 1 and 2 of the J3 are grounded, the pin 11 of the J3 is connected with the pin 58 of the U1, the pin 10 of the J3 is connected with the pin 30 of the U1, and the pins 8-5 of the J3 are respectively connected with the pins 32, 31, 34 and 35 of the U1 correspondingly. The 240×64 pixel LCD liquid crystal display is connected through the jack J3.
The resistors R24 and R25 are 820 ohms, the resistor R26 is 51K ohms, the resistor R27 is 6K ohms, and the NPN triode Q4 is a 9014 triode.
The keyboard adopts a5×5 keyboard.
The LCD liquid crystal display screen adopts an LCD liquid crystal display screen with 240 multiplied by 64 pixels.
The boost chopper circuit comprises inductors L1-L3, diodes D1-D3, resistors R1-R6, field effect transistors Q1-Q3, capacitors C1-C3 and TLP250F chips U3-U5;
the 3 pin of the U1 is connected with the 2 pin of the U3 through a resistor R1, the 3 pin of the U3 is grounded, the 8 pin of the U3 is connected with a power supply V, the 6 pin of the U3 is respectively connected with the 7 pin of the U3 and one end of a resistor R2, the other end of the resistor R2 is connected with the grid electrode of a field effect tube Q1, the source electrode of the field effect tube Q1 is respectively connected with an AGND end and one end of a capacitor C1, the other end of the capacitor C1 is respectively connected with the Uo1 end, the cathode of a diode D1 and one end of a normally open switch of a relay K1, the other end of the normally open switch of the relay K1 is respectively connected with the Ui1 end and one end of an inductor L1, and the other end of the inductor L1 is respectively connected with the anode of the diode D1 and the drain electrode of the field effect tube Q1;
the 6 pin of U1 is connected with the 2 pin of U4 through a resistor R3, the 3 pin of U4 is grounded, the 8 pin of U4 is connected with a power supply V, the 6 pin of U4 is respectively connected with the 7 pin of U4 and one end of a resistor R4, the other end of the resistor R4 is connected with the grid electrode of a field effect tube Q2, the source electrode of the field effect tube Q2 is respectively connected with an AGND end and one end of a capacitor C2, the other end of the capacitor C2 is respectively connected with the Uo2 end, the cathode of a diode D2 and one end of a normally open switch of a relay K2, the other end of the normally open switch of the relay K2 is respectively connected with the Ui2 end and one end of an inductor L2, and the other end of the inductor L2 is respectively connected with the anode of the diode D2 and the drain electrode of the field effect tube Q2;
the 8 feet of U1 link to each other with the 2 feet of U5 through resistance R5, the 3 feet of U5 are grounded, the 8 feet of U5 connect power V, the 6 feet of U5 link to each other with 7 feet of U5, resistance R6 one end respectively, the other end of resistance R6 links to each other with the grid of field effect tube Q3, the source electrode of field effect tube Q3 links to each other with AGND end respectively, electric capacity C3 one end, the electric capacity C3 other end links to each other with Uo3 end respectively, diode D3's negative pole, relay K3's normally open switch one end, relay K3's normally open switch other end links to each other with Ui3 end respectively, inductance L3 one end, the inductance L3 other end links to each other with diode D3's positive pole, field effect tube Q3's drain electrode respectively.
The main loss of the compensation device circuit is the on-off loss of a switching tube, and the on-off loss is very small compared with the output power of a photovoltaic array and can be ignored.
L1-L3, D1-D3, R1-R6, Q1-Q3, C1-C3 and U3-U5 form a three-way boost chopper circuit, and a PWM generator contained in PIC18F6520 outputs three independent PWM square wave signals through three pins 3, 6 and 8, so that the three-way boost chopper circuit is independently controlled.
The inductor L1-L3 adopts 330 mu H inductor, the diode D1-D3 adopts MUR30100 diode, the resistor R1, R3 and R5 adopt 300 ohm resistor, the resistor R2, R4 and R6 adopt 1K ohm resistor, the field effect tube Q1-Q3 adopts KIA12N60H type field effect tube, and the capacitor C1-C3 adopts 33 mu F capacitor.
The switching value output control circuit comprises a TLP521-4 chip U2, relays K1-K3 and resistors R7-R9, wherein pins 46, 47 and 48 of U1 are respectively and correspondingly connected with pins 6, 4 and 2 of U2, pin 1 of U2 is connected with a power supply VCC through a resistor R7, pin 3 of U2 is connected with the power supply VCC through a resistor R8, and pin 5 of U2 is connected with the power supply VCC through a resistor R9;
the pins 16, 14 and 12 of the U2 are connected with the power supply V, and the pins 15, 13 and 11 of the U2 are respectively connected with one end of the control end of the relay K1, one end of the control end of the relay K2 and one end of the control end of the relay K3, and the other ends of the control end of the relay K1, the control end of the relay K2 and the control end of the relay K3 are connected with the AGND end.
The switching value output by the three pins 46, 47 and 48 of the PIC18F6520 drives the optocoupler, so that three intermediate relays K1-K3 are controlled.
The relays K1-K3 are HFE18V-20 relays, and the resistors R7-R9 are 300 ohm resistors.
The series voltage sampling circuit comprises resistors R10-R21 and AD8541 chips CA 1-CA 6, one end of the resistor R10 is connected with the Ui1 end, the other end of the resistor R10 is respectively connected with one end of the resistor R11 and the 3 pin of the resistor CA1, the other end of the resistor R11 is connected with the AGND end, and the 2 pin of the resistor CA1 is respectively connected with the 6 pin of the resistor CA1 and the 24 pin of the resistor U1;
one end of a resistor R14 is connected with a Ui2 end, the other end of the resistor R14 is respectively connected with one end of a resistor R15 and the 3 pin of a CA3, the other end of the resistor R15 is connected with an AGND end, and the 2 pin of the CA3 is respectively connected with the 6 pin of the CA3 and the 22 pin of the U1;
one end of a resistor R18 is connected with the Ui3 end, the other end of the resistor R18 is respectively connected with one end of a resistor R19 and the 3 pin of a CA5, the other end of the resistor R19 is connected with the AGND end, and the 2 pin of the CA5 is respectively connected with the 6 pin of the CA5 and the 18 pin of the U1;
one end of a resistor R12 is connected with the Uo1 end, the other end of the resistor R12 is respectively connected with one end of a resistor R13 and the 3 pin of a CA2, the other end of the resistor R13 is connected with the AGND end, and the 2 pin of the CA2 is respectively connected with the 6 pin of the CA2 and the 23 pin of the U1;
one end of a resistor R16 is connected with the Uo2 end, the other end of the resistor R16 is respectively connected with one end of a resistor R17 and the 3 pin of a CA4, the other end of the resistor R17 is connected with the AGND end, and the 2 pin of the CA4 is respectively connected with the 6 pin of the CA4 and the 21 pin of the U1;
one end of the resistor R20 is connected with the Uo3 end, the other end of the resistor R20 is respectively connected with one end of the resistor R21 and the 3 pin of the CA6, the other end of the resistor R21 is connected with the AGND end, and the 2 pin of the CA6 is respectively connected with the 6 pin of the CA6 and the 17 pin of the U1.
R10-R21 and CA 1-CA 6 form six paths of voltage sampling circuits for respectively collecting input end voltages U of three paths of photovoltaic strings i And an output voltage U after passing through the voltage compensation circuit o The voltage signals are input to an AD conversion module in the CPU by pins 17, 18 and 21-24 of the PIC18F6520 for analog-to-digital conversion.
The resistors R10, R14, R18, R12, R16 and R20 adopt 200K ohm resistors, and the resistors R11, R15, R19, R13, R17 and R21 adopt 1K ohm resistors.
As shown in FIGS. 5-6, when the invention starts to work, the keyboard is used to set the initial parameters of the system including the inspection interval time (when one path of compensation is controlled, the CPU does not receive the detection signals of the other paths, the device saves electricity and has low energy consumption), the PI regulation parameters and the voltage compensation threshold U th1 、U th2 K1 is closed, K2-Kn are opened, only the output power of the first path of photovoltaic string is output, and the voltage value U of the first path of string is acquired i1 The method comprises the steps of carrying out a first treatment on the surface of the According to the method, the voltage value U of each branch when working independently is collected in turn i1 ～U in Selecting the maximum value as a reference value U pref The method comprises the steps of carrying out a first treatment on the surface of the The voltage value U of each group of string branches i And U pref The comparison is made, and for the coincidence (U pref —U i ）<U th1 The corresponding intermediate relay Ki is closed by the branch circuit, so that the voltage compensation circuit does not work, and the power loss is reduced; for non-conforming (U pref —U i ）<U th1 The branch circuit of (1) opens the corresponding intermediate relay Ki, starts the voltage compensation function, and outputs the voltage U of the series branch circuit i And U pref Comparing with U pref PI regulation is carried out for a control target, and the compared regulating quantity is converted into PWM square wave signal with the duty ratio alpha to drive a field effect tube Qi, so that U o Lifting to U pref The method comprises the steps of carrying out a first treatment on the surface of the CollectingU-shaped collector out Calculate U pref And U out Is a difference in (2); if the difference is greater than U th2 Indicating that the branch still needs compensation voltage, and returning to the beginning of the program for re-execution; if the difference is smaller than U th2 The voltage of each branch of the array is recovered to a normal state, the array enters a timing inspection state, and U is detected at regular intervals pref And U out Whether the difference is greater than a threshold value U th2 If it is greater than threshold U th2 The above steps are repeated for voltage compensation.
When the photovoltaic compensation device is used, the photovoltaic compensation device is only required to be connected between the photovoltaic group string and the next-stage equipment in series, and the output end of each group string is connected with the Ui1 end, the Ui2 end and the Ui3 end of the photovoltaic compensation device. The output end Uout end (Uo 1 end, uo2 end, uo3 end) of the compensation device is the output end of the photovoltaic array after confluence, namely the total output power of the photovoltaic array obtained by carrying out voltage compensation on each group of strings and confluence, and can be connected with a photovoltaic grid-connected inverter, an off-grid inverter, a charge-discharge controller and the like (as shown in figure 2).
It should be understood that the foregoing detailed description of the present invention is provided for illustration only and is not limited to the technical solutions described in the embodiments of the present invention, and those skilled in the art should understand that the present invention may be modified or substituted for the same technical effects; as long as the use requirement is met, the invention is within the protection scope of the invention.
Claims (5)
1. The solar array voltage compensation device comprises a string voltage sampling circuit, a PWM control voltage compensation circuit, a switching value output control circuit, a keyboard circuit, an LCD display screen circuit and a main control CPU circuit, and is characterized in that a sampling signal output port of the string voltage sampling circuit is connected with a sampling signal input port of the main control CPU circuit, a control signal output port of the main control CPU circuit is respectively connected with a control signal input port of the PWM control voltage compensation circuit and a control signal input port of the switching value output control circuit, a control signal output port of the keyboard circuit is connected with a control signal input port of the main control CPU circuit, and a signal transmission port of the LCD display screen circuit is respectively connected with a signal transmission port of the main control CPU circuit and a signal transmission port of an LCD liquid crystal display screen; the control signal input port of the keyboard circuit is connected with the control signal output port of the keyboard;
the main control CPU circuit comprises a system clock circuit, a program downloading and online simulation circuit and a main control CPU, wherein a main control CPU port is respectively connected with the system clock circuit port and the program downloading and online simulation circuit port;
the main control CPU adopts a PIC18F6520 chip U1;
the system clock circuit comprises a capacitor C5, a capacitor C6 and a crystal oscillator X1, wherein one end of the crystal oscillator X1 is respectively connected with one end of the capacitor C5 and a pin 39 of the U1, the other end of the capacitor C5 is respectively connected with one end of a ground wire and one end of the capacitor C6, and the other end of the capacitor C6 is respectively connected with the other end of the crystal oscillator X1 and a pin 40 of the U1;
the program downloading and online simulation circuit comprises a resistor R22, a resistor R23, a diode D4, a capacitor C4 and a socket J1, wherein one end of the resistor R22 is connected with a power supply VCC and the cathode of the diode D4 respectively, the other end of the resistor R22 is connected with one end of the capacitor C4, the anode of the diode D4 and one end of the resistor R23 respectively, the other end of the capacitor C4 is grounded, and the other end of the resistor R23 is connected with the 1 pin of the socket J1;
the keyboard circuit comprises resistors R28-R32, a resistor RA1 and a socket J2, wherein pins 1-5 of the socket J2 are respectively connected with pins 2-6 of the resistor RA1 and pins 64-60 of the U1 correspondingly, pin 6 of the socket J2 is connected with pin 16 of the U1 through resistor R28, pin 7 of the socket J2 is connected with pin 15 of the U1 through resistor R29, pin 8 of the socket J2 is connected with pin 14 of the U1 through resistor R30, pin 9 of the socket J2 is connected with pin 13 of the U1 through resistor R31, pin 10 of the socket J2 is connected with pin 12 of the U1 through resistor R32, and pin 1 of the resistor RA1 is connected with a power supply VCC;
the string voltage sampling circuit samples the input voltage and the output voltage of each string branch according to a proportion, and analog signals obtained by sampling are converted into digital signals through an AD conversion module in the main control CPU after passing through the voltage follower circuit;
the PWM control voltage compensation circuit is a boost chopper circuit, the output voltage is regulated according to the duty ratio of PWM waveforms, and PWM signals are output by a PWM module in the main control CPU;
the switching value output control circuit outputs a switching value control signal from an IO port of the main control CPU, and controls the intermediate relay after being isolated by the optical coupler so as to control the working mode of the string branch circuit;
the series voltage sampling circuit comprises resistors R10-R21 and AD8541 chips CA 1-CA 6, one end of the resistor R10 is connected with the Ui1 end, the other end of the resistor R10 is respectively connected with one end of the resistor R11 and the 3 pin of the resistor CA1, the other end of the resistor R11 is connected with the AGND end, and the 2 pin of the resistor CA1 is respectively connected with the 6 pin of the resistor CA1 and the 24 pin of the resistor U1;
one end of a resistor R14 is connected with a Ui2 end, the other end of the resistor R14 is respectively connected with one end of a resistor R15 and the 3 pin of a CA3, the other end of the resistor R15 is connected with an AGND end, and the 2 pin of the CA3 is respectively connected with the 6 pin of the CA3 and the 22 pin of the U1;
one end of a resistor R18 is connected with the Ui3 end, the other end of the resistor R18 is respectively connected with one end of a resistor R19 and the 3 pin of a CA5, the other end of the resistor R19 is connected with the AGND end, and the 2 pin of the CA5 is respectively connected with the 6 pin of the CA5 and the 18 pin of the U1;
one end of a resistor R12 is connected with the Uo1 end, the other end of the resistor R12 is respectively connected with one end of a resistor R13 and the 3 pin of a CA2, the other end of the resistor R13 is connected with the AGND end, and the 2 pin of the CA2 is respectively connected with the 6 pin of the CA2 and the 23 pin of the U1;
one end of a resistor R16 is connected with the Uo2 end, the other end of the resistor R16 is respectively connected with one end of a resistor R17 and the 3 pin of a CA4, the other end of the resistor R17 is connected with the AGND end, and the 2 pin of the CA4 is respectively connected with the 6 pin of the CA4 and the 21 pin of the U1;
one end of the resistor R20 is connected with the Uo3 end, the other end of the resistor R20 is respectively connected with one end of the resistor R21 and the 3 pin of the CA6, the other end of the resistor R21 is connected with the AGND end, and the 2 pin of the CA6 is respectively connected with the 6 pin of the CA6 and the 17 pin of the U1.
2. The solar array voltage compensation device according to claim 1, wherein the keyboard circuit and the LCD display screen circuit have the functions of setting control parameters of the compensation device, including inspection interval time, PI adjustment parameters and voltage compensation threshold values, and checking the working state of each group of strings and the history data of each parameter on line through the LCD screen;
the main control CPU circuit diagnoses the working state of each group of strings, calculates the voltage compensation value and performs real-time closed-loop control.
3. The solar array voltage compensation device according to claim 1, wherein the main control CPU collects a string voltage signal and outputs a PWM control signal and a switching value control signal.
4. The solar array voltage compensation device according to claim 1, wherein the capacitors C5 and C6 are 18pF capacitors, and the crystal oscillator X1 is a 20MHz/50PPM crystal oscillator.
5. The solar array voltage compensation device according to claim 1, wherein the resistor R22 is a 10K ohm resistor, the resistor R23 is a 1K ohm resistor, the diode D4 is a 1N4181 diode, and the capacitor C4 is a 0.1 μf capacitor.
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| CN108711884A (en) * | 2018-05-30 | 2018-10-26 | 沈阳工程学院 | A kind of solar grid-connected power station micro-energy recovery system |
| CN108448639A (en) * | 2018-05-30 | 2018-08-24 | 沈阳工程学院 | Solar grid-connected power generation micro-energy smartphone device |
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