CN107967928B - Flash memory chip life prediction method based on mathematical model - Google Patents
Flash memory chip life prediction method based on mathematical model Download PDFInfo
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- G11—INFORMATION STORAGE
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- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
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- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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- G—PHYSICS
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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Abstract
The invention belongs to a flash memory chip life prediction technology, and particularly relates to a flash memory chip life prediction method based on a mathematical model. The method comprises the steps of firstly collecting physical information and service life information of a sample flash memory chip through a flash memory chip testing system, then carrying out operation processing on data information obtained through testing by using an intelligent algorithm to obtain a flash memory chip service life prediction model, finally obtaining the physical information of the flash memory chip to be predicted through a small amount of testing, and inputting the physical information into the prediction model to obtain a predicted service life value of the flash memory chip. The flash memory sample testing method provided by the invention adopts the random data with the constraint as the testing data set for testing, so that the data operation in the actual use process of the flash memory chip can be more effectively simulated, and the obtained flash memory physical information and the service life information have higher value.
Description
Technical Field
The invention belongs to a flash memory chip life prediction technology, and particularly relates to a flash memory chip life prediction method based on a mathematical model.
Background
In the modern electronic information industry, memories have been very important as carriers for storing data in electronic devices. Currently, the memories on the market are mainly divided into: volatile memory and non-volatile memory. The flash memory chip is a nonvolatile memory, can store data for a long time after power failure, and has the advantages of high data transmission speed, low production cost, large storage capacity and the like, so the flash memory chip is widely applied to electronic equipment.
At present, due to continuous progress of semiconductor manufacturing processes, inherent errors in flash memory chips become more and more serious due to reduction of distances between memory cells and reduction of thicknesses of oxide layers, the reliability requirements of the flash memory chips cannot be met by a traditional error correction code method, and the reliability problem of the flash memory becomes an important subject in the current memory research field. The service life of the flash memory represents the number of times that the flash memory can perform operations before failure, and is the most important parameter index of the flash memory chip. The residual service life of the flash memory is predicted, so that a user of the flash memory storage device can know the loss state of the memory during the use of the device, and the data loss caused by the failure of a memory unit is avoided. Meanwhile, the user of the memory can change the strategy of storing data according to the predicted residual life information of the flash memory and effectively utilize the flash memory chip to store the data.
Disclosure of Invention
The technical problem of the invention is mainly solved by the following technical scheme:
a flash memory chip life prediction method based on a mathematical model is characterized in that a life prediction value of a flash memory chip is predicted according to one physical quantity or a combination of several physical quantities of the flash memory chip. The flash memory chip physical quantity comprises: programming time, reading time, erasing time, programming current, reading current, erasing current, threshold voltage distribution and error rate of the flash memory chip. The method comprises the following specific steps:
and 3, testing the flash memory life prediction model, taking the physical quantity of the flash memory chip required by the prediction model as the input of the life prediction model, and calculating the output value of the life prediction model to predict the residual life value of the target flash memory product.
Preferably, in the step 1, the sample flash memory must be the same type of flash memory chip under the same manufacturing process; the same number of chip samples are randomly drawn from different batches of chips to ensure sample diversity. The sampling batch is selected randomly, the number of samples can be one percent of the total amount of the flash memory chips of the sampled batch, and the flash memory test system comprises an upper computer test control system and a flash memory control module. The upper computer testing system is realized by writing a program system through a computer language; the flash memory control module is realized through an FPGA.
Preferably, in step 1, the flash memory chip physical information includes: the flash memory chip comprises programming time, reading time, erasing time, programming current, reading current, erasing current, threshold voltage distribution and error rate data information of blocks in the flash memory chip from the beginning of use to the period of abnormal use. In the step 2, the input variable of the mathematical mapping relation for predicting the flash memory life is one or a combination of several of the above physical information. In step 1, the lifetime information of the flash memory chip is the number of program/erase operation cycles experienced by the flash memory chip from the beginning of use to the period of abnormal use.
Preferably, the
The method for acquiring the programming time of the storage block of the flash memory chip comprises the following steps: setting a programming time recording module in a flash memory test system; the programming time recording module records the passed clock period when the flash memory starts to write data operation and stops recording the clock period number after receiving a data programming completion mark returned by the flash memory chip; the program time value is the clock cycle duration times the number of program clock cycles.
The method for acquiring the erasing time and the programming time of the memory block of the flash memory chip comprises the following steps: and recording the number of clock cycles of the erasing operation by an erasing time recording module in the test system, wherein the erasing time value is the duration of the clock cycles multiplied by the number of erasing clock cycles. The method for acquiring the threshold voltage distribution of the storage unit of the flash memory chip comprises the following steps: the test system sends a READ-RETRY command set to the flash memory chip to gradually change the READ reference voltage of the flash memory and simultaneously READ data and count threshold voltage distribution according to the READ data values.
The flash memory chip memory block error rate acquisition mode is as follows: the test system executes read data operation on the flash memory chip to read data from the flash memory, compares the read data with the written test data to count the number of error data, and the error rate is the number of errors divided by the total number of data.
Preferably, in step 1, the step of testing and collecting the physical information and the lifetime information of the flash memory chip includes:
and 5.1, randomly extracting sample chips from the flash memory chip set, and connecting the sample flash memory chips with the test system.
And 5.2, randomly selecting a storage block from each sample flash memory chip, sending a test data set to the flash memory storage block through the test system, and executing data writing operation on the flash memory storage block.
Step 5.3, after the test data vector is sent, keeping the data stored in the flash memory storage block for a period of time, wherein the storage time is determined according to the type of the flash memory chip; the test system executes data reading operation on the flash memory chip, compares the read data with the sent test data, records and stores error data information, and does not store the error data information if the error data information does not exist; and after the error information is stored, the data erasing operation is executed on the flash memory chip through the test system.
Step 5.4, repeatedly executing the operations of the step 5.2 and the step 5.3, and recording the times of the operations of the step 5.2 and the step 5.3; when the operation times reach a set value, the test system records the duration of data writing operation of each storage block of the sample flash memory in the last step 5.2 and stores the recorded duration information; meanwhile, the test system records the duration of the operation of erasing data of each memory block of the sample flash memory in the last step 5.3 operation and saves the recorded duration information.
Step 5.5, measuring the threshold voltage distribution of the flash memory chip unit through the test system, and recording and storing the threshold voltage distribution information of the unit; this step is optional and is not included in the testing step if the predicted object does not have READ-RETRY functionality.
And 5.6, counting and storing the data error rate information of each storage block of the flash memory chip by the test system.
Step 5.7, repeating the step 5.4 to the step 5.6 until the flash memory chip reaches the service life limit; the test system counts the number of program/erase operation cycles of the flash memory chip.
In the present invention, step 2 is an intelligent algorithm using a genetic programming algorithm as a mathematical model, and the intelligent algorithm in the present invention is not limited to this algorithm. The flash life value refers to the number of program/erase cycles that a flash product can perform before failing, and the specific steps include:
6.1, initializing a life prediction function set by a computer program; and setting a life prediction function screening equation.
6.2, substituting the test data into each function in the life prediction function set; calculating a function result, namely a life prediction value of the flash memory chip; substituting the service life predicted value of the flash memory chip obtained by calculation and the actual service life value corresponding to the test data into a fitness equation, and screening a service life prediction function according to the calculation result of the fitness equation.
And 6.3, generating a new function set by using a gene programming method on the basis of the screened life prediction function set.
Step 6.4, the operation of the step 6.2 and the operation of the step 6.3 are repeatedly executed on the new function set, and the operation is terminated when the operation times reach the set upper limit value; the upper limit is set according to the predicted demand.
And 6.5, selecting a function with the best matching degree between the predicted value and the actual life value from the set to obtain a life prediction mathematical model.
The life prediction function in the step 6.1 comprises an operator, a coefficient and an input variable; the coefficient is a constant randomly generated by a computer program, and the input variables are a programming time, an erasing time, threshold voltage distribution and an error rate test data set, wherein the threshold voltage distribution is an optional input variable; one type of the test data set represents one input variable, and the number of the input variables contained in the function can be set according to the prediction requirement. The set of life prediction functions is implemented in the form of a matrix.
Wherein, the fitness equation in step 6.2 refers to the weighted sum of the absolute values of the differences between the predicted flash life values and the test values. The fitness equation is specifically expressed as: f ═ ω1|A1-B1|+ω2|A2-B2|+…+ωn|An-BnL, |; wherein Ai represents a predicted value; bi is an actual value; ω i is a weight, and the value of ω i is greater than 0 and less than or equal to 1; n is the total number of samples.
The operation of the new set of functions described in step 6.3 includes: crossover, mutation and reproduction operations of the functions. The cross operation of the function is specifically to exchange nodes of the tree structure function, and the function obtained after exchange is used as a new function set member. Mutation operation randomly generates functions through a computer program, and replaces the expression branches of the parent functions with the randomly generated functions to obtain new child functions. The gene programming propagation operation is to copy the function meeting the requirement after the selection operation according to a certain probability, and the copied function is taken as a new child.
Therefore, the invention has the following advantages: 1. the flash memory sample testing method provided by the invention adopts the random data with the constraint as the testing data set for testing, so that the data operation in the actual use process of the flash memory chip can be more effectively simulated, and the obtained flash memory physical information and the service life information have higher value. 2. The invention takes various reliability parameters as the input of the life prediction model, and the accuracy of the predicted life value is higher compared with the life prediction model which only takes one parameter as the basis. 3. The invention provides a method for predicting the service life of a flash memory based on the advanced intelligent algorithm modeling technology in the field of computers at present; compared with the prior art, the method has the advantages that the service life value of the flash memory is predicted by establishing a flash memory chip service life prediction mathematical model through an intelligent algorithm on the basis of experimental data.
Drawings
Fig. 1 is a schematic flow chart of a method for predicting the lifetime of a flash memory chip based on a mathematical model according to an embodiment of the present invention.
Fig. 2 is a flowchart of a method for testing reliability of a flash memory according to an embodiment of the present invention.
FIG. 3 is a block diagram of a flash memory test system according to an embodiment of the present invention.
FIG. 4 is a flow chart of modeling a flash life prediction model based on gene programming according to an embodiment of the present invention.
Fig. 5 is a diagram illustrating an exemplary structure of a life prediction function used in the embodiment of the present invention.
FIG. 6 is a diagram illustrating an exemplary form of a matrix of lifetime prediction functions in an embodiment of the present invention.
FIG. 7 is a diagram showing an example of crossover operation of gene programming in the example of the present invention.
FIG. 8 is a diagram showing an example of a gene programming mutation operation in the example of the present invention.
FIG. 9 is a diagram showing an example of a gene-programmed propagation operation in the example of the present invention.
Detailed Description
The technical scheme of the invention is further specifically described by the following embodiments and the accompanying drawings.
Example (b):
in order that the above objects, features and advantages of the present invention will become more apparent, a detailed description thereof will be given below with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a schematic diagram of a process for predicting the lifetime of a flash memory chip according to the present invention, wherein the process for predicting the lifetime of a flash memory chip is applicable to all types of flash memory chips, and the following explains fig. 1 in detail by taking one type of flash memory chip product as an embodiment.
In this embodiment, a multi-level cell NAND flash (MLC NAND flash) product in a certain manufacturing process is used as a test object and a life prediction object. As shown in step S01 of fig. 1, samples are extracted from the flash product set according to the following rules: the sample flash memory is the same type of flash memory chip under the same manufacturing process; the same number of chip samples are randomly drawn from different batches of chips to ensure sample diversity. The sampling batches are selected randomly, and the number of samples can be one percent of the total number of the sampled batches of flash memory chips.
And step S02, connecting the sample flash memory chip with the flash memory test system, starting the test, and collecting the physical information and the life information of the flash memory chip required by establishing the flash memory chip life prediction model. The flash memory chip physical information includes: data information (threshold voltage distribution is optional physical information) in which the program time, erase time, threshold voltage distribution, and error rate of a block in the flash memory chip change under an increasing condition of a program/erase cycle from the start of use to the period of abnormal use.
The method for acquiring the programming time of the storage block of the flash memory chip comprises the following steps: setting a programming time recording module in a flash memory test system; the programming time recording module records the passed clock period when the flash memory starts to write data operation and stops recording the clock period number after receiving a data programming completion mark returned by the flash memory chip; the program time value is the clock cycle duration times the number of program clock cycles.
The method for obtaining the erasing time of the storage block of the flash memory chip is similar to the method for obtaining the programming time, an erasing time recording module in a test system records the number of clock cycles of the continuous erasing operation, and the erasing time value is the time of the duration of the clock cycles multiplied by the number of the erasing clock cycles. The method for acquiring the threshold voltage distribution of the storage unit of the flash memory chip comprises the following steps: the test system sends a READ-RETRY command set to the flash memory chip to gradually change the READ reference voltage of the flash memory and simultaneously READ data and count threshold voltage distribution according to the READ data values.
The flash memory chip memory block error rate acquisition mode is as follows: the test system executes read data operation on the flash memory chip to read data from the flash memory, compares the read data with the written test data to count the number of error data, and the error rate is the number of errors divided by the total number of data.
The flash memory testing method adopted in step S02 is as shown in fig. 2. According to fig. 2, the specific steps of the flash memory test are as follows:
(1) and randomly extracting sample chips from the flash memory chip set, and connecting the sample flash memory chips with the test system.
(2) And randomly selecting a storage block from each sample flash memory chip, sending a test data set to the flash memory storage block through a test system, and executing data writing operation on the flash memory storage block.
(3) After the test data vector is sent, the data stored in the flash memory storage block is kept for a period of time, and the storage time is determined according to the type of the flash memory chip; the test system executes data reading operation on the flash memory chip, compares the read data with the sent test data, records and stores error data information, and does not store the error data information if the error data information does not exist; and after the error information is stored, the data erasing operation is executed on the flash memory chip through the test system.
(4) Repeatedly executing the operations of the step (2) and the step (3), and recording the times of the operations of the step (2) and the step (3); when the operation times reach a set value, the test system records the duration of data writing operation of each storage block of the sample flash memory in the last operation of the step (2) and stores the recorded duration information; meanwhile, the test system records the duration of the operation of erasing data of each memory block of the sample flash memory in the last operation of the step (3) and saves the recorded duration information.
(5) Measuring the threshold voltage distribution of the flash memory chip unit through a test system, and recording and storing the threshold voltage distribution information of the unit; this step is optional and is not included in the testing step if the predicted object does not have READ-RETRY functionality.
(6) The test system counts and stores the data error rate information of each storage block of the flash memory chip.
(7) Repeating the steps (4) to (6) until the flash memory chip reaches the service life limit; the test system counts the number of program/erase operation cycles of the flash memory chip.
The flash memory test system used in step S02 has a structure as shown in fig. 3, and mainly includes an upper computer test control system and a flash memory control module. The upper computer testing system is realized by writing a program system through a computer language; the flash memory control module is realized through an FPGA.
Step S03, processing data through an intelligent algorithm to establish a mathematical model, taking physical information obtained through testing as an input variable of a mathematical mapping relation in the algorithm, and taking a life prediction value of a flash memory chip as an output variable of the mathematical mapping relation; in this embodiment, a genetic programming algorithm is used as an intelligent algorithm for establishing a mathematical model, and the intelligent algorithm described in the present invention is not limited to this algorithm. The flash life value refers to the number of program/erase cycles that a flash product can perform before failing.
In step S03 of this embodiment, a process for establishing a flash life prediction model using a genetic programming algorithm is shown in fig. 4. According to fig. 4, the specific steps of establishing the flash memory life prediction model are as follows:
(1) initializing a life prediction function set by a computer program; and setting a life prediction function screening equation.
(2) Substituting the test data into each function in the life prediction function set; calculating a function result, namely a life prediction value of the flash memory chip; substituting the service life predicted value of the flash memory chip obtained by calculation and the actual service life value corresponding to the test data into a fitness equation, and screening a service life prediction function according to the calculation result of the fitness equation.
(3) And on the basis of the screened life prediction function set, generating a new function set by using a gene programming method.
(4) Repeatedly executing the operations of the step (2) and the step (3) on the new function set, and stopping the operations when the operation times reach the set upper limit value; the upper limit is set according to the predicted demand.
(5) And selecting a function with the best matching degree between the predicted value and the actual life value from the set to obtain a life prediction mathematical model.
The data processing operation required for establishing the flash memory chip life prediction model is realized by a computer program, and the used computer language is not limited to a certain computer language.
The expression pattern of the life prediction function in step (1) according to the definition of gene programming is shown in FIG. 5. The function comprises an operator, a coefficient and an input variable; wherein the coefficient is a constant randomly generated by a computer program, and the input variables are several test data sets of programming time, erasing time, threshold voltage distribution and error rate (the threshold voltage distribution is an optional input variable); one type of the test data set represents one input variable, and the number of the input variables contained in the function can be set according to the prediction requirement. The computer program may implement the set of lifetime prediction functions in the form of a matrix, as shown in fig. 6 in particular.
And (3) the fitness equation in the step (2) refers to the weighted sum of absolute values of the differences between the predicted flash life values and the test values. The fitness equation is specifically expressed as: f ═ ω1|A1-B1|+ω2|A2-B2|+…+ωn|An-BnL, |; wherein, the fitness equation represents a symbol of F; ai represents a predicted value; bi is an actual value; ω i is a weight, and the value of ω i is greater than 0 and less than or equal to 1; n is the total number of samples.
The operation of the new set of functions in step (3) comprises, according to the definition of gene programming: crossover, mutation and reproduction operations of the functions. The cross operation of the function is as shown in fig. 7, specifically, the cross operation is to exchange nodes of a tree structure function, and the function obtained after the exchange is used as a new function set member. Mutation operation the mutation operation is illustrated in figure 8, where a computer program randomly generates functions, and replaces the expression branches of parent functions with the randomly generated functions to obtain new child functions. The schematic diagram of the gene programming propagation operation is shown in fig. 9, the propagation operation copies the function meeting the requirement after the selection operation according to a certain probability, and the copied function is used as a new child.
In the present invention, experimental data are divided into two groups: a training data set and a validation data set. The invention adopts a cross validation method to train a mathematical model and divides experimental data into 5 groups. Of which 4 were used for training and 1 for validation. Each sub-experience data set will be verified once.
Step S04, the life prediction model is tested using the validation data set. In the invention, the flash memory life prediction model is tested by calculating the root mean square error:
wherein, RMSE is a root mean square error representative symbol; n is the same asThe total number of the samples; xobs,iThe service life of the ith flash memory chip is measured; xmodel,iAnd predicting the life prediction model of the ith flash memory chip.
And step S05, measuring physical information such as programming time, erasing time and the like of the flash memory to be predicted by using the flash memory test platform in the step S02, taking the measured physical information as an input variable of the life prediction model, and calculating an output value of the life prediction model to predict the residual life value of the target flash memory product.
The specific embodiments described herein are merely illustrative of the spirit of the invention. Various modifications or additions may be made to the described embodiments or alternatives may be employed by those skilled in the art without departing from the spirit or ambit of the invention as defined in the appended claims.
Claims (4)
1. A flash memory chip life prediction method based on mathematical model is characterized in that the life prediction value of a flash memory chip is predicted according to one physical quantity or the combination of several physical quantities of the flash memory chip; the flash memory chip physical quantity comprises: programming time, reading time, erasing time, programming current, reading current, erasing current, threshold voltage distribution and error rate of the flash memory chip; the method comprises the following specific steps:
step 1, extracting a sample from a flash memory product set as a sample flash memory, wherein the flash memory product set is a flash memory to be tested except the sample flash memory, and connecting a sample flash memory chip with a flash memory test system to start testing and collecting physical information and service life information of the flash memory chip required by establishing a flash memory chip service life prediction model; simultaneously connecting the flash memory chip to be tested with a flash memory test system to start testing and collecting physical information and service life information of the flash memory chip required by the prediction model;
in step 1, the specific steps of testing and collecting the physical information and the life information of the flash memory chip include:
step 5.1, randomly extracting sample chips from the flash memory chip set, and connecting the sample flash memory chips with a test system;
step 5.2, randomly selecting a storage block from each sample flash memory chip, sending a test data set to the flash memory storage block through a test system, and executing data writing operation on the flash memory storage block;
step 5.3, after the test data vector is sent, keeping the data stored in the flash memory storage block for a period of time, wherein the storage time is determined according to the type of the flash memory chip; the test system executes data reading operation on the flash memory chip, compares the read data with the sent test data, records and stores error data information, and does not store the error data information if the error data information does not exist; after the error information is stored, the data erasing operation is executed on the flash memory chip through the test system;
step 5.4, repeatedly executing the operations of the step 5.2 and the step 5.3, and recording the times of the operations of the step 5.2 and the step 5.3; when the operation times reach a set value, the test system records the duration of data writing operation of each storage block of the sample flash memory in the last step 5.2 and stores the recorded duration information; meanwhile, the test system records the duration of data erasing operation of each storage block of the sample flash memory in the last step 5.3 operation and stores the recorded duration information;
step 5.5, measuring the threshold voltage distribution of the flash memory chip unit through the test system, and recording and storing the threshold voltage distribution information of the unit; the step is an optional step, and if the predicted object does not have the READ-RETRY function, the step is not included in the testing step;
step 5.6, the test system counts and stores the data error rate information of each storage block of the flash memory chip;
step 5.7, repeating the step 5.4 to the step 5.6 until the flash memory chip reaches the service life limit; counting the programming/erasing operation cycles of the flash memory chip by the test system;
step 2, using one kind of physical information or combination of several kinds of physical information obtained by testing as an input variable of a mathematical mapping relation in the algorithm, using a predicted value of the service life of the flash memory chip as an output variable of the mathematical mapping relation, and processing data through an intelligent algorithm to establish a mathematical model;
and 3, testing the flash memory life prediction model, taking the physical quantity of the flash memory chip required by the prediction model as the input of the life prediction model, and calculating the output value of the life prediction model to predict the residual life value of the target flash memory product.
2. The method of claim 1, wherein in step 1, the sample flash memory is the same type of flash memory chip in the same manufacturing process; randomly drawing the same number of chip samples from different batches of chips to ensure the diversity of the samples; the sampling batch is selected randomly, the number of samples can be one percent of the total amount of the flash memory chips of the sampled batch, and the flash memory test system comprises an upper computer test control system and a flash memory control module; the upper computer testing system is realized by writing a program system through a computer language; the flash memory control module is realized through an FPGA.
3. The method of claim 1, wherein in step 1, the flash memory chip physical information comprises: programming time, reading time, erasing time, programming current, reading current, erasing current, threshold voltage distribution and error rate data information of the flash memory chip in a period from the beginning to the abnormal use of the flash memory chip; in the step 2, the input variable of the mathematical mapping relation for predicting the service life of the flash memory is one or a combination of more of the physical information; in step 1, the lifetime information of the flash memory chip is the number of program/erase operation cycles experienced by the flash memory chip from the beginning of use to the period of abnormal use.
4. The method of claim 3, wherein the flash memory chip life prediction method based on the mathematical model is characterized in that
The method for acquiring the programming time of the storage block of the flash memory chip comprises the following steps: setting a programming time recording module in a flash memory test system; the programming time recording module records the passed clock period when the flash memory starts to write data operation and stops recording the clock period number after receiving a data programming completion mark returned by the flash memory chip; the programming time value is the duration of the clock cycle times the number of programming clock cycles;
the method for acquiring the erasing time and the programming time of the memory block of the flash memory chip comprises the following steps: recording the number of clock cycles of the continuous erasing operation by an erasing time recording module in the test system, wherein the erasing time value is the product of the duration of the clock cycles and the number of the erasing clock cycles; the method for acquiring the threshold voltage distribution of the storage unit of the flash memory chip comprises the following steps: the test system sends READRETRY command set to the flash memory chip to gradually change the read reference voltage of the flash memory and simultaneously read data and count the threshold voltage distribution according to the read data value;
the flash memory chip memory block error rate acquisition mode is as follows: the test system executes read data operation on the flash memory chip to read data from the flash memory, compares the read data with the written test data to count the number of error data, and the error rate is the number of errors divided by the total number of data.
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| CN108777157B (en) * | 2018-05-08 | 2021-07-09 | 南京邮电大学 | Self-adaptive method for predicting MLC flash memory voltage threshold based on deep neural network |
| TWI657456B (en) | 2018-05-14 | 2019-04-21 | 慧榮科技股份有限公司 | Method for performing memory access management with aid of machine learning in memory device, associated memory device and controller thereof, and associated electronic device |
| CN108847267B (en) * | 2018-05-23 | 2022-04-08 | 置富科技（深圳）股份有限公司 | Flash memory life test method based on error mode |
| CN108831517B (en) * | 2018-05-23 | 2021-04-27 | 武汉忆数存储技术有限公司 | Method and test device for judging reliability of flash memory chip based on operation time or current |
| CN108682442B (en) * | 2018-05-23 | 2022-04-05 | 置富科技（深圳）股份有限公司 | Online testing and classifying method and testing system for different packaged flash memory chips |
| CN109634527B (en) * | 2018-12-12 | 2020-06-09 | 华中科技大学 | Flash memory service life prediction method realized in SSD |
| CN109815534B (en) * | 2018-12-17 | 2020-09-04 | 武汉忆数存储技术有限公司 | Flash memory life prediction method and system based on decision tree algorithm |
| CN109817267B (en) * | 2018-12-17 | 2021-02-26 | 武汉忆数存储技术有限公司 | Deep learning-based flash memory life prediction method and system and computer-readable access medium |
| CN109637576B (en) * | 2018-12-17 | 2021-06-11 | 华中科技大学 | Flash memory life prediction method based on support vector regression |
| CN109830254A (en) * | 2018-12-17 | 2019-05-31 | 武汉忆数存储技术有限公司 | A kind of service life of flash memory prediction technique, system, storage medium |
| CN109830255B (en) * | 2018-12-17 | 2020-11-17 | 武汉忆数存储技术有限公司 | Characteristic quantity-based flash memory life prediction method and system and storage medium |
| CN109857607A (en) * | 2018-12-24 | 2019-06-07 | 北京大学 | A kind of reliability checking method and device of NAND Flash solid state hard disk |
| CN110007857B (en) * | 2019-03-08 | 2022-08-19 | 北京星网锐捷网络技术有限公司 | Method and device for predicting service life of flash memory chip |
| CN110147290B (en) * | 2019-04-15 | 2023-06-27 | 深圳市纽创信安科技开发有限公司 | Chip age judging method and device, chip and terminal |
| CN110211626B (en) * | 2019-05-13 | 2020-11-17 | 华中科技大学 | Method and system for measuring health degree of flash memory |
| CN110232948B (en) * | 2019-05-28 | 2020-10-30 | 华中科技大学 | Method and system for measuring health degree of UFS chip in UFS storage device |
| CN110851079B (en) * | 2019-10-28 | 2021-10-15 | 置富科技（深圳）股份有限公司 | Adaptive storage device loss balancing method and system |
| CN111312326B (en) * | 2020-03-09 | 2021-11-12 | 宁波三星医疗电气股份有限公司 | Flash memory life testing method and device, power acquisition terminal and storage medium |
| CN112908399B (en) * | 2021-02-05 | 2022-01-18 | 置富科技（深圳）股份有限公司 | Flash memory abnormality detection method and device, computer equipment and storage medium |
| CN112908391B (en) * | 2021-02-08 | 2022-04-12 | 置富科技（深圳）股份有限公司 | Flash memory classification method and device based on mathematical model |
| CN113792878B (en) * | 2021-08-18 | 2024-03-15 | 南华大学 | Automatic recognition method for numerical program metamorphic relation |
| CN116880747A (en) * | 2023-06-13 | 2023-10-13 | 珠海妙存科技有限公司 | Flash memory wear degree judging method and system and electronic equipment |
| CN116822383A (en) * | 2023-08-31 | 2023-09-29 | 成都态坦测试科技有限公司 | Equipment life prediction model construction method and device, readable storage medium and equipment |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101159169A (en) * | 2006-10-05 | 2008-04-09 | 国际商业机器公司 | End of life prediction of flash memory |
| CN101266840A (en) * | 2008-04-17 | 2008-09-17 | 北京航空航天大学 | A life prediction method for flash memory electronic products |
| CN104376875A (en) * | 2014-11-19 | 2015-02-25 | 华为数字技术（苏州）有限公司 | Methods and devices for predicting and determining life of storage device |
| CN105159840A (en) * | 2015-10-16 | 2015-12-16 | 华中科技大学 | Method for extracting soft information of flash memory device |
| CN105679369A (en) * | 2015-12-28 | 2016-06-15 | 上海华虹宏力半导体制造有限公司 | Flash memory service predicting method and flash memory screening method |
| CN106504794A (en) * | 2015-09-04 | 2017-03-15 | Hgst荷兰公司 | Operating parameter for flash memory device |
| WO2017136220A1 (en) * | 2016-02-01 | 2017-08-10 | Qualcomm Incorporated | Flash device lifetime monitor systems and methods |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10222982B2 (en) * | 2016-02-10 | 2019-03-05 | Ricoh Company, Ltd. | Lifetime management device and lifetime management method |
-
2017
- 2017-10-18 CN CN201710973383.4A patent/CN107967928B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101159169A (en) * | 2006-10-05 | 2008-04-09 | 国际商业机器公司 | End of life prediction of flash memory |
| CN101266840A (en) * | 2008-04-17 | 2008-09-17 | 北京航空航天大学 | A life prediction method for flash memory electronic products |
| CN104376875A (en) * | 2014-11-19 | 2015-02-25 | 华为数字技术（苏州）有限公司 | Methods and devices for predicting and determining life of storage device |
| CN106504794A (en) * | 2015-09-04 | 2017-03-15 | Hgst荷兰公司 | Operating parameter for flash memory device |
| CN105159840A (en) * | 2015-10-16 | 2015-12-16 | 华中科技大学 | Method for extracting soft information of flash memory device |
| CN105679369A (en) * | 2015-12-28 | 2016-06-15 | 上海华虹宏力半导体制造有限公司 | Flash memory service predicting method and flash memory screening method |
| WO2017136220A1 (en) * | 2016-02-01 | 2017-08-10 | Qualcomm Incorporated | Flash device lifetime monitor systems and methods |
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