CN107959597B - Power-on self-detection method for airborne 1394b bus node - Google Patents
Power-on self-detection method for airborne 1394b bus node Download PDFInfo
- Publication number
- CN107959597B CN107959597B CN201711240034.8A CN201711240034A CN107959597B CN 107959597 B CN107959597 B CN 107959597B CN 201711240034 A CN201711240034 A CN 201711240034A CN 107959597 B CN107959597 B CN 107959597B
- Authority
- CN
- China
- Prior art keywords
- checking
- layer
- bus
- confirming
- node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40052—High-speed IEEE 1394 serial bus
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
- H04L43/0817—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking functioning
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
Abstract
The invention discloses a power-on self-detection method for an airborne 1394b bus node, and belongs to the technical field of airborne bus detection. The method comprises the following steps: checking an FPGA time scale counter of a node transaction layer, confirming whether a crystal oscillator of the transaction layer is normal and confirming that the FPGA is in a power-on working state; checking the bus configuration table and confirming whether the bus configuration table is correct; checking a data buffer area of the transaction layer, and confirming whether the double-port RAM of the transaction layer is normal; checking the link layer RAM, and confirming whether the link layer RAM and the link layer protocol chip work normally; checking a Cycle Timer of the link layer, and confirming that the crystal oscillator of the link layer works normally; step six, checking the negotiation rate of the physical layer, and confirming that the protocol chip of the physical layer and the crystal oscillator work normally; and step seven, checking the physical layer root node position and confirming that the bus node is correct. The invention has complete detection coverage, combines the crystal oscillator and the chip detection items and improves the detection efficiency.
Description
Technical Field
The invention belongs to the technical field of airborne bus detection, and particularly relates to an airborne 1394b bus node power-on detection method.
Background
The aircraft management system of the novel high-performance aircraft mostly adopts a high-speed airborne 1394b bus as a transmission path of core control signals and data. The on-board 1394b bus is an on-board bus protocol that has been defined and extended in a series from the IEEE 1394b bus protocol. The onboard 1394b bus is composed of a cc (control computer) node, an rn (remote node) node, a cable, and the like. In order to ensure normal operation of the bus system after power-on and improve the fault handling capability of the bus node, detection needs to be performed after the bus node is powered on to confirm the operating state of the node.
The existing power-on self-detection method detects devices such as chips, crystal oscillators, RAMs and the like of a physical layer, a link layer and a transaction layer of a bus node in sequence. In practice, the bus node is detected by the processor of the host computer where the bus node is located. The instruction sent to the physical layer by the upper computer is firstly sent to the FPGA chip of the transaction layer, then transferred to the link layer protocol chip, and finally executed by the physical layer chip. If the integrity of the physical layer circuit is detected, the instruction needs to be transmitted through the link layer and the transaction layer, but the integrity of the link layer and the transaction layer is not verified, and even if the fault of the physical layer is detected, the fault point cannot be effectively positioned.
Disclosure of Invention
The purpose of the invention is as follows: in order to solve the problems, the invention provides a power-on detection method for the airborne 1394b bus nodes, which optimizes the power-on self-detection sequence and test items of the airborne 1394b bus nodes in an airplane management system, thereby reducing the time overhead and improving the self-detection coverage rate and the fault positioning efficiency.
The technical scheme of the invention is that the power-on self-detection method of the airborne 1394b bus node comprises the following steps that according to the protocol hierarchical structure of the bus node, self-detection is carried out downwards from a transaction layer by an upper computer until reaching a physical layer; the method comprises the following steps:
checking an FPGA time scale counter of a node transaction layer, confirming whether a crystal oscillator of the transaction layer is normal and confirming that the FPGA is in a power-on working state;
checking whether the register value is updated or not by continuously reading the current FPGA time scale register value;
checking the bus configuration table and confirming whether the bus configuration table is correct;
reading a CRC result from a CRC result register of the configuration table, and checking whether a CRC value of the configuration table is consistent with a theoretical value;
checking a data buffer area of the transaction layer, and confirming whether the double-port RAM of the transaction layer is normal;
checking the link layer RAM, and confirming whether the link layer RAM and the link layer protocol chip work normally;
performing a link layer RAM TEST on the RAM _ TEST position 1 of the link layer protocol chip to confirm that the access of the link layer RAM is correct;
checking a Cycle Timer of the link layer, and confirming that the crystal oscillator of the link layer works normally;
reading the current Cycle Timer register twice continuously, and checking whether the Cycle Timer is updated;
step six, checking the negotiation rate of the physical layer, and confirming that the protocol chip of the physical layer and the crystal oscillator work normally;
and step seven, checking the physical layer root node position and confirming that the bus node is correct.
Preferably, in the third step, data is continuously written into the sending buffer, and then the written data is read;
and if the data written in and read from the data buffer area are consistent, judging that the transaction layer dual-port RAM is normal.
Preferably, in the seventh step, if the 1394b bus CC node is 1 and the RN node is 0, it is determined that the 1394b bus node has the correct role.
The technical scheme of the invention has the beneficial technical effects that: the invention discloses a power-on self-detection method of an airborne 1394b bus node, which has the following advantages:
1) the chip, the crystal oscillator, the chip, the crystal oscillator and the RAM of a physical layer covering the airborne 1394b bus node, the RAM and the crystal oscillator of a link layer, the RAM and the crystal oscillator of a transaction layer, a bus configuration table and a bus root node competition state are detected, and the detection coverage is complete;
2) the crystal oscillator and the chip detection items are combined, so that the detection efficiency is improved;
3) and a new detection sequence from top to bottom is adopted, and when a hardware problem is found, the detection is immediately stopped, so that the precision and the efficiency of fault positioning are improved.
Drawings
Fig. 1 is a flowchart illustrating a power-on self-test method for an airborne 1394b bus node according to a preferred embodiment of the present invention.
Detailed Description
In order to make the implementation objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be described in more detail below with reference to the accompanying drawings in the embodiments of the present invention. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The described embodiments are only some, but not all embodiments of the invention. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 1, in a power-on self-detection method for an airborne 1394b bus node, for a CC node of a certain airplane management calculation, after a computer is powered on, self-detection is performed from an upper computer to a physical layer from a transaction layer downwards according to a protocol hierarchy structure of the bus node; carrying out power-on self-detection on the CC nodes according to the following sequence:
checking an FPGA time scale counter of a node transaction layer, confirming whether a crystal oscillator of the transaction layer is normal or not and confirming that the FPGA is in a power-on working state;
and (3) reading the current FPGA time mark register value twice continuously, checking whether the time mark value changes, and recording the chassis channel number, the bus number and the initialization fault word (0x0100H) in the NVM if the time mark value does not change.
Checking the bus configuration table and confirming whether the bus configuration table is correct;
and reading a CRC check result from the CRC check result register of the configuration table, and checking whether the CRC check value of the configuration table is consistent with a theoretical value. If not, the chassis channel number, bus number, and initialization fault word (0x0101H) are recorded in the NVM.
Checking a data buffer area, and determining whether the transaction layer dual-port RAM is normal;
in this embodiment, a scheme of continuously writing 0x5555 data into a transmission buffer (offset address: 0x4000) and then reading the written data is adopted to confirm whether the written data and the read data are consistent, and finally, all the data in the transmission buffer is cleared.
If the written data and the read data are inconsistent, recording the chassis channel number, the bus number, the initialization fault word (0x0102H) and the address of the fault RAM in the NVM;
checking the link layer RAM, and confirming whether the link layer RAM and the link layer protocol chip work normally;
and (4) carrying out RAM TEST on the RAM _ TEST position 1 of the link layer protocol chip in the link layer protocol chip to confirm whether the access of the RAM of the link layer is correct or not.
If not, the chassis channel number, bus number, and initialization fault word (0x0103H) are recorded in the NVM.
Checking a Cycle Timer of a link layer and confirming that a crystal oscillator of the link layer works normally;
reading the current Cycle Timer register value twice continuously, and checking whether the Cycle Timer is changed.
If not, the chassis channel number, bus number, and initialization fault word (0x0104H) are recorded in the NVM.
Step six, checking the physical layer negotiation rate;
in this embodiment, the value should be S400; if not, the chassis channel number, bus number, and initialization fault word (0x0105H) are recorded in the NVM.
Step seven, checking the physical layer root node position and confirming that the bus node is correct;
in this embodiment, the bit value should be 1 for the CC node. If not, the chassis channel number, bus number, and initialization fault word (0x0106H) are recorded in the NVM.
The invention relates to a power-on self-detection method of an airborne 1394b bus node, which adopts a new detection sequence from top to bottom, and immediately terminates detection when a hardware problem is found, thereby improving the precision and efficiency of fault positioning; the detection method covers the chip and the crystal oscillator of a physical layer of an airborne 1394b bus node, the chip, the crystal oscillator and the RAM of a link layer, the RAM and the crystal oscillator of a transaction layer, a bus configuration table and a bus root node competition state, and is complete in detection coverage; and the crystal oscillator and the chip detection items are combined, so that the detection efficiency is improved.
Finally, it should be pointed out that: the above examples are only for illustrating the technical solutions of the present invention, and are not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (3)
1. A power-on self-detection method for an airborne 1394b bus node is characterized by comprising the following steps: according to the protocol hierarchical structure of the bus node, the upper computer performs self-detection from the transaction layer downwards until reaching the physical layer; the method comprises the following steps:
checking an FPGA time scale counter of a node transaction layer, confirming whether a crystal oscillator of the transaction layer is normal and confirming that the FPGA is in a power-on working state;
checking whether the register value is updated or not by continuously reading the current FPGA time scale register value;
checking the bus configuration table and confirming whether the bus configuration table is correct;
reading a CRC result from a CRC result register of the configuration table, and checking whether a CRC value of the configuration table is consistent with a theoretical value;
checking a data buffer area of the transaction layer, and confirming whether the double-port RAM of the transaction layer is normal;
checking the link layer RAM, and confirming whether the link layer RAM and the link layer protocol chip work normally;
performing a link layer RAM TEST on the RAM _ TEST position 1 of the link layer protocol chip to confirm that the access of the link layer RAM is correct;
checking a Cycle Timer of the link layer, and confirming that the crystal oscillator of the link layer works normally;
reading the current Cycle Timer register twice continuously, and checking whether the Cycle Timer is updated;
step six, checking the negotiation rate of the physical layer, and confirming that the protocol chip of the physical layer and the crystal oscillator work normally;
and step seven, checking the physical layer root node position and confirming that the bus node is correct.
2. The method of power-on self-test of an airborne 1394b bus node of claim 1, wherein: in the third step, continuously writing data into the sending buffer area, and then reading the written data;
and if the data written in and read from the data buffer area are consistent, judging that the transaction layer dual-port RAM is normal.
3. The method of power-on self-test of an airborne 1394b bus node of claim 1, wherein: and in the seventh step, if the 1394b bus CC node is 1 and the RN node is 0, the role of the 1394b bus node is judged to be correct.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711240034.8A CN107959597B (en) | 2017-11-30 | 2017-11-30 | Power-on self-detection method for airborne 1394b bus node |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711240034.8A CN107959597B (en) | 2017-11-30 | 2017-11-30 | Power-on self-detection method for airborne 1394b bus node |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107959597A CN107959597A (en) | 2018-04-24 |
| CN107959597B true CN107959597B (en) | 2021-01-08 |
Family
ID=61962226
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711240034.8A Active CN107959597B (en) | 2017-11-30 | 2017-11-30 | Power-on self-detection method for airborne 1394b bus node |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107959597B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113422713B (en) * | 2021-05-28 | 2022-08-19 | 中国航空工业集团公司沈阳飞机设计研究所 | 1394b bus network testing method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6639918B1 (en) * | 2000-01-18 | 2003-10-28 | Apple Computer, Inc. | Method and apparatus for border node behavior on a full-duplex bus |
| US7269670B2 (en) * | 2003-06-05 | 2007-09-11 | Texas Instruments Incorporated | Analog ethernet detector having first logic circuit and second logic circuit coupled to output signal detectors to determine ethernet and non-ethernet signals |
| CN101764794A (en) * | 2008-12-23 | 2010-06-30 | 中国科学院空间科学与应用研究中心 | Programmable IEEE1394 bus monitoring system and monitoring method thereof |
| CN106342296B (en) * | 2011-12-13 | 2014-08-20 | 中国航空工业第六一八研究所 | A kind of 1394B Bus simulator device based on AS5643 agreement |
| CN104572563A (en) * | 2014-12-11 | 2015-04-29 | 深圳市国微电子有限公司 | Physical layer circuit based on IEEE 1394 interface |
| CN106371961A (en) * | 2016-11-24 | 2017-02-01 | 陕西千山航空电子有限责任公司 | Device and method for testing bus recorder |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4768565B2 (en) * | 2006-09-28 | 2011-09-07 | 富士通セミコンダクター株式会社 | Interface device and topology construction method |
-
2017
- 2017-11-30 CN CN201711240034.8A patent/CN107959597B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6639918B1 (en) * | 2000-01-18 | 2003-10-28 | Apple Computer, Inc. | Method and apparatus for border node behavior on a full-duplex bus |
| US7269670B2 (en) * | 2003-06-05 | 2007-09-11 | Texas Instruments Incorporated | Analog ethernet detector having first logic circuit and second logic circuit coupled to output signal detectors to determine ethernet and non-ethernet signals |
| CN101764794A (en) * | 2008-12-23 | 2010-06-30 | 中国科学院空间科学与应用研究中心 | Programmable IEEE1394 bus monitoring system and monitoring method thereof |
| CN106342296B (en) * | 2011-12-13 | 2014-08-20 | 中国航空工业第六一八研究所 | A kind of 1394B Bus simulator device based on AS5643 agreement |
| CN104572563A (en) * | 2014-12-11 | 2015-04-29 | 深圳市国微电子有限公司 | Physical layer circuit based on IEEE 1394 interface |
| CN106371961A (en) * | 2016-11-24 | 2017-02-01 | 陕西千山航空电子有限责任公司 | Device and method for testing bus recorder |
Non-Patent Citations (2)
| Title |
|---|
| "1394b IEEE standard for a high-performance serial bus-amendment 2";IEEE;《IEEE》;20091114;第217-246页 * |
| "机载1394B总线的应用需求和实现";李新民等;《第六届中国航天学会青年科技论坛文集（下册）》;20141130;第1186-1191页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107959597A (en) | 2018-04-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106463179B (en) | Utilize the methods, devices and systems of Memory Controller processing error in data event | |
| CN105702300B (en) | A kind of NAND Flash tolerant systems based on FPGA | |
| CN103092798B (en) | The method of the access means under SOC(system on a chip) and bus | |
| CN102567146B (en) | Log backup method and device and smart card | |
| CN104932954A (en) | FPGA (Field Programmable Gate Array) key data protection method for microsatellite | |
| CN104781794A (en) | In-place change between transient and persistent state for data structures in non-volatile memory | |
| CN103699337A (en) | Writing control method and system based on independent redundant array of independent disks (RAID) | |
| CN104579313A (en) | On-orbit SRAM type FPGA fault detection and restoration method based on configuration frame | |
| CN108089822A (en) | Management method, system, equipment and the storage medium of storage chip | |
| CN104111870A (en) | Interrupt processing device and method | |
| CN109451098A (en) | FPGA accelerator card MAC Address configuration method, device and accelerator card | |
| CN107959597B (en) | Power-on self-detection method for airborne 1394b bus node | |
| CN110941582B (en) | USB bus structure of BMC chip and communication method thereof | |
| CN105573947B (en) | A kind of SD/MMC card control methods based on APB buses | |
| US8910004B2 (en) | Information processing apparatus, and method of controlling information processing apparatus | |
| CN102760109B (en) | The communication means of data, Apparatus and system | |
| EP3125251A1 (en) | Hamming code-based data access method and integrated random access memory | |
| CN104780123A (en) | Network packet receiving and sending processing device and design method thereof | |
| US11036595B2 (en) | Semiconductor system including fault manager | |
| CN104460938A (en) | System-wide power conservation method and system using memory cache | |
| CN104484260A (en) | Simulation monitoring circuit based on GJB289 bus interface SoC (system on a chip) | |
| CN103744752B (en) | A kind of online fault detection method of internal memory and device | |
| US9092486B2 (en) | Extensible I/O activity logs | |
| CN105718349A (en) | Cross-die interface snoop or global observation message ordering | |
| CN109710187A (en) | Read command accelerated method, device, computer equipment and the storage medium of NVMe SSD main control chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |