CN107959432A - A kind of clamp circuit and with lifting step-up ratio and suppress the Y source inventers of DC bus-bar voltage spike - Google Patents
A kind of clamp circuit and with lifting step-up ratio and suppress the Y source inventers of DC bus-bar voltage spike Download PDFInfo
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- CN107959432A CN107959432A CN201711367579.5A CN201711367579A CN107959432A CN 107959432 A CN107959432 A CN 107959432A CN 201711367579 A CN201711367579 A CN 201711367579A CN 107959432 A CN107959432 A CN 107959432A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
- H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
Abstract
A kind of clamp circuit and step-up ratio and suppress the Y source inventers of DC bus-bar voltage spike with lifting, be related to inverter technology field.The problem of present invention is limited to solve existing Z-source inverter power grade, and circuit utilization ratio is low.Diode D2Cathode connect capacitance C at the same time3One end and inductance L0One end, capacitance C4Both ends connect diode D respectively2Anode and inductance L0The other end, diode D2Anode and capacitance C3Voltage input end of the other end as clamp circuit, inductance L0The other end and capacitance C3Voltage output end of the other end as clamp circuit.The voltage input end of the voltage output end connection clamp circuit of Y source network circuits, the voltage input end of the voltage output end connection inversion bridge circuit of clamp circuit, inversion bridge circuit are used for for load or power grid power supply.
Description
Technical Field
The invention belongs to the technical field of inverters.
Background
Inverters are currently an indispensable important device in power applications, however, conventional inverters have many inherent drawbacks. For example, the upper and lower switching tubes of the same bridge arm of the inverter of the conventional voltage source cannot be turned on simultaneously, so that dead time needs to be injected, which causes a certain distortion of the output waveform. In contrast, conventional current source inverters do not allow to enter a freewheel mode, and therefore require the addition of an overlap time. On the other hand, the conventional voltage source inverter and current source inverter respectively require that the output voltage must be lower or higher than the dc bus voltage, so that a multi-stage circuit may be required for transformation in practical applications, which not only increases the control complexity, but also increases the cost and volume. In 2002, peng Fangzheng teaches a source-to-source inverter, the Z source inverter. The Z-source inverter can realize the functions of boosting and reducing voltage through single-stage inversion, so that the efficiency of the Z-source inverter is higher than that of a traditional inverter. In addition, the Z-source inverter realizes the boosting function through direct connection, so dead time is not needed, the EMI interference resistance is stronger than that of the traditional inverter, and the output waveform quality is better.
In the last decade, many scholars have been working on improving the operating characteristics of Z-source inverters. The impedance source inverter with high boosting capacity can be realized by introducing a coupling inductor into a circuit. The impedance source inverter can obtain any required voltage boosting ratio by changing the turn ratio of the coupling inductor, and therefore, the impedance source inverter can be suitable for various application occasions.
However, the leakage inductance in the coupling inductance causes many problems to the operation of the circuit, for example, a large voltage peak is generated on the dc bus, so that the voltage stress of the switching tube becomes large, and the power level that can be applied to the circuit is limited. Meanwhile, the energy of the leakage inductance is not recycled, which reduces the efficiency of the circuit.
Disclosure of Invention
The invention aims to solve the problems that the power level of a circuit is limited and the utilization efficiency of the circuit is low due to leakage inductance in a coupling inductor of the conventional Z-source inverter, and provides a clamping circuit and a Y-source inverter which can improve the boost ratio and inhibit the voltage spike of a direct-current bus.
A clamping circuit comprising a capacitor C 3 Capacitor C 4 Diode D 2 And an inductance L 0 ；
Diode D 2 The cathode of the capacitor is simultaneously connected with the capacitor C 3 One terminal of (1) and an inductance L 0 One terminal of (C), a capacitor 4 Are respectively connected with a diode D 2 Anode and inductor L of 0 The other end of the first tube is connected with the second tube,
diode D 2 Anode and capacitor C 3 The other end of which serves as a voltage input port of the clamping circuit,
inductor L 0 Another terminal of (1) and a capacitor C 3 And the other end of the second switch is used as a voltage output port of the clamping circuit.
The first Y-source inverter with the clamping circuit comprises a Y-source network circuit, a clamping circuit and an inverter bridge circuit,
the voltage output port of the Y source network circuit is connected with the voltage input port of the clamping circuit,
the voltage output port of the clamping circuit is connected with the voltage input port of the inverter bridge circuit,
the inverter bridge circuit is used for supplying power to a load or a power grid.
The second Y-source inverter with the clamping circuit comprises a Y-source network circuit, a clamping structure and an inverter bridge circuit,
the clamping structure is a plurality of cascaded clamping circuits, a voltage input port of the head end clamping circuit is used as a voltage input port of the clamping structure, a voltage output port of the tail end clamping circuit is used as a voltage output port of the clamping structure,
the voltage output port of the Y source network circuit is connected with the voltage input port of the clamping structure, the voltage output port of the clamping structure is connected with the voltage input port of the inverter bridge circuit, and the inverter bridge circuit is used for supplying power to a load or a power grid.
The clamping circuit can be applied to an impedance source inverter with coupling inductors so as to inhibit voltage spikes generated on a direct current bus and improve the voltage boosting ratio of the original circuit. Since the present invention also enables some decoupling of power, a smaller capacitance can be used in the circuit, which helps to increase the life of the circuit and reduce the ESRs of the capacitance to improve efficiency.
When the Y-source inverter disclosed by the invention reaches the same boost ratio, a smaller through duty ratio is required, a higher modulation ratio is allowed, and the utilization rate of a direct current bus is higher. In addition, the clamping circuit also has a certain power decoupling effect, and the influence of double power frequency power fluctuation on a power supply can be reduced.
Drawings
FIG. 1 is a circuit diagram of a clamp circuit according to a first embodiment when the clamp circuit is applied to different circuits;
figure 2 is a detailed structure of the coupling inductor of figure 1,
wherein (a) represents a Y-type coupling inductance, (b) represents a T-type coupling inductance, (c) represents a delta-type coupling inductance, (d) represents an LCCT-type coupling inductance, and (e) represents a f-type coupling inductance;
fig. 3 is a circuit configuration diagram of a Y-source inverter according to a second embodiment;
fig. 4 is a waveform diagram of parameters of a Y-source inverter according to a second embodiment;
figure 5 is a schematic diagram of four operating modes of the Y-source inverter,
wherein (a) represents a through mode corresponding to t in FIG. 4 0 To t 1 Period, (b) indicates that the through mode corresponds to t in fig. 4 1 To t 2 Period, (c) indicates that the non-pass-through mode corresponds to t in fig. 4 2 To t 3 Period, (d) represents non-pass-through mode, corresponding to t in FIG. 4 3 To t 0 A time period;
fig. 6 is a circuit configuration diagram of a Y-source inverter having a cascade structure;
FIG. 7 is an equivalent operating circuit of an inverter without a clamp circuit, wherein (a) indicates a pass-through mode and (b) indicates a non-pass-through mode;
FIG. 8 is a waveform diagram of experimental data for input voltage, current and output voltage, current;
fig. 9 is a waveform diagram of experimental data for diode current, voltage, and bus voltage.
Detailed Description
The first embodiment is as follows: this embodiment will be described in detail with reference to fig. 1 and 2, and the clamp circuit according to this embodiment includes a capacitor C 3 Capacitor C 4 Diode D 2 And an inductance L 0 ；
Diode D 2 The cathode of the capacitor is simultaneously connected with the capacitor C 3 One terminal of (1) and an inductance L 0 One terminal of (C), a capacitor 4 Are respectively connected with a diode D 2 Anode and inductor L 0 The other end of the first tube is connected with the second tube,
diode D 2 Anode and capacitor C 3 The other end of the diode D is used as a voltage input port of the clamping circuit 2 The anode of (1) is a positive input end, and a capacitor C 3 The other end of the first switch is a reverse input end,
inductor L 0 Another terminal of (1) and a capacitor C 3 The other end of the inductor L is used as a voltage output port of the clamping circuit 0 The other end of the capacitor C is a forward output end 3 And the other end of the input terminal is a reverse output terminal.
L in FIG. 1 coupled Indicating inverterThe specific structure of the medium coupling inductor is shown in fig. 2.
After applying the clamp circuit described in this embodiment, it can be seen that the capacitor C is used 3 Capacitor C 4 And a diode D 2 The voltage on the dc bus is clamped so that no voltage spikes are generated on the dc bus.
Fig. 1 shows a specific structure of the clamp circuit according to the present embodiment in different practical applications;
wherein, (a) is applied to occasions with low requirements on power supply, such as common remote controllers and toy vehicles;
(b) The (c), (i) and (j) are applied to occasions with higher requirements on power sources, such as photovoltaic panel power generation and fuel cells;
(d) The magnetic core works in an alternating current magnetization mode in the circuit, and a smaller magnetic core can be selected;
(e) And (f) the application is applied to the occasion with higher requirement on the withstand voltage of the capacitor;
(g) And (h) the current of the capacitor can be reduced, and the capacitor can be applied to occasions with larger ESR (equivalent series resistance) of the capacitor, so that the loss is reduced;
(k) And (l) shows that when the coupled inductor is applied to the situation with larger leakage inductance, the energy absorbed by the leakage inductance can be reduced.
The second embodiment is as follows: the present embodiment is described in detail with reference to fig. 3 to 5, and the present embodiment is a Y-source inverter including the clamp circuit described in the first embodiment, and includes a Y-source network circuit, a clamp circuit, and an inverter bridge circuit, where a voltage output port of the Y-source network circuit is connected to a voltage input port of the clamp circuit, a voltage output port of the clamp circuit is connected to a voltage input port of the inverter bridge circuit, and the inverter bridge circuit is used to supply power to a load or a power grid.
In this embodiment, the capacitor C 3 Capacitor C 4 And a diode D 2 For clamping the voltage on the dc bus so that no voltage spikes can occur on the dc bus.
The third concrete implementation mode: in this embodiment, the inverter bridge circuit is equivalent to a switch, and the Y-source inverter includes a through mode and a non-through mode, where the equivalent switch is closed in the through mode and the equivalent switch is open in the non-through mode.
The Y-source inverter works in a direct-through mode and a non-direct-through mode, wherein the linear region is included in the direct-through mode and the non-direct-through mode. In the linear region, the current on the leakage inductance changes slowly and linearly, so that no large voltage spikes occur across the leakage inductance. The equivalent circuit in both modes is shown in fig. 5. The alternating current output is equivalent to a current source, and the inverter bridge is equivalent to a switching tube SW. In the through mode, the equivalent switch SW is closed; while in the non-through state the equivalent switch SW is open.
The reference numbers in fig. 4 and 5 are defined as follows:
G SW in order to switch the drive signal on and off,is flowed through a capacitor C 4 The current of (2) is measured by the sensor,is flowed through a capacitor C 2 The current of (a) is measured,is flowed through a capacitor C 3 Current of (i) 3 For flowing through the coil N 3 Current of (i) 2 Is flowing through the coil N 2 Current of (i) 1 Is flowing through the coil N 1 The current of (a) is measured,to flow through a diode D 2 The current of (a) is measured,is a diodeD 1 The voltage of the two ends is applied,is a diode D 2 The voltage of the two ends is applied,is a capacitor C 1 The voltage of the two ends is applied,is a capacitor C 2 The voltage of the two ends is applied,is a capacitor C 3 The voltage of the two ends is applied,is a capacitor C 4 The voltage of the two ends is applied,is a current flowing through the inductor L 0 Current of v S And V dc Is the voltage across the switch (DC bus voltage), I in For input of current, I o Is the load current.
t 0 To t 1 Has a short time interval to the exciting inductance L M Input inductance L in And an output inductor L 0 The energy of (c) has no effect and is therefore negligible. At t 3 To t 0 In time period, diode D 2 Off, appears in the diode D 2 The reverse voltage across and the voltage drop appearing on the bus are small and therefore negligible, so (c) and (d) in fig. 5 can be considered as one and the same equivalent circuit.
In-pair excitation inductance L M An input inductor L in And an output inductor L 0 After the volt-second balance principle is applied, a boosting formula of the Y-source inverter can be obtained:
wherein K is the coupling inductance coefficient,V dc is the DC bus voltage, V, of the Y-source inverter in Is the input voltage of the Y-source inverter, V o The output voltage of the Y-source inverter, d is a through duty ratio, B is a boost coefficient, and M is a modulation ratio.
As can be seen from equation (1), the range of the through duty cycle d and the modulation ratio M:
0≤d<d max ＝1/(1+k),0<M<M max ＝1-d (2)，
in the inverter without the additional clamp circuit, the boost formula is:
it can be seen that the Y-source inverter has a higher step-up ratio when the coupling inductance K is the same. Namely, when the same boost ratio is reached, the Y-source inverter needs a smaller through duty ratio d, so that a higher modulation ratio M is allowed, and the utilization rate of the direct-current bus is higher. In addition, the clamping circuit also has a certain power decoupling effect, and the influence of double power frequency power fluctuation on a power supply can be reduced.
The fourth concrete implementation mode: referring to fig. 6, the embodiment is specifically described, and the embodiment is a Y-source inverter including the clamp circuit described in the first embodiment, and includes a Y-source network circuit, a clamp structure, and an inverter bridge circuit,
the clamping structure is a plurality of cascaded clamping circuits, a voltage input port of the first end clamping circuit is used as a voltage input port of the clamping structure, a voltage output port of the tail end clamping circuit is used as a voltage output port of the clamping structure,
the voltage output port of the Y source network circuit is connected with the voltage input port of the clamping structure, the voltage output port of the clamping structure is connected with the voltage input port of the inverter bridge circuit, and the inverter bridge circuit is used for supplying power to a load or a power grid.
In this embodiment, the capacitor C 3 Capacitor C 4 And a diode D 2 For clamping the voltage on the dc bus so that no voltage spikes can occur on the dc bus.
By cascading clamping circuits together, a cascaded Y-source inverter as shown in fig. 6 can be obtained, and such a circuit can also clamp the bus voltage. In FIG. 6 (a), C 2n-1 、C 2n And D n Constituting a clamping structure, C in FIG. 6 (b) 2n-1 、C 2n 、C′ 2 And D n A clamping structure is formed. The advantage of the cascaded Y-source inverter is that when the turn ratio K is smaller, there is still a larger step-up ratio, and the step-up formula is:
wherein n is the stage number of the clamping circuit, n is not less than 2,K is the coupling inductance coefficient, V dc Is the DC bus voltage, V, of the Y-source inverter in Is the input voltage of a Y-source inverter, V o The output voltage of the Y-source inverter, d is a through duty ratio, B is a boost coefficient, and M is a modulation ratio.
Without the addition of the clamping circuit, the equivalent operating circuit diagram of the inverter is shown in fig. 7, in which the coupled inductor is equivalent to an ideal coupled inductor and a leakage inductor, and the leakage inductor is represented by a wavy line.
In FIG. 7 (a), the current flowing through the leakage inductance is
i 1 ＝0 (5)，
In FIG. 7 (b), the current flowing through the leakage inductance is
In fig. 7, when the switch is turned on to off, the current flowing through the dc bus is instantaneously changed, and the current flowing through the leakage inductance is instantaneously changed from the current value calculated in (5) to the current value calculated in (6). According to the relation between the inductance voltage and the current change rate:
it has been found that when the rate of change of the current is too fast, a large voltage is developed across the leakage inductance, which also drives up the voltage on the dc bus, thereby creating a voltage spike on the dc bus.
In the novel Y-source inverter to which the clamp circuit is added, when the circuit is shifted from the operating state shown in fig. 5 (b) to the operating state shown in fig. 5 (c). Even if the switch SW is turned off, the diode D 2 It will be turned on immediately to form a new current loop, so that the current flowing through the leakage inductance will not change immediately. Meanwhile, the energy on the leakage inductance is stored in the capacitor by the clamping circuit, and the efficiency of the circuit is improved.
In order to verify the practicability of the invention, a 200W experimental platform based on the DSP TMS320F2812 is designed. Coefficient of coupling inductance K =3 (N) 1 :N 2 :N 3 =40, boost coefficient B =2.85, and modulation ratio M =0.68. The input voltage is 80V, the inverter dc bus voltage is 228V, the output rated voltage is 110VAC, 50Hz, the load R =60 Ω, and the switching frequency is 10kHz.
Fig. 8 shows experimental waveforms of input current and voltage and output current and voltage of the Y-source inverter. The through duty cycle is 0.13 and the output voltage is 150V (155V theoretical). It can be seen that the topology proposed by the present invention has a smaller through duty cycle at the same boost ratio. The double power frequency ripple (caused by power ripple) in the input current is also smaller.
Fig. 9 shows a diode voltage current waveform and a bus voltage waveform. In a Y-source inverter, where the bus voltage is 223V and the voltage spike is only 10V, the clamp effectively eliminates the voltage spike on the bus.
Claims (6)
1. A clamping circuit comprising a capacitor C 3 Capacitor C 4 Diode D 2 And an inductance L 0 ；
Diode D 2 The cathode of the capacitor is simultaneously connected with the capacitor C 3 One terminal of (1) and an inductance L 0 One terminal of (C), a capacitor 4 Are respectively connected with a diode D 2 Anode and inductor L 0 The other end of the first tube is connected with the second tube,
diode D 2 Anode and capacitor C 3 The other end of which serves as a voltage input port of the clamping circuit,
inductor L 0 Another terminal of (1) and a capacitor C 3 And the other end of the second terminal serves as a voltage output port of the clamp circuit.
2. The Y-source inverter including the clamping circuit of claim 1, comprising a Y-source network circuit, a clamping circuit, and an inverter bridge circuit,
the voltage output port of the Y source network circuit is connected with the voltage input port of the clamping circuit,
the voltage output port of the clamping circuit is connected with the voltage input port of the inverter bridge circuit,
the inverter bridge circuit is used for supplying power to a load or a power grid.
3. The Y-source inverter of claim 2, wherein the Y-source inverter comprises a pass-through mode and a non-pass-through mode,
the equivalent switch is closed in the through mode,
the equivalent switch is turned off in the non-through mode.
4. The Y-source inverter of claim 2, wherein the boost formula for the Y-source inverter is:
wherein K is coupling inductance coefficient, V dc Is the DC bus voltage, V, of the Y-source inverter in Is the input voltage of a Y-source inverter, V o The output voltage of the Y-source inverter, d is a through duty ratio, B is a boost coefficient, and M is a modulation ratio.
5. The Y-source inverter including the clamping circuit of claim 1, comprising a Y-source network circuit, a clamping structure, and an inverter bridge circuit,
the clamping structure is a plurality of cascaded clamping circuits, a voltage input port of the head end clamping circuit is used as a voltage input port of the clamping structure, a voltage output port of the tail end clamping circuit is used as a voltage output port of the clamping structure,
the voltage output port of the Y source network circuit is connected with the voltage input port of the clamping structure, the voltage output port of the clamping structure is connected with the voltage input port of the inverter bridge circuit, and the inverter bridge circuit is used for supplying power to a load or a power grid.
6. The Y-source inverter of claim 5, wherein the boost formula for the Y-source inverter is:
wherein n is the stage number of the clamping circuit, n is not less than 2,K is the coupling inductance coefficient, V dc Is the DC bus voltage, V, of the Y-source inverter in Is the input voltage of the Y-source inverter, V o The output voltage of the Y-source inverter, d is a through duty ratio, B is a boost coefficient, and M is a modulation ratio.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109586605A (en) * | 2019-01-15 | 2019-04-05 | 哈尔滨工业大学 | A kind of Y source inventer inhibiting direct-current chain peak voltage |
| CN109756140A (en) * | 2019-01-17 | 2019-05-14 | 哈尔滨工业大学 | A kind of Y source inventer with raising step-up ratio |
| CN109818494A (en) * | 2019-01-25 | 2019-05-28 | 山东科技大学 | A kind of quasi- source Y DC-DC converter of high gain voltage type |
| CN110768552A (en) * | 2019-11-08 | 2020-02-07 | 东北电力大学 | Double-coil coupling inductance type impedance source inverter for inhibiting DC link voltage peak |
| CN111130374A (en) * | 2019-12-12 | 2020-05-08 | 东北电力大学 | T source inverter with low direct-current link voltage spike |
| CN111900893A (en) * | 2020-06-15 | 2020-11-06 | 哈尔滨工业大学 | High-boost-ratio T-source inverter for inhibiting DC link voltage spike and working method thereof |
| CN112398350A (en) * | 2020-11-09 | 2021-02-23 | 哈尔滨工业大学 | double-Y-source high-boost-ratio DC-DC converter |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204316331U (en) * | 2015-01-16 | 2015-05-06 | 四川瑞新轨道交通科技发展有限公司 | The accurate Z source step-up/step-down circuit of track traffic automatic grounding system |
| CN105958823A (en) * | 2016-06-28 | 2016-09-21 | 华南理工大学 | Current continuous high-gain switch voltage rise quasi-Z-source converter circuit |
| CN205847124U (en) * | 2016-06-30 | 2016-12-28 | 华南理工大学 | A kind of switched inductors type mixes quasi-Z-source inverter |
-
2017
- 2017-12-18 CN CN201711367579.5A patent/CN107959432B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204316331U (en) * | 2015-01-16 | 2015-05-06 | 四川瑞新轨道交通科技发展有限公司 | The accurate Z source step-up/step-down circuit of track traffic automatic grounding system |
| CN105958823A (en) * | 2016-06-28 | 2016-09-21 | 华南理工大学 | Current continuous high-gain switch voltage rise quasi-Z-source converter circuit |
| CN205847124U (en) * | 2016-06-30 | 2016-12-28 | 华南理工大学 | A kind of switched inductors type mixes quasi-Z-source inverter |
Non-Patent Citations (1)
| Title |
|---|
| LIU HONGPENG, LIU KUAN等: "Stability Analysis of Improved Y-Source Inverter", 《2017 IEEE TRANSPORTATION ELECTRIFICATION CONFERENCE AND EXPO, ASIA-PACIFIC》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109586605A (en) * | 2019-01-15 | 2019-04-05 | 哈尔滨工业大学 | A kind of Y source inventer inhibiting direct-current chain peak voltage |
| CN109756140A (en) * | 2019-01-17 | 2019-05-14 | 哈尔滨工业大学 | A kind of Y source inventer with raising step-up ratio |
| CN109818494A (en) * | 2019-01-25 | 2019-05-28 | 山东科技大学 | A kind of quasi- source Y DC-DC converter of high gain voltage type |
| CN109818494B (en) * | 2019-01-25 | 2020-11-17 | 山东科技大学 | High-gain voltage type quasi-Y source direct current-direct current converter |
| CN110768552A (en) * | 2019-11-08 | 2020-02-07 | 东北电力大学 | Double-coil coupling inductance type impedance source inverter for inhibiting DC link voltage peak |
| CN111130374A (en) * | 2019-12-12 | 2020-05-08 | 东北电力大学 | T source inverter with low direct-current link voltage spike |
| CN111900893A (en) * | 2020-06-15 | 2020-11-06 | 哈尔滨工业大学 | High-boost-ratio T-source inverter for inhibiting DC link voltage spike and working method thereof |
| CN112398350A (en) * | 2020-11-09 | 2021-02-23 | 哈尔滨工业大学 | double-Y-source high-boost-ratio DC-DC converter |
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| CN107959432B (en) | 2019-11-29 |
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