CN107946238A - A kind of preparation process of metal interconnection structure - Google Patents
A kind of preparation process of metal interconnection structure Download PDFInfo
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- CN107946238A CN107946238A CN201711208507.6A CN201711208507A CN107946238A CN 107946238 A CN107946238 A CN 107946238A CN 201711208507 A CN201711208507 A CN 201711208507A CN 107946238 A CN107946238 A CN 107946238A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
The present invention provides a kind of preparation process of metal interconnection structure, comprise the following steps：Sacrifice layer, passivation layer and lithography layer are sequentially depositing on the surface of interlayer dielectric layer；Photoetching is carried out to remove the lithography layer of position to be etched, forms photoetching raceway groove；Perform etching to form metal interconnecting layer raceway groove, and then remove lithography layer；One layer of metal seed layer is first deposited in metal interconnecting layer raceway groove；Deposited metal interconnection layer is with full of raceway groove；The metal interconnecting layer is planarized, and exposes sacrifice layer；Remove sacrifice layer and cover metal interconnecting layer and air-gap to form air-gap (Air Gap) deposition barrier layer.The technique of the present invention, can effectively prepare air-gap, reduce parasitic capacitance, so that the speed of service of the semiconductor devices such as 3D nand flash memories is improved, and use reliability.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of chip back-end metal making technology, particularly one kind
The preparation process of metal interconnection structure.
Background technology
Semiconductor devices, such as 3D NAND (3D with non-) flash memory, its manufacture must be after series of process flow, the stream
Journey includes a variety of semiconductor device technology steps such as etching and photoetching.It can include on traditional manufacturing process
300~400 steps, each of which step can all influence the final pattern of each device of semiconductor core on piece, that is, influence device
Characteristic size, so as to influence the various electrical characteristics of device.The main secondary work of two classes can be divided into traditional technological process
Skill flow, respectively front-end process (Front End of Line, abbreviation FEOL) and back-end process (Back End of Line,
Abbreviation BEOL).
Back-end process may include the formation of metal layer, and the metal interlevel metal connecting line of different layers, contact on wafer
The formation in hole etc..Wherein, metal interconnection structure is to realize the important feature of the electrical connection between semiconductor chip, mesh
Before have been developed various metal interconnection structures and formation process, such as copper interconnection structure, and form the electricity of copper interconnection structure
Chemical plating (Electrochemical Plating, abbreviation ECP) technique.
However, as feature sizes of semiconductor devices (Critical Dimension, abbreviation CD) is less and less, it is adjacent
The distance between metal layer becomes less and less, causes the capacitance that adjacent metal interlayer produces increasing, which also becomes
Parasitic capacitance, the capacitance not only influence the speed of service of semiconductor devices, and also the reliability of semiconductor devices is seriously affected.
In order to mitigate this problem, when forming interlayer dielectric layer and/or intermetallic dielectric layer, with low k dielectric substitution as aoxidized
The high-k dielectric materials such as silicon, to reduce the capacitance between adjacent metal layer.
For example, the preparation process of metal interconnection structure generally includes following step in the prior art：
S1：Referring to Fig. 1 a, low k oxide layer 2, passivation layer 3 and lithography layer 4 are sequentially depositing on the surface of interlayer dielectric layer 1；
S2：With continued reference to Fig. 1 a, photoetching is carried out to remove the lithography layer 4 of position to be etched, forms photoetching raceway groove 5；
S3：Referring to Fig. 1 b, perform etching to form metal interconnecting layer raceway groove 6, and then remove lithography layer 4；
S4：Referring to Fig. 1 c, one layer of metal seed layer 7 is first deposited in metal interconnecting layer raceway groove 6；
S5：Referring to Fig. 1 d, deposited metal interconnection layer 8 is with full of raceway groove 6；
S6：Referring to Fig. 1 e, the metal interconnecting layer 8 is planarized, and expose low k oxide layer 2；
S7：Referring to Fig. 1 f, barrier layer 9 is deposited to cover metal interconnecting layer 8 and low k oxide layer 2.
But after the characteristic size of semiconductor devices becomes smaller, the problem of parasitic capacitance, also becomes more serious, existing
Some low-k dielectric layer cannot be effectively reduced parasitic capacitance, so as to be unfavorable for reducing RC retardation ratio.Meanwhile low-k dielectric layer is big
K values are reduced using porous material more, but the thermodynamic stability of porous material is poor, can cause the 3D NAND of heat conductor
The semiconductor devices such as flash memory use reliability is deteriorated.In addition, with the reduction of metal connecting line layer minimum range and k values, leakage current
The problems such as also can be serious all the more.
Therefore, wish further to reduce the dielectric constant of interlayer dielectric layer and intermetallic dielectric layer in the industry, to solve
Parasitic capacitance and RC retardation ratio and its caused a series of problems, so as to improve the operation speed of the semiconductor devices such as 3D nand flash memories
Degree, and use reliability, this is endeavoured the direction of research by those skilled in the art always.
The content of the invention
It is an object of the invention to provide the preparation process of metal interconnection structure, can effectively improve 3D nand flash memories etc.
The speed of service of semiconductor devices, and use reliability.
To achieve these goals, the present invention proposes a kind of preparation process of metal interconnection structure, it is characterised in that bag
Include following steps：
Sacrifice layer, passivation layer and lithography layer are sequentially depositing on the surface of interlayer dielectric layer；
Photoetching is carried out to remove the lithography layer of position to be etched, forms photoetching raceway groove；
Perform etching to form metal interconnecting layer raceway groove, and then remove lithography layer；
One layer of metal seed layer is first deposited in metal interconnecting layer raceway groove；
Deposited metal interconnection layer is with full of raceway groove；
The metal interconnecting layer is planarized, and exposes sacrifice layer；
Sacrifice layer is removed to form air-gap (Air Gap)
Barrier layer is deposited to cover metal interconnecting layer and air-gap.
Further, the sacrifice layer is silicon nitride.
Further, the metal is copper (Cu).
Further, one layer of metal seed layer of the deposition, using physical vapour deposition (PVD) (Physical Vapor
Deposition, abbreviation PVD) technique.
Further, the deposited metal interconnection layer, using electrochemical plating (Electrochemical Plating, abbreviation
ECP) technique.
Further, the planarization material interconnection layer, using chemical mechanical milling tech (CMP).
Further, the removal sacrifice layer, using the wet-etching technology of phosphoric acid solution；
Further, the barrier layer is carbonitride of silicium.
Further, the interlayer dielectric layer is carbonitride of silicium.
Further, the passivation layer is silica.
Compared with prior art, the beneficial effects are mainly as follows：
First, air-gap (Air Gap) is prepared by using sacrifice layer to substitute low-k dielectric layer, and air-gap (Air
Gap) there is the dielectric constant (its permittivity of vacuum is about 1) lower than regular low k dielectric material, can more preferably play reduction
Parasitic capacitance, the effect for reducing RC retardation ratio；
Second, using silicon nitride as sacrifice layer, and phosphoric acid solution wet etching is used, can be effectively clear by sacrifice layer
Remove, even if air-gap also can be effectively prepared in the case of very small dimensions, while also avoid photoetching, etching and etc. caused by
The problem of cycle is elongated, damage device；
3rd, using carbonitride of silicium as barrier layer, its filling capacity is relatively poor, so as to avoid it sacrificial to removing
Air-gap after domestic animal layer carries out unwanted filling, so as to ensure the preparation of air-gap.
4th, blank medium of the air-gap as metal interconnecting layer, can effectively reduce current leakage, so as to improve device
Part performance.
By the above-mentioned technique of the present invention, effectively prepare air-gap, reduce parasitic capacitance, so as to improve 3D nand flash memories
Deng the speed of service of semiconductor devices, and use reliability.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this area
Technical staff will be clear understanding.Attached drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Limitation.And in whole attached drawing, identical component is denoted by the same reference numerals.In the accompanying drawings：
Fig. 1 a-f are the flow chart of the preparation process of metal interconnection structure in the prior art；
Fig. 2 a-f are the flow chart of the preparation process of metal interconnection structure in the present invention.
Embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although this public affairs is shown in attached drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.Conversely, there is provided these embodiments are to be able to be best understood from the disclosure, and can be by this public affairs
The scope opened completely is communicated to those skilled in the art.
For clarity, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to a large amount of implementation details are made to realize the specific objective of developer, such as according to related system or related business
Limitation, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expends
Time, but it is only to those skilled in the art routine work.
More specifically description is of the invention by way of example referring to the drawings in the following passage.Will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is using very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
A-f is please referred to Fig.2, in the present embodiment, it is proposed that the present invention proposes a kind of preparation work of metal interconnection structure
Skill, it comprises the following steps：
S100：Sacrifice layer, passivation layer and lithography layer are sequentially depositing on the surface of interlayer dielectric layer；
S200：Photoetching is carried out to remove the lithography layer of position to be etched, forms photoetching raceway groove；
S300：Perform etching to form metal interconnecting layer raceway groove, and then remove lithography layer；
S400：One layer of metal seed layer is first deposited in metal interconnecting layer raceway groove；
S500：Deposited metal interconnection layer is with full of raceway groove；
S600：The metal interconnecting layer is planarized, and exposes sacrifice layer；
S700：Sacrifice layer is removed to form air-gap (Air Gap)
S800：Barrier layer is deposited to cover metal interconnecting layer and air-gap.
Specifically, please referring to Fig.2 a, in the step s 100, step S110 is carried out first, in carbonitride of silicium (SiCN) interlayer
Dielectric layer 100 surface deposited silicon nitride (SiN) sacrifice layer 110；Step S120 is then carried out, in silicon nitride (SiN) sacrifice layer 110
Surface deposits one layer of silica (SiO2) passivation layer 120；Step S130 is then carried out, in silica (SiO2) 120 surface of passivation layer
Deposit one layer of lithography layer 130.
Please continue to refer to Fig. 2 a, in step s 200, common process is used to carry out photoetching to remove the light of position to be etched
Layer 130 is carved, forms photoetching raceway groove 140.
B is please referred to Fig.2, in step S300, step S310 is carried out first, uses common process to perform etching to form gold
Belong to interconnection layer raceway groove 150；Step S320 is then carried out, removes lithography layer 130.
C is please referred to Fig.2, in step S400, using physical vapour deposition (PVD) (Physical Vapor Deposition, letter
PVD) the thin metal copper seed layer 160 of one layer of process deposits to be to be referred to as that subsequent electrochemical plates (Electrochemical
Plating, abbreviation ECP) metal interconnecting layer use.
Please continue to refer to Fig. 2 c, in step S500, using electrochemical plating (ECP) technique, in metallic copper seed crystal surface
Deposited metal copper (Cu) 170 is with full of channel metal interconnection layer raceway groove 150.
D is please referred to Fig.2, in step S600, using chemical mechanical milling tech (CMP) planarization process metallic copper 170
Surface, forms copper metal interconnection layer 180, and exposes silicon nitride sacrificial layers 110.
E is please referred to Fig.2, in step S700, is removed and nitrogenized come wet etching using the wet-etching technology of phosphoric acid solution
Sacrificial silicon layer 110, to form air-gap (Air Gap) 190.Phosphoric acid solution has excellent silicon nitride etch selectivity, can have
Effect removes silicon nitride, so as to form air-gap 190 under very small dimensions.
F is please referred to Fig.2, in step S800, deposits carbonitride of silicium (SiCN) barrier layer 200 to cover interlayer dielectric layer
100 and metal interconnecting layer 180.
To sum up, air-gap (Air Gap) is prepared by using sacrifice layer to substitute low-k dielectric layer, and air-gap (Air
Gap) there is the dielectric constant (its permittivity of vacuum is about 1) lower than regular low k dielectric material, can more preferably play reduction
Parasitic capacitance, the effect for reducing RC retardation ratio；And using silicon nitride as sacrifice layer, and phosphoric acid solution wet etching is used,
Effectively sacrifice layer can be removed, even if also can effectively prepare air-gap in the case of very small dimensions, it also avoid subsequent optical
Carve, etching and etc. caused by the problem of cycle is elongated, damage device；And carbonitride of silicium is used as barrier layer, its filling
Performance is relatively poor, so as to avoid it from carrying out unwanted filling to the air-gap after removing sacrifice layer, so as to ensure sky
The preparation of air gap；Blank medium of the air-gap as metal interconnecting layer, can effectively reduce current leakage, so as to improve device
Performance.
The above-mentioned technique of the present invention, effectively prepares air-gap, reduces parasitic capacitance, so as to improve 3D nand flash memories etc. half
The speed of service of conductor device, and use reliability.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (10)
1. a kind of preparation process of metal interconnection structure, it is characterised in that comprise the following steps：
Sacrifice layer, passivation layer and lithography layer are sequentially depositing on the surface of interlayer dielectric layer；
Photoetching is carried out to remove the lithography layer of position to be etched, forms photoetching raceway groove；
Perform etching to form metal interconnecting layer raceway groove, and then remove lithography layer；
One layer of metal seed layer is first deposited in metal interconnecting layer raceway groove；
Deposited metal interconnection layer is with full of raceway groove；
The metal interconnecting layer is planarized, and exposes sacrifice layer；
Sacrifice layer is removed to form air-gap (Air Gap)
Barrier layer is deposited to cover metal interconnecting layer and air-gap.
2. preparation process according to claim 1, it is characterised in that：
The sacrifice layer is silicon nitride.
3. preparation process according to claim 1, it is characterised in that：
The metal is copper (Cu).
4. preparation process according to claim 1, it is characterised in that：
One layer of metal seed layer of the deposition, using physical vapour deposition (PVD) (Physical Vapor Deposition, abbreviation
PVD) technique.
5. preparation process according to claim 1, it is characterised in that：
The deposited metal interconnection layer, using electrochemical plating (Electrochemical Plating, abbreviation ECP) technique.
6. preparation process according to claim 1, it is characterised in that：
The planarization material interconnection layer, using chemical mechanical milling tech (CMP).
7. preparation process according to claim 1, it is characterised in that：
The removal sacrifice layer, using the wet-etching technology of phosphoric acid solution.
8. preparation process according to claim 1, it is characterised in that：
The barrier layer is carbonitride of silicium.
9. preparation process according to claim 1, it is characterised in that：
The interlayer dielectric layer is carbonitride of silicium.
10. preparation process according to claim 1, it is characterised in that：
The passivation layer is silica.
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| CN201711208507.6A CN107946238A (en) | 2017-11-27 | 2017-11-27 | A kind of preparation process of metal interconnection structure |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108550564A (en) * | 2018-06-12 | 2018-09-18 | 长江存储科技有限责任公司 | Form method, conductive interconnecting structure and the three-dimensional storage of conductive interconnecting structure |
| CN113380698A (en) * | 2021-05-13 | 2021-09-10 | 中国科学院微电子研究所 | Air gap manufacturing method, air gap and electronic device |
| CN113380743A (en) * | 2021-05-13 | 2021-09-10 | 中国科学院微电子研究所 | Chip unit, chip assembly and manufacturing method of chip unit |
| CN113644029A (en) * | 2021-08-12 | 2021-11-12 | 上海集成电路制造创新中心有限公司 | Metal interconnection structure and manufacturing method thereof |
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| CN103066014A (en) * | 2012-11-06 | 2013-04-24 | 上海集成电路研发中心有限公司 | Copper/ air gap preparation method |
| CN104319260A (en) * | 2014-10-29 | 2015-01-28 | 上海集成电路研发中心有限公司 | Method for forming air gaps among copper interconnection lines |
| CN107230658A (en) * | 2016-03-25 | 2017-10-03 | 中芯国际集成电路制造(上海)有限公司 | The method for forming the semiconductor devices with extension the air gap |
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| CN103066014A (en) * | 2012-11-06 | 2013-04-24 | 上海集成电路研发中心有限公司 | Copper/ air gap preparation method |
| CN104319260A (en) * | 2014-10-29 | 2015-01-28 | 上海集成电路研发中心有限公司 | Method for forming air gaps among copper interconnection lines |
| CN107230658A (en) * | 2016-03-25 | 2017-10-03 | 中芯国际集成电路制造(上海)有限公司 | The method for forming the semiconductor devices with extension the air gap |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108550564A (en) * | 2018-06-12 | 2018-09-18 | 长江存储科技有限责任公司 | Form method, conductive interconnecting structure and the three-dimensional storage of conductive interconnecting structure |
| CN108550564B (en) * | 2018-06-12 | 2024-06-07 | 长江存储科技有限责任公司 | Method for forming conductive interconnection structure, conductive interconnection structure and three-dimensional memory |
| CN113380698A (en) * | 2021-05-13 | 2021-09-10 | 中国科学院微电子研究所 | Air gap manufacturing method, air gap and electronic device |
| CN113380743A (en) * | 2021-05-13 | 2021-09-10 | 中国科学院微电子研究所 | Chip unit, chip assembly and manufacturing method of chip unit |
| CN113644029A (en) * | 2021-08-12 | 2021-11-12 | 上海集成电路制造创新中心有限公司 | Metal interconnection structure and manufacturing method thereof |
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Application publication date: 20180420 |