CN107946183A - A kind of mmic chip back side dicing lane manufacture craft based on photoresist - Google Patents
A kind of mmic chip back side dicing lane manufacture craft based on photoresist Download PDFInfo
- Publication number
- CN107946183A CN107946183A CN201711184640.2A CN201711184640A CN107946183A CN 107946183 A CN107946183 A CN 107946183A CN 201711184640 A CN201711184640 A CN 201711184640A CN 107946183 A CN107946183 A CN 107946183A
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- China
- Prior art keywords
- photoresist
- dicing lane
- back side
- manufacture craft
- chip back
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
Abstract
The present invention relates to a kind of mmic chip back side dicing lane manufacture craft based on photoresist, comprise the following steps：101st, crystal column surface is bombarded using gas ions；102nd, photoresist is injected in crystal column surface grounding through hole region, and cured under certain solidification temperature；103rd, dicing lane figure is produced on the wafer after the curing of grounding through hole region photoresist；104th, dicing lane is produced in dicing lane graphics field etching Au using wet-etching technology；105th, the photoresist of crystal column surface is removed.The present invention is by the way of gluing twice; first in MMIC grounding through hole area filling into photoresist; after cured; photoresist coating, exposure are carried out again, developing makes dicing lane figure to make dicing lane; mmic chip bottom layer gold can effectively be protected; back-side ground through-hole side wall and bottom layer gold are especially protected, so as to ensure the good grounded capacities of MMIC.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, and work is made more particularly to a kind of mmic chip back side dicing lane
Skill.
Background technology
GaAs is the semi-conducting material that most important, purposes is most wide in group Ⅲ-Ⅴ compound semiconductor.Electronics in GaAs moves
Shifting rate is 6 times of electron mobility in silicon (Si), its electronics peak shift speed is 2 times of Si.GaAs devices have high frequency, height
Speed, low-power consumption, noise be small, can single-chip integration the characteristics of.With the increasingly lifting of people's demand, GaAs MMIC have been widely used
In fields such as mobile communication, wifi.
In the frequency applications of MMIC, minimized for chip, convenient encapsulation considers, generally using microstrip line construction, i.e.,
While the function elements such as Embedded FET, capacitance, inductance, resistance, through hole (backside is grounded in chip back
Via), and electroplate 2~5um Au (gold).
In fact, after MMIC (monolithic integrated microwave circuit) chip back plating gold, since layer gold is thicker, and layer gold
With preferable ductility, for convenience of the cutting that mmic chip is last, it is necessary to carry out dicing lane making.Traditional approach generally uses
Photoresist, by exposure imaging, makes dicing lane figure, finally using wet-etching technology, produces dicing lane as mask.
Dicing lane making is carried out using traditional approach, mainly there is following contradiction：On the one hand since the MMIC back sides have ground connection to lead to
The presence in hole (depth is generally 75~150um, and aperture is 40~100um), in order to ensure photoresist energy good protection through hole bottom
The Au of portion and side wall layers, the general photoresist for selecting viscosity larger, while photoresist selects thickness larger, generally in more than 8um；
On the other hand, since photoresist thickness is big, it is existing easily to there is under-exposure, poor visualization etc. there are certain difficulty for exposure imaging
As, after causing wet etching Au, dicing lane distortion, a large amount of Au residuals in not straight or dicing lane, to works such as follow-up cutting, encapsulation
Skill causes to perplex.
The content of the invention
It is an object of the invention to provide a kind of mmic chip back side dicing lane manufacture craft, using the side of gluing twice
Formula, is first filled into photoresist in MMIC perforated, after cured, then carries out yellow light technique (gluing, exposure, development), makes
Dicing lane figure, using wet etching au layer removed, forms dicing lane.
To achieve these goals, the present invention provides following technical scheme：
The present invention provides a kind of mmic chip back side dicing lane manufacture craft, comprises the following steps：
101st, crystal column surface is bombarded using gas ions；
102nd, photoresist is injected in crystal column surface grounding through hole region, and cured under certain solidification temperature；
103rd, dicing lane figure is produced on the wafer after the curing of grounding through hole region photoresist；
104th, dicing lane is produced in dicing lane graphics field etching Au using wet-etching technology；
105th, the photoresist of crystal column surface is removed.
Further, in step 102 using be manually injected into or screen printing mode grounding through hole region inject photoresist.
Further, the solidification temperature of grounding through hole region photoresist is 90C-150C in step 102.
Yet further, ground connection via regions photoresist is cured using hot plate or baking oven in step 102.
Further, dicing lane figure is produced on wafer using yellow light technique in step 103.
Compared with prior art, the present invention has the following advantages：
A kind of mmic chip back side dicing lane manufacture craft based on photoresist of the present invention, using the side of gluing twice
Formula, first after cured, then carries out photoresist coating, exposure, development making stroke in MMIC grounding through hole area filling into photoresist
Film channel figure can effectively protect mmic chip bottom layer gold to make dicing lane, especially protect back-side ground through-hole side wall and
Bottom layer gold, so as to ensure the good grounded capacities of MMIC.
Below by drawings and examples, technical scheme is described in further detail.
Brief description of the drawings
Fig. 1 is the FB(flow block) of the embodiment of the present invention；
Fig. 2 is the original state structure diagram of the embodiment of the present invention；
Fig. 3 is that Fig. 2 passes through the structure diagram that photoresist is injected in grounding through hole；
Fig. 4 is the structure diagram that Fig. 3 produces dicing lane figure；
Fig. 5 is the structure diagram that Fig. 4 produces dicing lane；
Fig. 6 is structure diagrams of the Fig. 5 through removal photoresist；
Wherein, 1 is face portion, and 2 be substrate, and 3 be Au layers, and 4 be photoetching colloid, and 5 be photoresist layer, and 6 be dicing lane figure,
7 be dicing lane.
Embodiment
The embodiment of the present invention is illustrated below in conjunction with attached drawing, it will be appreciated that embodiment described herein is only used
In the description and interpretation present invention, it is not intended to limit the present invention.
Embodiment
A kind of mmic chip back side dicing lane manufacture craft provided in this embodiment, on the basis that chip front-end process is completed
On, carry out dicing lane manufacture craft.
First completing chip front-end process includes complete chip front side technique, chip thinning technique, grounding through hole technique, with
Completion includes face portion 1, substrate 2, the wafer of Au layers 3, referring to Fig. 2.
Referring to Fig. 1, the back side dicing lane manufacture craft of the present embodiment comprises the following steps that：
Step 101, using gas ions bombard crystal column surface.
Using the crystal column surface of plasma bombardment containing O2：Surface residual is removed, increases surface-active, strengthens surface attachment
Power.
Step 102, in crystal column surface grounding through hole region inject photoresist, and cures under certain solidification temperature.
Using being manually injected into or screen printing mode, photoresist is injected in MMIC grounding through hole region, and be formed by curing light
Photoresist body 4, referring to Fig. 3.Wherein, ground connection via regions photoresist is cured using hot plate or baking oven；Grounding through hole region
The solidification temperature of photoresist is 90C-150C, is typically 100C, 105C, 120C.And there is no photoetching then in no ground via regions
Glue, eliminates the big height of crystal column surface using photoetching colloid 4 and rises and falls.
Dicing lane figure is produced in step 103, the wafer after the curing of grounding through hole region photoresist.
Dicing lane figure 6 is produced on wafer using the yellow light technique for coating, exposing, developing including photoresist, wherein,
Coat photoresist and form photoresist layer 5, referring to Fig. 4.
Step 104, using wet-etching technology dicing lane graphics field etching Au produce dicing lane.
Dicing lane is completed using wet-etching technology to make, and is made using KI liquids in dicing lane graphics field etching Au layers 3
Dicing lane 7 is made, referring to Fig. 5.
Step 105, the photoresist for removing crystal column surface.
Removed photoresist using glue wet method, dry method remove photoresist or both removed by the way of combining crystal column surface include photoetching colloid and
The photoresist of photoresist layer, referring to Fig. 6.
Photoresist first is filled into MMIC perforated, after cured, then carries out existing dicing lane photoetching process (yellow light
Technique), i.e. gluing, exposure, development, makes dicing lane figure to make dicing lane, can effectively protect mmic chip bottom layer gold,
Especially protect back-side ground through-hole side wall and bottom layer gold.
It should be appreciated that the above embodiment of the present invention and example, are in order at description and interpretation purpose, not thereby limit this hair
Bright scope.The scope of the present invention is defined by claim, rather than by above-described embodiment and example definition.
Claims (9)
1. a kind of mmic chip back side dicing lane manufacture craft, it is characterised in that comprise the following steps：
101st, crystal column surface is bombarded using gas ions；
102nd, photoresist is injected in crystal column surface grounding through hole region, and cured under certain solidification temperature；
103rd, dicing lane figure is produced on the wafer after the curing of grounding through hole region photoresist；
104th, dicing lane is produced in dicing lane graphics field etching Au using wet-etching technology；
105th, the photoresist of crystal column surface is removed.
A kind of 2. mmic chip back side dicing lane manufacture craft according to claim 1, it is characterised in that the step 101
In gas ions be the gas ions comprising O2.
A kind of 3. mmic chip back side dicing lane manufacture craft according to claim 1, it is characterised in that the step 102
In, using be manually injected into or screen printing mode grounding through hole region inject photoresist.
A kind of 4. mmic chip back side dicing lane manufacture craft according to claim 1, it is characterised in that the step 102
In, the solidification temperature of grounding through hole region photoresist is 90C-150C.
A kind of 5. mmic chip back side dicing lane manufacture craft according to claim 4, it is characterised in that the step 102
In, the solidification temperature of grounding through hole region photoresist is 100C, 105C, 120C.
A kind of 6. mmic chip back side dicing lane manufacture craft according to claim 1, it is characterised in that the step 102
In, ground connection via regions photoresist is cured using hot plate or baking oven.
A kind of 7. mmic chip back side dicing lane manufacture craft according to claim 1, it is characterised in that the step 103
In, dicing lane figure is produced on wafer using yellow light technique.
A kind of 8. mmic chip back side dicing lane manufacture craft according to claim 1, it is characterised in that the wet etching
Technique is using KI liquids etching Au.
A kind of 9. mmic chip back side dicing lane manufacture craft according to claim 1, it is characterised in that the step 105
In, remove photoresist by the way of wet method is removed photoresist and/or dry method is removed photoresist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711184640.2A CN107946183A (en) | 2017-11-23 | 2017-11-23 | A kind of mmic chip back side dicing lane manufacture craft based on photoresist |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711184640.2A CN107946183A (en) | 2017-11-23 | 2017-11-23 | A kind of mmic chip back side dicing lane manufacture craft based on photoresist |
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| Publication Number | Publication Date |
|---|---|
| CN107946183A true CN107946183A (en) | 2018-04-20 |
Family
ID=61930141
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711184640.2A Pending CN107946183A (en) | 2017-11-23 | 2017-11-23 | A kind of mmic chip back side dicing lane manufacture craft based on photoresist |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112838057A (en) * | 2021-01-08 | 2021-05-25 | 江苏东海半导体科技有限公司 | Scribing method suitable for IGBT semiconductor device |
| CN114171500A (en) * | 2021-12-07 | 2022-03-11 | 成都海威华芯科技有限公司 | Layout positioning mark drawing method, chip and wafer prepared based on layout positioning mark drawing method |
| CN116676571A (en) * | 2023-04-26 | 2023-09-01 | 武汉敏芯半导体股份有限公司 | Electrode manufacturing method, electrode and semiconductor device |
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| CN116676571A (en) * | 2023-04-26 | 2023-09-01 | 武汉敏芯半导体股份有限公司 | Electrode manufacturing method, electrode and semiconductor device |
| CN116676571B (en) * | 2023-04-26 | 2024-01-19 | 武汉敏芯半导体股份有限公司 | Electrode manufacturing method, electrode and semiconductor device |
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Application publication date: 20180420 |