CN107918596A - A kind of SOC chip and frequency signal processing method - Google Patents
A kind of SOC chip and frequency signal processing method Download PDFInfo
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Abstract
The invention discloses a kind of SOC chip and frequency signal processing method, wherein SOC chip includes：Non- connection module coprocessor and non-switched letter module, non-switched letter module, is electrically connected with non-connection module coprocessor, including preliminary wake-up module and clock and data recovery module；Preliminary wake-up module, is electrically connected with non-connection module coprocessor, for the field strength of radiofrequency field where detecting SOC chip, when detecting that field strength is more than preset value, sends first to non-connection module coprocessor and wakes up instruction；Non- connection module coprocessor, is electrically connected with clock and data recovery module；Clock and data recovery module, enters working status for waking up instruction according to first, extracts the clock signal of input radio frequency signal, and sent according to clock signal to non-connection module coprocessor and wake up indication signal；Non- connection module coprocessor, is additionally operable to determine whether to wake up SOC chip according to wake-up indication signal.Realizing reduces SOC chip power consumption.
Description
Technical Field
The embodiment of the invention relates to a wireless communication technology, in particular to an SOC chip and a radio frequency signal processing method.
Background
With the continuous development of wireless Communication technology, the application of the payment mode of NFC (Near Field Communication) is more and more extensive, and an NFC front-end chip is integrated in an intelligent terminal such as a smart phone and a smart band, so that the intelligent terminal has functions of NFC payment and the like, and the convenience of user payment is improved.
However, when the rf front-end chip is disposed in the intelligent terminal, along with the improvement of the complexity of the application environment, in order to meet the payment requirement of the rf chip, an operating system is added in the rf chip, and the rf chip operates in cooperation with the host, but due to the increase of the operating system and the like, the power consumption of the rf chip is too large, and the user experience is poor.
Disclosure of Invention
The invention provides an SOC chip and a radio frequency signal processing method, which aim to reduce the power consumption of a radio frequency chip.
In a first aspect, an embodiment of the present invention provides an SOC chip, including: a non-connected module co-processor and a non-connected communication module, wherein,
the non-connection communication module is electrically connected with the non-connection module coprocessor and comprises a primary awakening module and a clock data recovery module;
the primary awakening module is electrically connected with the non-connection module coprocessor and is used for detecting the field intensity of a radio frequency field where the SOC chip is located and sending a first awakening instruction to the non-connection module coprocessor when the field intensity is detected to be larger than a preset value;
the non-connection module coprocessor is electrically connected with the clock data recovery module and used for sending the first wake-up instruction to the clock data recovery module;
the clock data recovery module is used for entering a working state according to the first wake-up instruction, extracting a clock signal of an input radio frequency signal and sending a wake-up indication signal to the non-connection module coprocessor according to the clock signal;
the non-connected module coprocessor is further used for determining whether to wake up the SOC chip according to the wake-up indication signal.
In a second aspect, an embodiment of the present invention further provides a radio frequency signal processing method, where the method includes:
acquiring an input radio frequency signal and acquiring the signal intensity of the input radio frequency signal;
if the signal intensity is detected to be larger than a preset value, generating a first awakening instruction, and powering on the SOC chip according to the first awakening instruction;
extracting a clock signal of the input radio frequency signal, judging whether the clock signal is in a stable state according to a preset rule, generating a wakeup indication instruction according to a judgment result, and determining whether to wakeup the SOC chip according to the wakeup indication instruction.
According to the embodiment of the invention, the field intensity and the clock signal of the input radio frequency signal are respectively detected by the primary awakening module and the clock data recovery module, the secondary awakening mechanism is set, and the SOC chip can be essentially awakened only when the SOC chip is in a stable radio frequency field, so that the problems of frequent false start and overlarge power consumption of the SOC chip caused by high sensitivity of the SOC chip or more external noise signals are solved, and the reduction of the power consumption of the SOC chip is realized.
Drawings
Fig. 1 is a schematic structural diagram of an SOC chip according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an SOC chip according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a non-communication module according to an embodiment of the present invention;
fig. 4 is a flowchart of a radio frequency signal processing method according to a second embodiment of the present invention;
fig. 5 is a flowchart of radio frequency signal processing according to a second embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a schematic structural diagram of an SOC chip according to an embodiment of the present invention, where the SOC chip may be integrated in an intelligent terminal such as a smart phone, a bracelet, or a smart watch, and used as a radio frequency analog tag to implement a secure and reliable NFC (Near Field Communication) payment function.
Referring to fig. 1, the SOC (System on Chip) Chip specifically includes: a non-interface module co-processor 110 and a non-interface communication module 120.
The non-connection communication module 120 is electrically connected with the non-connection module coprocessor 110 and comprises a preliminary wake-up module 121 and a clock data recovery module 122;
the preliminary wake-up module 121 is electrically connected to the non-connected module coprocessor 110, and configured to detect a field intensity of a radio frequency field in which the SOC chip is located, and send a first wake-up instruction to the non-connected module coprocessor 110 when the field intensity is detected to be greater than a preset value;
the non-connection module coprocessor 110 is electrically connected with the clock data recovery module 122 and is used for sending the first wake-up instruction to the clock data recovery module 122;
the clock data recovery module 122 is configured to enter a working state according to the first wake-up instruction, extract a clock signal of the input radio frequency signal, and send a wake-up instruction signal to the non-interface module coprocessor 110 according to the clock signal;
the non-module co-processor 110 is further configured to determine whether to wake up the SOC chip according to the wake-up indication signal.
In this embodiment, the preliminary wake-up module may be connected to the terminal antenna, and may acquire the radio frequency input signal, and detect the field strength of the radio frequency field in which the SOC chip is located through the radio frequency input signal. For example, if the field strength is greater than the preset value, it indicates that the SOC chip is located in the radio frequency field, and performs preliminary wake-up on the SOC chip, otherwise, it indicates that the SOC chip is not located in the radio frequency field, and the SOC chip continues to maintain the non-wake-up state.
In this embodiment, when it is detected that the SOC chip is located in the radio frequency field, the preliminary wake-up module 121 sends a first wake-up instruction to the non-connected module coprocessor 110, and the non-connected module coprocessor 110 receives the first wake-up instruction and sends the first wake-up instruction to each module of the SOC chip to perform preliminary wake-up on each module of the SOC chip, where the preliminary wake-up refers to performing power-up processing on each module, and illustratively, each module may complete output wake-up within several hundred microseconds.
After the clock data recovery module 122 is initially awakened, it receives an input rf signal, extracts a clock signal of the input rf signal, detects whether the clock signal is a spurious signal, i.e., determines whether the clock signal is a stable clock signal, and determines an awakening indication signal according to the detection result, wherein the spurious signal may be a noise signal. The wake-up indication signal may be a second wake-up signal or a cancel wake-up signal, for example, if a noise signal exists in the clock signal, the cancel wake-up signal is generated to cancel the wake-up of the SOC chip; and if the clutter signals do not exist in the clock signals, generating a second wake-up signal to wake up the SOC chip for the second time.
According to the technical scheme, the field intensity and the clock signal of the input radio-frequency signal are detected through the primary awakening module and the clock data recovery module respectively, the secondary awakening mechanism is arranged, the SOC chip can be essentially awakened only when the SOC chip is in a stable radio-frequency field, the problems that the SOC chip is frequently started by mistake due to the fact that the sensitivity of the SOC chip is high or external noise signals are more, power consumption is overlarge are solved, and the reduction of the power consumption of the SOC chip is achieved.
Optionally, the preliminary wake-up module 121 includes a field intensity detection circuit 1211 and a power management unit 1212; wherein,
the field intensity detection circuit 1211 is electrically connected with the power management unit 1212, and is configured to detect a field intensity of the input radio frequency signal, and send a first start instruction to the power management unit 1212 when detecting that the field intensity of the input radio frequency signal is greater than a preset value;
the power management unit 1212 is electrically connected to the non-connected module coprocessor 110, and the user enters a working state according to the first start instruction and sends a first wake-up instruction to the non-connected module coprocessor 110.
In this embodiment, the field intensity of the input rf signal is detected by the field intensity detection circuit 1211. The power management unit 1212 is configured to perform power-on management on the SOC chip, and send a first wake-up instruction to the non-connected module coprocessor 110 after starting according to the first start instruction, and perform preliminary wake-up on each module of the SOC chip, that is, when the SOC chip does not enter the radio frequency field, each module of the SOC chip is in a non-power-on state, so that power consumption of each module when the module is not in the radio frequency field is reduced, and power consumption of the SOC chip is further reduced.
Optionally, the clock data recovery module 122 is specifically configured to: acquiring frequency information and amplitude information of a clock signal, and determining whether the frequency information meets a first preset condition and whether the amplitude information meets a second preset condition; if yes, generating a second wake-up signal, and if not, generating a cancel wake-up signal.
The clock data recovery module 122 determines whether the SOC chip is in a stable rf field by identifying the frequency signal and the amplitude information of the clock signal. In this embodiment, the first preset condition may be that the frequency information is within a preset frequency range and has regularity, for example, the frequency information may have periodicity or no irregular abrupt change. The second preset condition may be that the amplitude information is within a preset amplitude range and has regularity, for example, the amplitude information may have periodicity or no irregular abrupt change.
The non-interface module coprocessor 110 is specifically configured to: awakening the SOC chip according to the second awakening signal and processing the input radio frequency signal; or, powering off the SOC chip according to the cancel wake-up signal.
In this embodiment, the non-connected module coprocessor 110 determines that the SOC chip does not enter the stable radio frequency field when the second wake-up instruction is not received within the preset time after receiving the first wake-up instruction or when a wake-up cancellation signal is received, and performs power-down processing on the SOC chip. Wherein the preset time may be a preset millisecond.
In the embodiment, whether the SOC chip is awakened or not is judged by accurately inputting whether the radio frequency signal is a stable signal or not, and whether a radio frequency field is carried out or not is not only taken as a basis, so that the condition that the SOC chip is not started is reduced, and the power consumption caused by false starting is reduced.
In this embodiment, the SOC chip further includes a Central Processing Unit (CPU) core 130, an Advanced Peripheral Bus (APB) 150, an Advanced high performance Bus (AHB) 140, and an AHB to APB Bus bridge 160. The CPU core is used for responding communication information of external equipment and is connected with the AHB bus, the AHB bus and the APB bus are connected based on an AHB to APB bus bridge, the AHB bus can also be connected with a plurality of high-speed peripherals, and the APB bus can also be connected with a plurality of low-speed peripherals. For example, referring to fig. 2, fig. 2 is a schematic structural diagram of an SOC chip according to a first embodiment of the present invention.
Optionally, the system further includes a global clock management module 170, electrically connected to the AHB bus 140, configured to generate a modulation clock signal according to the reference clock signal and a configuration file sent by the CPU core, and adjust a clock frequency of the APB bus and a working state of a peripheral electrically connected to the APB bus according to the modulation clock signal, where the configuration file includes working clock information of the APB bus and the peripheral.
The reference clock signal is preset in the global clock management module 170, and may be related to the physical property of each peripheral, for example. The configuration file is determined by the CPU core in real time according to the operation states of the APB bus and the peripheral devices. The global clock management module 170 combines the configuration information and the reference clock signal to generate modulation clock signals of the APB bus and each peripheral, and adjusts the frequency of PCLK of the APB bus and the operating states of the peripherals connected to the APB bus according to the modulation clock signals through the AHB to APB bus bridge 160, wherein the operating states include an enable state and an off state.
It should be noted that, the global clock management module 170 and the CPU core both power up according to the first wake-up signal and power down according to the cancel wake-up signal.
In the embodiment, the global clock management module is arranged to control the clock frequency of the APB bus and the working state of the peripheral connected with the APB bus, so that each peripheral is turned off when in a non-working state, and power consumption caused by the fact that each peripheral is in an enabling state for a long time is reduced.
Optionally, the CPU core 130 is an 16/32bit mixed instruction CPU core.
The 16/32bit mixed instruction CPU core has the following two dimensions: the control system comprises a 16-bit instruction and a 32-bit instruction, wherein the 16-bit instruction is small in operation power consumption and low in operation speed, and correspondingly, the 32-bit instruction is large in operation power consumption and high in operation speed. The CPU core 130 determines different operation dimensions according to different operation states. CPU core 130 obtains current operating parameters, which may include, but are not limited to, address range and operand length. For example, if the address range is smaller than the first threshold or the operand length is smaller than the second threshold, the CPU core 130 executes a 16-bit instruction; if the address range is greater than or equal to the first threshold value and the operand length is greater than or equal to the second threshold value, the CPU core 130 executes a 32-bit instruction.
In the embodiment, the operation dimensionality of the CPU kernel is determined according to the current operation parameters, and the operation times of the 16-bit instruction is greater than that of the 32-bit instruction, so that the operation speed and the operation power consumption are considered, and the total operation power consumption is reduced.
Optionally, the off-hook communication module 120 further includes a variable gain amplifier 123, an indication circuit 124, and an analog demodulator 125. For example, referring to fig. 3, fig. 3 is a schematic structural diagram of a non-contact communication module according to an embodiment of the present invention. Wherein the content of the first and second substances,
the variable gain amplifier 123 is configured to amplify an input radio frequency signal according to a current gain in an awake state, and output a carrier signal;
the indicating circuit 124 is electrically connected with the variable gain amplifier 123 and the non-connection module coprocessor respectively, and is used for extracting a first voltage of a carrier signal, generating an indicating signal according to the first voltage and an internal reference voltage, and sending the indicating signal to the non-connection module coprocessor;
the analog demodulator 125 is electrically connected with the variable gain amplifier 123 and the non-connection module coprocessor and is used for analyzing the carrier signal and sending a generated analysis instruction to the non-connection module coprocessor;
the non-connected module coprocessor 110 is electrically connected with the CPU core 130 based on the APB bus 150 and the AHB bus 140, and is further configured to send an indication signal and an analysis instruction to the CPU core 130, where the APB bus 150 and the AHB bus 140 are connected by an AHB toAPB bus bridge 160;
the CPU core 130 is configured to generate a gain adjustment signal according to the indication signal, send the gain adjustment signal to the non-interface module coprocessor 110, and generate a return parameter according to a corresponding parsing instruction when the indication signal meets a preset condition;
the non-connection module coprocessor 110 is electrically connected to the variable gain amplifier 123, and is further configured to send a gain adjustment signal to the variable gain amplifier 123, so that the variable gain amplifier 123 adjusts a current gain, and perform signal amplification on the input radio frequency signal according to a first amplification gain generated by the adjustment.
In this embodiment, the variable gain amplifier 123 has a variable gain function, and can amplify the input rf signal to different degrees according to different amplification gains. Illustratively, the input radio frequency signal may be a radio frequency signal transmitted by a card reader and carrying the interaction instruction. Here, the current gain refers to a gain stored in the variable gain amplifier 123 when the input radio frequency signal is input to the variable gain amplifier 123.
When receiving the input radio frequency signal, the variable gain amplifier 123 amplifies the radio frequency signal according to the current gain to generate a carrier signal, where the carrier signal also carries the interactive instruction of the input radio frequency signal. The output of the variable gain amplifier 123 is connected to the input of the indication circuit 124, and the carrier signal is sent to the indication circuit 124, and the indication circuit 124 extracts a first voltage of the carrier signal, wherein the first voltage may be an envelope of the carrier signal. Optionally, the Indication circuit 124 may be an RSSI (Received Signal Strength Indication) indicator. The operation principle of the indicating circuit 124 is to compare the first voltage of the carrier signal with the internal reference voltage and generate a 2-bit indicating signal according to the comparison result. For example, if the indication signal generated by the indication circuit 124 is 01 or 10, it indicates that the carrier signal is in a normal state, and further it is known that the input radio frequency signal is in a normal state, and the current gain of the variable gain amplifier 123 does not need to be adjusted; if the indication signal generated by the indication circuit 124 is 00, it indicates that the carrier signal becomes small, and further it is known that the input radio frequency signal becomes small and the current gain of the variable gain amplifier 123 needs to be increased; if the indication signal generated by the indication circuit 124 is 11, it indicates that the carrier signal is increased, and it is further known that the input rf signal is increased and the current gain of the variable gain amplifier 123 needs to be decreased.
The non-interface module coprocessor 110 receives the indication signal sent by the indication circuit 124 and sends the indication signal to the CPU core 130, wherein the transmission path of the indication signal is the non-interface module coprocessor 110, the APB bus 150, the AHB toAPB bus bridge 160, the AHB bus 140 and the CPU core 130 in sequence.
The CPU core 130 receives the indication signal, generates a gain adjustment signal according to the indication signal, and sends the gain adjustment signal to the non-interface coprocessor 110, where the transmission path of the gain adjustment signal includes the CPU core 130, the AHB bus 140, the AHB to APB bus bridge 160, the APB bus 150, and the non-interface coprocessor 110.
The non-interface module coprocessor 110 sends the gain adjustment signal to the variable gain amplifier 123, wherein the gain adjustment signal includes a gain increase signal, a gain decrease signal and a gain hold signal. If the gain adjustment signal is a gain increase signal or a gain decrease signal, the variable gain amplifier 123 adjusts the current gain according to the gain adjustment signal, re-amplifies the input rf signal according to the adjusted gain, and repeats the above steps until the indication circuit 124 generates an indication signal of 01 or 10.
In this embodiment, the gain adjustment of the variable gain amplifier is performed iteratively, and different first amplification gains are determined for different input radio frequency signals, so that the problem that the input radio frequency signals are too large or too small to be processed or the processing error is large is solved, the radio frequency signals sent by radio frequency devices at different distances can be received and processed, the receiving sensitivity and the anti-interference capability of the radio frequency signals are improved, and the size requirement of the terminal antenna can be reduced.
The input end of the analog demodulator 125 is connected to the input end of the variable gain amplifier 123, receives the carrier signal sent by the variable gain amplifier 123, analyzes the carrier signal, extracts an analysis instruction of the carrier signal, and sends the analysis instruction to the non-interface module coprocessor 110.
The non-interface module coprocessor 110 may send the parsing instruction to the CPU core 130 when the indication signal satisfies the predetermined condition. The preset condition of the indication signal may be 01 or 10, that is, the indication signal corresponding to the gain holding signal satisfies the preset condition. The transmission path of the analysis command is the same as the transmission path of the instruction signal.
The CPU core 130 receives the parsing instruction and generates a return parameter, where the return parameter is a response parameter of the parsing instruction, and for example, if the parsing instruction is a card reading instruction, the return parameter is current card data information. The CPU core 130 sends the generated return parameter to the non-interface module coprocessor 110.
Optionally, the SOC chip further includes a memory for storing relevant data of the SOC chip, for example, the relevant data includes current card data information, the memory is connected to the AHB bus 140, when the CPU core 130 generates return data, the return data is sent to the memory for verification, and is sent to the non-connected module coprocessor 110 when verification is successful, and the transmission path of the return parameter is the CPU core 130, the AHB bus 140, the memory, the AHB bus 140, the AHB to APB bus bridge 160, the APB bus 150, and the non-connected module coprocessor 110.
In this embodiment, the indication circuit compares the first voltage of the carrier signal amplified by the determined variable gain amplifier with the internal reference voltage to generate the adjustment indication signal of the variable gain amplifier, so that the control circuit controls the variable gain amplifier to adjust the amplification gain of the variable gain amplifier, thereby determining suitable amplification gains for input radio frequency signals of different sizes, and improving the receiving sensitivity and the anti-interference capability of the radio frequency front-end chip for the radio frequency signals.
Optionally, the non-communication module 120 further includes: a data synchronization module 126 and an amplifier 127. Referring to fig. 3, in which,
the CPU core 130 is further configured to generate a state control signal according to the indication signal, and send the state control signal to the clock data recovery module 122 based on the non-interface module coprocessor 110;
the clock data recovery module 122 is electrically connected to the variable gain amplifier 123, and is configured to receive the state control signal, switch the operating state according to the state control signal, extract a clock signal of the carrier signal in the enabled state, send the clock signal to the non-interface module coprocessor 110, and generate an amplifier control signal that is homologous to the clock signal, where the operating state includes an enabled state and a suspended state;
the non-connected module coprocessor 110 is further configured to generate return data according to the clock signal and the return parameter;
a data synchronization module 126 electrically connected to the clock data recovery module 122 and the non-connection module coprocessor 110, respectively, for synchronizing the clock signal and the return data to generate a modulation signal;
and the amplifier 127 is electrically connected with the clock data recovery module 122 and the data synchronization module 126, and is configured to amplify the modulated signal to generate an output radio frequency signal, and dissipate energy after the output radio frequency signal is output according to the amplifier control signal.
In this embodiment, the CPU core 130 generates a state control signal for controlling the operating state of the clock data recovery module 122 according to the indication signal while receiving the indication signal. For example, the state control signal may be composed of logic "0" and logic "1", for example, when the state control signal is set to "0", the clock data recovery module 122 may be in a suspend state, and when the state control signal is set to "1", the clock data recovery module 122 may be in an enable state. Wherein, when the indication signal is 01 or 10, the state control signal may be set to "1", and when the indication signal is 11 or 00, the state control signal may be set to "0".
The clock data recovery module 122 receives the state control signal, switches the operating state according to the state control signal, does not receive the carrier signal sent by the variable gain amplifier 123 if the operating state is in the pause state, and receives the carrier signal and extracts the clock signal of the carrier signal if the operating state is in the enable state.
The non-interface module coprocessor 110 receives the clock signal sent by the clock data recovery module 122 and the return parameter sent by the CPU core 130, loads the return parameter on the clock signal, and generates return data, where the return data is a carrier signal carrying the return parameter.
The data synchronization module 126 synchronizes the clock signal with the return data, eliminates time delays in the return data, and makes the generated modulated signal have the same frequency as the clock signal.
In this embodiment, since the clock signal needs to pass through a multi-stage program in the process of generating the return data by the non-link module coprocessor 110, the generated return data is prone to have delay, and in order to avoid an error caused by time delay, the return data and the clock signal are synchronized to generate a modulation signal having the same frequency as the clock signal. The amplified adjusted signal is determined to be an output radio frequency signal.
In this embodiment, the operating state of the clock data recovery module 122 is controlled by the state control signal, that is, the clock data recovery module enters the enable state only after the amplification gain adjustment of the variable gain amplifier is completed, so that the problem of signal confusion caused by the fact that the output radio frequency signal generated in the amplification gain adjustment process of the variable gain amplifier is collected by the terminal antenna again is avoided, and the interference of irrelevant signals is reduced.
In this embodiment, the amplifier 127 is configured to amplify the modulated signal, so that the generated output radio frequency signal has higher sensitivity, the output sensitivity of the radio frequency signal is improved, and the size requirement of the terminal antenna can be reduced.
In this embodiment, the amplifier control signal is homologous to the clock signal of the carrier signal and is used to control the amplifier 127, and when the amplifier 127 finishes transmitting the output radio frequency signal, the energy remaining in the amplifier 127 is dissipated, so as to prevent the residual energy from affecting the transmission of the subsequent output radio frequency signal.
Optionally, the CPU core 130 is further configured to, when the indication signal meets a preset condition, obtain a first amplification gain of the variable gain amplifier 123, determine a second amplification gain according to the first amplification gain, and send the second amplification gain to the non-connection module coprocessor 110, where the second amplification gain is matched with the first amplification gain;
the non-interface module coprocessor 110 is electrically connected to the amplifier 127, and is further configured to send the second amplification gain to the amplifier 127, so that the amplifier 127 performs signal amplification on the modulated signal according to the second amplification gain.
In this embodiment, the amplification gain of the amplifier 127 is adjustable, and the second amplification gain of the amplifier 127 is related to the first amplification gain of the variable gain amplifier 123. Optionally, the CPU core 130 is provided with a corresponding list or a corresponding functional relationship between the first amplification gain and the second amplification gain, and the second amplification gain can be quickly and reliably obtained according to the first amplification gain. Optionally, the second amplification gain is positively correlated with the first amplification gain. For example, if the first amplification gain of the variable gain amplifier 123 is closer, it indicates that the distance between the external communication device such as a card reader and the terminal where the SOC chip is located is smaller, and the field strength of the radio frequency field is larger, and it is further known that the amplification capability of the amplifier 127 should be reduced; accordingly, if the first amplification gain of the variable gain amplifier 123 is relatively large, it indicates that the external communication device, such as a card reader, is relatively far away from the terminal where the SOC chip is located, and the field strength of the radio frequency field is small, so that it is further known that the amplification capability of the amplifier 127 should be improved.
In this embodiment, the distance between the external communication device and the terminal where the SOC chip is located is represented by the first amplification gain, and the second amplification gain matched with the distance is determined, so that the generated output radio frequency signal is matched with the distance, the problem that the output radio frequency signal determined by the fixed gain is too large or too small and exceeds the communication distance of the external communication device is solved, and the applicability of the output radio frequency signal is improved.
Optionally, the SOC chip further includes a security module 180, where the security module 180 is electrically connected to the APB bus 150, and is configured to receive an analysis instruction sent by the non-connected module coprocessor 110 based on the APB bus 150, perform security verification on the analysis instruction, generate verification information, and send the verification information to the non-connected module coprocessor 110 based on the APB bus 150;
the non-connection module coprocessor 110 is further configured to combine the return parameter with the clock signal of the carrier signal to generate return data when the verification information is successful, and discard the return parameter when the verification information is unsuccessful.
In this embodiment, in order to improve the security of the communication between the rf front-end chip and the external device, the security module 180 is used to perform security verification on the parsing instruction, and communicates with the non-connection module coprocessor 110 through the APB bus 150.
The security module 180 receives the parsing instruction sent by the non-link module coprocessor 110, and feeds back verification information after verification, wherein if the feedback information is verification success, the non-link module coprocessor 110 performs an operation of combining the return parameter with the clock signal of the carrier signal to generate return data, and if the feedback information is verification failure, the control circuit 140 interrupts the response to the input radio frequency signal and discards the return parameter.
In the embodiment, the safety of communication between the SOC chip and the external equipment is improved through the safety verification of the analysis instruction.
Optionally, the SOC chip further includes a communication interface, which is connected to the APB bus 150 and used for encoding transmission data, and the communication interface may be, for example, a private GPIO (General Purpose Input/Output) interface or an SWP (Single Wire Protocol) interface. The communication interface is arranged to encode the transmission data, so that the safety and reliability of data transmission between the radio frequency front-end chip and the external security module are improved, and the problems of data loss or leakage and the like in the data transmission process are avoided.
Example two
Fig. 4 is a flowchart of a radio frequency signal processing method according to a second embodiment of the present invention, where this embodiment is applicable to a situation where an SOC chip in an intelligent terminal processes a radio frequency signal, and the method can be executed by the SOC chip according to the second embodiment of the present invention. The method specifically comprises the following steps:
s210, acquiring an input radio frequency signal and acquiring the signal intensity of the input radio frequency signal.
In this embodiment, the field intensity of the radio frequency field in which the SOC chip is located is represented by the signal intensity of the input radio frequency signal.
And S220, if the signal intensity is detected to be larger than the preset value, generating a first awakening instruction, and powering on the SOC chip according to the first awakening instruction.
If the detected signal intensity is larger than the preset value, the SOC chip is located in a radio frequency field, and the SOC chip is preliminarily awakened through a first awakening instruction, wherein the preliminary awakening refers to the step of conducting power-on processing on each module of the SOC chip.
S230, extracting a clock signal of the input radio frequency signal, judging whether the clock signal is in a stable state according to a preset rule, generating a wakeup indication instruction according to a judgment result, and determining whether to wakeup the SOC chip according to the wakeup indication instruction.
And determining whether the radio frequency field in which the SOC chip is positioned is a stable radio frequency field by further judging whether the clock signal of the input radio frequency signal is in a stable state. The radio frequency field comprises a stable radio frequency field and a clutter radio frequency field, the stable radio frequency field refers to a radio frequency field emitted by external communication equipment such as a card reader, and the clutter radio frequency field refers to a radio frequency field formed by a noise signal.
Optionally, step S230 includes: acquiring frequency information and amplitude information of a clock signal, and determining whether the frequency information meets a first preset condition and whether the amplitude information meets a second preset condition;
if so, generating a second wake-up signal, waking up the SOC chip according to the second wake-up signal, and processing the input radio frequency signal;
and if not, generating a cancel awakening signal, and powering off the SOC chip according to the cancel awakening signal.
In this embodiment, whether the radio frequency field in which the SOC chip is located is a stable radio frequency field is determined according to the frequency information and the amplitude information of the clock signal. When the radio frequency field is not stabilized, the SOC chip is powered down, and power consumption caused by the power-up state of the SOC chip is reduced.
Optionally, referring to fig. 5, fig. 5 is a flowchart of radio frequency signal processing according to a second embodiment of the present invention, where processing an input radio frequency signal includes:
s310, an input radio frequency signal is obtained, and a first amplification gain of the input radio frequency signal is determined.
Wherein, a corresponding first amplification gain is determined for each input radio frequency signal, wherein the first amplification gain can be determined through a plurality of iterative adjustments, and the receiving sensitivity of the radio frequency signal is improved by adjusting the first amplification gain.
Optionally, step S310 includes: performing signal amplification on an input radio frequency signal according to the current gain to generate a carrier signal; extracting a first voltage of the carrier signal, comparing the first voltage with an internal reference voltage, and determining an indication signal according to a comparison result; and generating a gain adjusting signal according to the indicating signal, adjusting the current gain according to the gain adjusting signal, and determining a first amplification gain.
Optionally, the determining the amplification gain includes determining a gain of the current gain according to the gain adjustment signal, where the gain adjustment signal includes a gain increase signal, a gain decrease signal, and a gain hold signal, and the determining the amplification gain includes: if the gain adjusting signal is a gain increasing signal, the first amplification gain is the sum of the current gain and the reference gain, and the indicating signal is determined again; if the gain adjusting signal is a gain reducing signal, the first amplification gain is the difference between the current gain and the reference gain, and the indicating signal is determined again; and if the gain adjusting signal is a gain maintaining signal, stopping adjusting the current gain, and determining the current gain as the first amplification gain.
The reference gain refers to a gain change amount per gain adjustment. In this embodiment, when it is detected that the gain adjustment signal is the gain hold signal, it is determined that the gain adjustment is completed, and subsequent processing is performed on the carrier signal generated by the determined amplification gain processing.
And S320, performing signal amplification on the input radio frequency signal according to the amplification gain to generate a carrier signal.
S330, extracting an analysis instruction carried by the carrier signal, and generating a return parameter according to the analysis instruction.
And S340, combining the return parameters with the clock signal of the carrier signal to generate an output radio frequency signal.
Optionally, S340 includes: merging the return parameters with the clock signals of the carrier signals to generate return data; synchronizing the returned data with a clock signal of the carrier signal to generate a modulation signal; and amplifying the modulated signal to generate and output a radio frequency signal.
In this embodiment, the modulation signal is signal-amplified, so that the generated output radio frequency signal has higher sensitivity, and the output sensitivity of the radio frequency signal is improved.
Optionally, before the signal amplification is performed on the modulated signal, the method further includes: determining a second amplification gain according to the first amplification gain, wherein the second amplification gain is matched with the first amplification gain; and amplifying the modulation signal according to the second amplification gain.
In this embodiment, the distance between the external communication device and the terminal where the SOC chip is located is represented by the first amplification gain, and the second amplification gain matched with the distance is generated, so that the generated output radio frequency signal is matched with the distance, the problem that the output radio frequency signal determined by the fixed gain is too large or too small and exceeds the communication distance of the external communication device is solved, and the applicability of the output radio frequency signal is improved.
Optionally, before combining the return parameter with the clock signal of the carrier signal to generate the output radio frequency signal, the method further includes: transmitting the analysis instruction to a safety module, carrying out safety verification on the analysis instruction, and receiving feedback information of the safety module; if the feedback information is verified successfully, merging the return parameters and the clock signal of the carrier signal; and if the feedback information is failed to verify, discarding the parameters.
In the embodiment, the safety of communication between the radio frequency front-end chip and the external equipment is improved through the safety verification of the analysis instruction.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (16)
1. An SOC chip comprising a non-connected module co-processor and a non-connected communication module, wherein,
the non-connection communication module is electrically connected with the non-connection module coprocessor and comprises a primary awakening module and a clock data recovery module;
the primary awakening module is electrically connected with the non-connection module coprocessor and is used for detecting the field intensity of a radio frequency field where the SOC chip is located and sending a first awakening instruction to the non-connection module coprocessor when the field intensity is detected to be larger than a preset value;
the non-connection module coprocessor is electrically connected with the clock data recovery module and used for sending the first wake-up instruction to the clock data recovery module;
the clock data recovery module is used for entering a working state according to the first wake-up instruction, extracting a clock signal of an input radio frequency signal and sending a wake-up indication signal to the non-connection module coprocessor according to the clock signal;
the non-connected module coprocessor is further used for determining whether to wake up the SOC chip according to the wake-up indication signal.
2. The SOC chip of claim 1, wherein the preliminary wake-up module includes a field strength snooping circuit and a power management unit; wherein,
the field intensity detection circuit is electrically connected with the power supply management unit and is used for detecting the field intensity of the input radio-frequency signal and sending a first starting instruction to the power supply management unit when detecting that the field intensity of the input radio-frequency signal is greater than a preset value;
and the power management unit is electrically connected with the non-connection module coprocessor, and a user enters a working state according to the first starting instruction and sends a first awakening instruction to the non-connection module coprocessor.
3. The SOC chip of claim 1, wherein the clock data recovery module is specifically configured to:
acquiring frequency information and amplitude information of the clock signal, and determining whether the frequency information meets a first preset condition and whether the amplitude information meets a second preset condition;
if yes, generating a second wake-up signal, and if not, generating a cancel wake-up signal;
correspondingly, the non-interface module coprocessor is specifically configured to:
awakening the SOC chip according to the second awakening signal and processing the input radio frequency signal; or the like, or, alternatively,
and powering off the SOC according to the wake-up canceling signal.
4. The SOC chip of claim 1, wherein the SOC chip further comprises a CPU core, the off-chip communication module further comprises a variable gain amplifier, an indication circuit, and an analog demodulator; wherein,
the variable gain amplifier is used for amplifying an input radio frequency signal according to the current gain in an awakening state and outputting a carrier signal;
the indicating circuit is respectively electrically connected with the variable gain amplifier and the non-connection module coprocessor and is used for extracting a first voltage of the carrier signal, generating an indicating signal according to the first voltage and an internal reference voltage and sending the indicating signal to the non-connection module coprocessor;
the analog demodulator is electrically connected with the variable gain amplifier and the non-connection module coprocessor and is used for analyzing the carrier signal and sending a generated analysis instruction to the non-connection module coprocessor;
the non-connection module coprocessor is electrically connected with the CPU kernel based on an APB bus and an AHB bus, and is also used for sending the indication signal and the analysis instruction to the CPU kernel, wherein the APB bus and the AHB bus are connected through an AHB to APB bus bridge;
the CPU kernel is used for generating a gain adjusting signal according to the indicating signal, sending the gain adjusting signal to the non-connection module coprocessor, and generating a return parameter according to a corresponding analysis instruction when the indicating signal meets a preset condition;
the non-connection module coprocessor is electrically connected with the variable gain amplifier and is also used for sending the gain adjusting signal to the variable gain amplifier so that the variable gain amplifier adjusts the current gain and amplifies the input radio frequency signal according to the adjusted first amplification gain.
5. The SOC chip of claim 4, wherein the non-communicating module further comprises: a data synchronization module and an amplifier; wherein,
the CPU inner core is also used for generating a state control signal according to the indication signal and sending the state control signal to a clock data recovery module based on the non-connection module coprocessor;
the clock data recovery module is electrically connected with the variable gain amplifier, and is used for receiving the state control signal, switching a working state according to the state control signal, extracting a clock signal of the carrier signal in an enabling state, sending the clock signal to the non-connection module coprocessor, and generating an amplifier control signal which is homologous with the clock signal, wherein the working state comprises an enabling state and a suspending state;
the non-interface module coprocessor is also used for generating return data according to the clock signal and the return parameters;
the data synchronization module is respectively electrically connected with the clock data recovery module and the non-connection module coprocessor and is used for synchronizing the clock signal and the return data to generate a modulation signal;
the amplifier is respectively and electrically connected with the clock data recovery module and the data synchronization module, and is used for amplifying the modulation signal to generate an output radio frequency signal and dissipating energy after the output radio frequency signal is output according to the amplifier control signal.
6. The SOC chip according to claim 5, wherein the CPU core is further configured to, when the indication signal satisfies a preset condition, obtain a first amplification gain of the variable gain amplifier, determine a second amplification gain according to the first amplification gain, and send the second amplification gain to the non-interface module co-processor, wherein the second amplification gain is matched with the first amplification gain;
the non-connection module coprocessor is electrically connected with the amplifier and is further used for sending the second amplification gain to the amplifier so that the amplifier can amplify the signal of the modulation signal according to the second amplification gain.
7. The SOC chip of claim 5, further comprising a security module electrically connected to the APB bus, the security module configured to receive a parsing command sent by the non-connected module coprocessor based on the APB bus, perform security verification on the parsing command, generate verification information, and send the verification information to the non-connected module coprocessor based on the APB bus;
the non-connection module coprocessor is further configured to combine the return parameter with the clock signal of the carrier signal to generate return data when verification information is successful, and discard the return parameter when verification information is failed.
8. The SOC chip of claim 4, further comprising a global clock management module electrically connected to the AHB bus, configured to generate a modulated clock signal according to a reference clock signal and a configuration file sent by the CPU core, and adjust a clock frequency of the APB bus and an operating state of a peripheral electrically connected to the APB bus according to the modulated clock signal, wherein the configuration file includes operating clock information of the APB bus and the peripheral.
9. The SOC chip of any of claims 4-8, wherein the CPU core is an 16/32bit mixed instruction CPU core.
10. A method of radio frequency signal processing, comprising:
acquiring an input radio frequency signal and acquiring the signal intensity of the input radio frequency signal;
if the signal intensity is detected to be larger than a preset value, generating a first awakening instruction, and powering on the SOC chip according to the first awakening instruction;
extracting a clock signal of the input radio frequency signal, judging whether the clock signal is in a stable state according to a preset rule, generating a wakeup indication instruction according to a judgment result, and determining whether to wakeup the SOC chip according to the wakeup indication instruction.
11. The method of claim 10, wherein the extracting a clock signal of the input rf signal, determining whether the clock signal is in a stable state according to a preset rule, generating a wake-up instruction according to a determination result, and determining whether to wake up the SOC chip according to the wake-up instruction comprises:
acquiring frequency information and amplitude information of the clock signal, and determining whether the frequency information meets a first preset condition and whether the amplitude information meets a second preset condition;
if so, generating a second wake-up signal, waking up the SOC chip according to the second wake-up signal, and processing the input radio frequency signal;
and if not, generating a cancel awakening signal, and powering down the SOC chip according to the cancel awakening signal.
12. The method of claim 11, wherein processing the input radio frequency signal comprises:
acquiring an input radio frequency signal and determining a first amplification gain of the input radio frequency signal;
performing signal amplification on the input radio frequency signal according to the amplification gain to generate a carrier signal;
extracting an analysis instruction carried by the carrier signal, and generating a return parameter according to the analysis instruction;
and combining the return parameters with the clock signal of the carrier signal to generate an output radio frequency signal.
13. The method of claim 12, wherein obtaining an input radio frequency signal and determining a first amplification gain for the input radio frequency signal comprises:
performing signal amplification on the input radio frequency signal according to the current gain to generate a carrier signal;
extracting a first voltage of the carrier signal, comparing the first voltage with an internal reference voltage, and determining an indication signal according to a comparison result;
and generating a gain adjusting signal according to the indicating signal, adjusting the current gain according to the gain adjusting signal, and determining the first amplification gain.
14. The method of claim 12, wherein combining the return parameter with a clock signal of the carrier signal to generate an output radio frequency signal comprises:
merging the return parameters with the clock signals of the carrier signals to generate return data;
synchronizing the return data with a clock signal of the carrier signal to generate a modulation signal;
and amplifying the modulation signal to generate and output a radio frequency signal.
15. The method of claim 14, further comprising, prior to signal amplifying the modulated signal:
determining a second amplification gain according to the first amplification gain, wherein the second amplification gain is matched with the first amplification gain;
and amplifying the modulation signal according to the second amplification gain.
16. The method of claim 12, wherein prior to combining the return parameter with the clock signal of the carrier signal to generate the output radio frequency signal, further comprising:
transmitting the analysis instruction to a safety module, carrying out safety verification on the analysis instruction, and receiving feedback information of the safety module;
if the feedback information is verified successfully, combining the return parameter with the clock signal of the carrier signal;
and if the feedback information is failed to verify, discarding the parameter.
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| CN117094340A (en) * | 2023-10-17 | 2023-11-21 | 中诚华隆计算机技术有限公司 | Method for improving NFC recognition efficiency of SOC chip |
| CN117094340B (en) * | 2023-10-17 | 2023-12-15 | 中诚华隆计算机技术有限公司 | Method for improving NFC recognition efficiency of SOC chip |
| CN117119568A (en) * | 2023-10-25 | 2023-11-24 | 中诚华隆计算机技术有限公司 | Method for reducing unnecessary wake-up NFC recognition process of SOC chip |
| CN117114025A (en) * | 2023-10-25 | 2023-11-24 | 中诚华隆计算机技术有限公司 | Method for reducing energy consumption of SOC (system on chip) |
| CN117119568B (en) * | 2023-10-25 | 2023-12-29 | 中诚华隆计算机技术有限公司 | Method for reducing unnecessary wake-up NFC recognition process of SOC chip |
| CN117114025B (en) * | 2023-10-25 | 2023-12-29 | 中诚华隆计算机技术有限公司 | Method for reducing energy consumption of SOC (system on chip) |
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