CN107918314B - DSP implementation method and system of direct current frequency limiter control model - Google Patents
DSP implementation method and system of direct current frequency limiter control model Download PDFInfo
- Publication number
- CN107918314B CN107918314B CN201711068063.0A CN201711068063A CN107918314B CN 107918314 B CN107918314 B CN 107918314B CN 201711068063 A CN201711068063 A CN 201711068063A CN 107918314 B CN107918314 B CN 107918314B
- Authority
- CN
- China
- Prior art keywords
- direct current
- frequency difference
- frequency
- limiter
- dead zone
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Feedback Control In General (AREA)
- Inverter Devices (AREA)
Abstract
The invention discloses a DSP realization method and a system of a direct current frequency limiter control model, wherein the method comprises the following steps: acquiring a frequency difference of a converter station; judging whether the frequency difference of the converter station exceeds the dead zone of the direct current frequency limiter, if so, delaying the first preset time, starting the direct current frequency limiter, obtaining the direct current power regulating quantity through proportional-integral control for regulation, and delaying the second preset time when the frequency difference of the converter station is recovered to the dead zone of the direct current frequency limiter, and then restoring the direct current power to the planned value; otherwise, the frequency difference input is locked. According to the invention, the delay resetting type direct current frequency limiter control model is constructed through the cooperation of the dead zone of the direct current frequency limiter, the first preset time and the second preset time, so that the dynamic simulation of the system is closer to the actual system and is more objective and comprehensive, and meanwhile, the control model is optimized through the second preset time, so that the simulation performance is better. The method can be widely applied to the field of simulation optimization of the power system.
Description
Technical Field
The invention relates to the field of simulation optimization of power systems, in particular to a DSP (digital signal processor) implementation method and system of a direct-current frequency limiter control model.
Background
With the rapid increase of the direct current transmission scale in the power grid, the direct current power modulation plays an increasingly important role in improving the system stability. Taking the southern power grid as an example, after the Yunnan power grid is asynchronously networked with the main grid, the frequency stability replaces the transient stability to become the most main stability problem of the system, and the frequency fluctuation of the power grid is difficult to quickly stabilize only by adjusting a prime motor and a speed regulator. And the direct current has overload capacity, and the direct current Frequency Limiter (FLC) can rapidly change the direct current power, so that the method is an effective means for solving the problem of frequency stability.
A frequency limit controller (FLC, referred to as a dc frequency limiter for short) plays an important role in an asynchronous networking system as an important dc active power modulation means. The existing power system simulation tool, such as the DSP simulation software BPA, only provides a control block diagram of the FLC, as shown in fig. 1. In fig. 1, Dfmax and Dfmin are respectively the maximum and minimum values of the frequency difference, Tf is the filter time constant, Fband is the frequency difference dead zone limiting range, KP is the proportional gain, KI is the integral gain, and Pmodmin and Pmodmax are the lower and upper limits of the dc power adjustment.
In fact, in the high voltage direct current transmission line currently operated in the power grid (such as the south power grid), the FLC mainly has two control models: one is to make the FLC to be restored by frequency difference in the reverse direction (i.e. the FLC of the reverse frequency difference restoration type), which is provided by siemens, as shown in fig. 1, this type of FLC can be simulated in BPA by a direct current system frequency limitation model represented by the DS-7 card; another method is to use a delay-on integral negative feedback link to enable FLC to be reset (i.e. delay-reset FLC), which is provided by ABB corporation, as shown in fig. 2, this type of FLC has no corresponding card in BPA and can be used for time domain simulation.
Although the two types of FLCs both adopt proportional-integral control and have a dead zone setting function, the specific control processes of the two FLCs have a large difference, including whether there is a difference in control delay and a difference in output quantity resetting principle. Therefore, the two types of frequency limiters have a difference which cannot be ignored on the frequency modulation effect of the system, particularly on the influence of large disturbance such as direct current single-pole blocking, cutting and the like on the dynamic process of the frequency. The existing power system simulation tool only provides a simulation model for the reverse frequency difference resetting FLC, but does not provide a corresponding simulation model for the delay resetting DC frequency limiter, so that the simulation tool is not objective and comprehensive, and the simulation performance needs to be further improved to meet the requirements of an actual system.
Disclosure of Invention
To solve the above technical problems, the present invention aims to: the DSP implementation method and the DSP implementation system of the DC frequency limiter control model are objective, comprehensive and good in simulation performance.
The first technical scheme adopted by the invention is as follows:
a DSP implementation method of a direct current frequency limiter control model comprises the following steps:
acquiring a frequency difference of a converter station;
judging whether the frequency difference of the converter station exceeds the dead zone of the direct current frequency limiter, if so, delaying the first preset time, starting the direct current frequency limiter, obtaining the direct current power regulating quantity through proportional-integral control for regulation, and delaying the second preset time when the frequency difference of the converter station is recovered to the dead zone of the direct current frequency limiter, and then restoring the direct current power to the planned value; otherwise, the frequency difference input is locked.
Further, the step of acquiring the frequency difference of the converter station specifically includes:
and extracting the frequency difference of the converter station and filtering the frequency difference through a filtering link to obtain a filtered frequency difference signal.
Further, whether the frequency difference of the converter station exceeds the dead zone of the direct current frequency limiter is judged, if yes, the direct current frequency limiter is started after delaying for a first preset time, the direct current power regulating quantity is obtained through proportional-integral control to carry out regulation, and when the frequency difference of the converter station is recovered to the dead zone of the direct current frequency limiter, the direct current power is restored to a planned value after delaying for a second preset time; otherwise, the step of locking the frequency difference input specifically includes:
judging whether the frequency difference of the converter station exceeds the dead zone of the direct-current frequency limiter, if so, executing the next step, otherwise, locking the frequency difference input;
starting a direct current frequency limiter after delaying the first preset time, conducting a proportional integral link, obtaining a direct current power regulating quantity through the proportional integral link, and further carrying out corresponding regulation according to the direct current power regulating quantity;
judging whether the frequency difference of the converter station is restored within the dead zone of the direct current frequency limiter, if so, delaying the second preset time and then switching on a negative feedback regulation link, and enabling the direct current power to be restored to a planned value through the negative feedback regulation link; otherwise, returning to the previous step.
Further, the first preset time is 100ms, and the second preset time is 60 s.
Furthermore, the frequency difference value interval of the dead zone of the direct current frequency limiter is [ -0.14Hz,0.14Hz ].
Further, the step of judging whether the frequency difference of the converter station exceeds the dead zone of the direct current frequency limiter, if so, executing the next step, otherwise, locking the frequency difference input is specifically as follows:
judging whether the frequency difference of the converter station exceeds the dead zone of the direct-current frequency limiter or not by adopting preset three-layer judgment logic, if so, enabling a frequency difference signal which exceeds the dead zone of the direct-current frequency limiter and meets a preset conduction condition to be conducted to a proportional integral link, otherwise, locking the frequency difference input, wherein the preset three-layer judgment logic comprises a first judgment logic, a second judgment logic and a third judgment logic, a first logic value corresponding to the first judgment logic is 1 when the frequency difference signal which exceeds the dead zone of the direct-current frequency limiter exceeds 0.001Hz, otherwise, the first judgment logic is 0, and the first judgment logic starts a timing module to time when the first logic value is 1 and resets the timing module when the first logic value is 0; a second logic value corresponding to the second judgment logic is 1 when the timing module times for more than 100ms, otherwise, the second logic value is 0; a third logic value corresponding to the third judgment logic is 1 when a differentiated signal is less than 0, otherwise, the differentiated signal is 0, and the differentiated signal is obtained by a frequency difference signal exceeding a dead zone of the direct current frequency limiter through a differentiation link;
the predetermined on condition is that the second logic value is 1, or the first logic value is 0 and the third logic value is 1.
Further, whether the frequency difference of the converter station is restored to be within the dead zone of the direct current frequency limiter is judged, if yes, a negative feedback adjusting link is conducted after a second preset time is delayed, and the direct current power is restored to a planned value through the negative feedback adjusting link; otherwise, returning to the step of the previous step, specifically:
judging whether the frequency difference of the converter station is recovered to be within the dead zone of the direct current frequency limiter [ -0.14Hz,0.14Hz ], if so, delaying the second preset time and then switching on a negative feedback regulation link, and gradually resetting the direct current power to a planned value through the negative feedback regulation link; otherwise, returning to the previous step.
The second technical scheme adopted by the invention is as follows:
a DSP implementation system of a direct current frequency limiter control model comprises the following modules:
the frequency difference acquisition module is used for acquiring the frequency difference of the converter station;
the time delay resetting adjusting module is used for judging whether the frequency difference of the converter station exceeds the dead zone of the direct current frequency limiter, if so, the direct current frequency limiter is started after delaying for first preset time, the direct current power adjusting quantity is obtained through proportional-integral control to adjust, and when the frequency difference of the converter station is recovered to the dead zone of the direct current frequency limiter, the direct current power is reset to a planned value after delaying for second preset time; otherwise, the frequency difference input is locked.
Further, the delay resetting adjusting module comprises:
the first judging unit is used for judging whether the frequency difference of the converter station exceeds the dead zone of the direct-current frequency limiter, if so, the converter station is switched to the delay adjusting unit, otherwise, the frequency difference input is locked;
the delay adjusting unit is used for starting the direct current frequency limiter after delaying the first preset time, conducting a proportional-integral link, obtaining a direct current power adjusting quantity through the proportional-integral link, and further carrying out corresponding adjustment according to the direct current power adjusting quantity;
the second judgment unit is used for judging whether the frequency difference of the converter station is restored to be within the dead zone of the direct-current frequency limiter, if so, the negative feedback regulation link is conducted after delaying for a second preset time, and the direct-current power is restored to a planned value through the negative feedback regulation link; otherwise, returning to the delay adjusting unit.
The third technical scheme adopted by the invention is as follows:
a DSP implementation system for a dc frequency limiter control model, comprising:
a memory for storing a program;
the processor is configured to load the program to execute the DSP implementation method of the dc frequency limiter control model according to the first technical solution.
The invention has the beneficial effects that: the invention relates to a DSP (digital signal processor) implementation method and a DSP implementation system of a DC frequency limiter control model, which utilize the modeling function of a user-defined DC power transmission control system of a DSP power system simulation software, construct the delay resetting type DC frequency limiter control model by the cooperation of a DC frequency limiter dead zone, first preset time and second preset time, fill the blank of the existing power system simulation tool on the delay resetting type DC frequency controller model, ensure that the dynamic simulation of the system is closer to the actual system and is more objective and comprehensive, and optimize the delay resetting type DC frequency limiter control model by the second preset time, and have better simulation performance.
Drawings
FIG. 1 is a control block diagram of a reverse frequency difference reset type DC frequency limiter of a prior art DSP simulation software;
FIG. 2 is a control block diagram of a delayed reset DC frequency limiter;
FIG. 3 is a general flow chart of a DSP implementation method of a DC frequency limiter control model according to the present invention;
FIG. 4 is a flowchart of an implementation of embodiment 1 of the present invention;
fig. 5 is a control block diagram of the delay-resetting dc frequency limiter according to embodiment 1 of the present invention.
Detailed Description
Referring to fig. 3, the DSP implementation method of a dc frequency limiter control model of the present invention includes the following steps:
acquiring a frequency difference of a converter station;
judging whether the frequency difference of the converter station exceeds the dead zone of the direct current frequency limiter, if so, delaying the first preset time, starting the direct current frequency limiter, obtaining the direct current power regulating quantity through proportional-integral control for regulation, and delaying the second preset time when the frequency difference of the converter station is recovered to the dead zone of the direct current frequency limiter, and then restoring the direct current power to the planned value; otherwise, the frequency difference input is locked.
The converter station frequency difference can be obtained by extracting corresponding frequency difference extraction instructions in a user-defined direct-current power transmission control system modeling function of DSP power system simulation software. The proportional-integral control is realized by a proportional-integral link of the delay resetting type direct current frequency limiter. The direct current power is restored to the planned value, and the process can be realized through a negative feedback link of the delay restoration type direct current frequency limiter.
The invention utilizes the modeling function of the user-defined direct-current power transmission control system of the DSP power system simulation software, constructs the delay resetting type direct-current frequency limiter control model through the cooperation of the dead zone of the direct-current frequency limiter, the first preset time and the second preset time, fills the blank of the existing power system simulation tool for the delay resetting type direct-current frequency limiter model, ensures that the dynamic simulation of the system is closer to the actual system and is more objective and comprehensive, optimizes the delay resetting type direct-current frequency limiter control model through the second preset time, has better simulation performance, and is beneficial to improving the simulation precision of the dynamic process of the power system under the large disturbance of asynchronous networking.
Further as a preferred embodiment, the step of obtaining the frequency difference of the converter station specifically includes:
and extracting the frequency difference of the converter station and filtering the frequency difference through a filtering link to obtain a filtered frequency difference signal.
Further, as a preferred embodiment, the determining unit determines whether the frequency difference of the converter station exceeds a dead zone of the dc frequency limiter, if so, delays for a first preset time, starts the dc frequency limiter, obtains a dc power adjustment value through proportional-integral control for adjustment, and delays for a second preset time, and then returns the dc power to a planned value; otherwise, the step of locking the frequency difference input specifically includes:
judging whether the frequency difference of the converter station exceeds the dead zone of the direct-current frequency limiter, if so, executing the next step, otherwise, locking the frequency difference input;
starting a direct current frequency limiter after delaying the first preset time, conducting a proportional integral link, obtaining a direct current power regulating quantity through the proportional integral link, and further carrying out corresponding regulation according to the direct current power regulating quantity;
judging whether the frequency difference of the converter station is restored within the dead zone of the direct current frequency limiter, if so, delaying the second preset time and then switching on a negative feedback regulation link, and enabling the direct current power to be restored to a planned value through the negative feedback regulation link; otherwise, returning to the previous step.
In a further preferred embodiment, the first preset time is 100ms, and the second preset time is 60 s.
Further, as a preferred embodiment, the frequency difference value interval of the dead zone of the dc frequency limiter is [ -0.14Hz,0.14Hz ].
The dead zone exceeding the direct current frequency limiter means that the frequency difference of the converter station is less than-0.14 Hz or the frequency difference of the converter station is more than 0.14 Hz; the dead zone of the direct current frequency limiter means that the frequency difference of the converter station is more than or equal to-0.14 Hz and less than or equal to 0.14 Hz.
Further as a preferred embodiment, the step of judging whether the frequency difference of the converter station exceeds the dead zone of the dc frequency limiter, if so, executing the next step, otherwise, locking the frequency difference input is specifically:
judging whether the frequency difference of the converter station exceeds the dead zone of the direct-current frequency limiter or not by adopting preset three-layer judgment logic, if so, enabling a frequency difference signal which exceeds the dead zone of the direct-current frequency limiter and meets a preset conduction condition to be conducted to a proportional integral link, otherwise, locking the frequency difference input, wherein the preset three-layer judgment logic comprises a first judgment logic, a second judgment logic and a third judgment logic, a first logic value corresponding to the first judgment logic is 1 when the frequency difference signal which exceeds the dead zone of the direct-current frequency limiter exceeds 0.001Hz, otherwise, the first judgment logic is 0, and the first judgment logic starts a timing module to time when the first logic value is 1 and resets the timing module when the first logic value is 0; a second logic value corresponding to the second judgment logic is 1 when the timing module times for more than 100ms, otherwise, the second logic value is 0; a third logic value corresponding to the third judgment logic is 1 when a differentiated signal is less than 0, otherwise, the differentiated signal is 0, and the differentiated signal is obtained by a frequency difference signal exceeding a dead zone of the direct current frequency limiter through a differentiation link;
the predetermined on condition is that the second logic value is 1, or the first logic value is 0 and the third logic value is 1.
In order to judge whether the frequency difference of the converter station exceeds the dead zone of the direct current frequency limiter, the invention introduces a preset three-layer judgment logic and a preset conduction condition, and when the frequency exceeds the dead zone by 0.001Hz and lasts for 100ms or the frequency is in a recovery state, the frequency difference signal exceeding the dead zone of the direct current frequency limiter and meeting the preset conduction condition is transmitted to a proportional integral link. In the preset three-layer judgment logic, the judgment of the logic value is true when the logic value is 1, and the judgment of the logic value is false when the logic value is 0. The first layer of judgment logic is mainly used for judging whether the frequency exceeds the dead zone by 0.001 Hz. The second decision logic is mainly used to decide whether the delay has exceeded 100 ms. The third judging logic is used for judging whether the frequency is in a recovery state, if so, the frequency is judged to be in a positive direction, and the third judging logic value is true.
According to the third judgment logic, when the frequency difference signal exceeding the dead zone of the direct current frequency limiter is recovered to the state that the frequency difference signal exceeds the dead zone by 0.001Hz and does not exceed the dead zone by 0.001Hz, the signal conducted to the proportional integral link cannot be stepped to 0, the phenomenon of small-amplitude power oscillation caused by step change of direct current power after the proportional integral link is avoided, and the method is more reliable.
Further as a preferred embodiment, the method includes judging whether the frequency difference of the converter station is restored within a dead zone of the direct current frequency limiter, if so, delaying for a second preset time, turning on a negative feedback adjusting link, and returning the direct current power to a planned value through the negative feedback adjusting link; otherwise, returning to the step of the previous step, specifically:
judging whether the frequency difference of the converter station is recovered to be within the dead zone of the direct current frequency limiter [ -0.14Hz,0.14Hz ], if so, delaying the second preset time and then switching on a negative feedback regulation link, and gradually resetting the direct current power to a planned value through the negative feedback regulation link; otherwise, returning to the previous step.
Corresponding to the method of fig. 3, the DSP implementation system of a dc frequency limiter control model of the present invention includes the following modules:
the frequency difference acquisition module is used for acquiring the frequency difference of the converter station;
the time delay resetting adjusting module is used for judging whether the frequency difference of the converter station exceeds the dead zone of the direct current frequency limiter, if so, the direct current frequency limiter is started after delaying for first preset time, the direct current power adjusting quantity is obtained through proportional-integral control to adjust, and when the frequency difference of the converter station is recovered to the dead zone of the direct current frequency limiter, the direct current power is reset to a planned value after delaying for second preset time; otherwise, the frequency difference input is locked.
Further, the delay resetting adjusting module comprises:
the first judging unit is used for judging whether the frequency difference of the converter station exceeds the dead zone of the direct-current frequency limiter, if so, the converter station is switched to the delay adjusting unit, otherwise, the frequency difference input is locked;
the delay adjusting unit is used for starting the direct current frequency limiter after delaying the first preset time, conducting a proportional-integral link, obtaining a direct current power adjusting quantity through the proportional-integral link, and further carrying out corresponding adjustment according to the direct current power adjusting quantity;
the second judgment unit is used for judging whether the frequency difference of the converter station is restored to be within the dead zone of the direct-current frequency limiter, if so, the negative feedback regulation link is conducted after delaying for a second preset time, and the direct-current power is restored to a planned value through the negative feedback regulation link; otherwise, returning to the delay adjusting unit.
Corresponding to the method of fig. 3, the present invention provides a DSP implementation system of a dc frequency limiter control model, which includes:
a memory for storing a program;
and the processor is used for loading the program to execute the DSP implementation method of the direct current frequency limiter control model.
The invention will be further explained and explained with reference to the drawings and the embodiments in the description.
Example 1
As shown in fig. 4 and 5, this embodiment proposes a DSP implementation scheme of a delay-resetting dc frequency limiter control model for the deficiency of the existing simulation model. According to the scheme, the modeling function of the user-defined direct-current power transmission control system of the DSP power system simulation software is utilized, a delay resetting type direct-current frequency limiter model is established, the blank of the existing simulation tool for the delay resetting type direct-current frequency limiter model is made up, and the model is optimized, so that the model has better simulation performance.
As shown in fig. 4 and 5, taking a south power grid as an example (the first preset time is 100ms, and the second preset time is 60s), the DSP software implementation method of the delay-resetting type dc frequency limiter control model in this embodiment specifically includes the steps of:
s1, acquiring the frequency difference of the converter station;
s2, judging whether the frequency difference of the converter station exceeds the dead zone of the direct current frequency limiter, if so, executing a step S3, otherwise, locking the frequency difference input;
s3, delaying for 100ms to start a direct current Frequency Limiter (FLC), conducting a proportional integral link (PI), and obtaining a direct current power regulating variable through the PI;
and S4, judging whether the frequency difference of the converter station is recovered to a dead zone, if so, delaying for 60S to conduct a negative feedback link, and gradually returning the direct current power to a planned value.
The step S1 specifically includes:
and extracting the frequency difference of the converter station and obtaining a filtered frequency difference signal (i) through a filtering link, as shown in fig. 5.
The dead zone (the dead zone for short) of the direct current frequency limiter means that the frequency difference of the converter station is within a dead zone value range of [ -0.14Hz,0.14Hz ].
If the frequency difference of the converter station is less than-0.14 Hz or more than 0.14Hz, it indicates that the frequency difference of the converter station exceeds the dead zone of the dc frequency limiter, and at this time, as described in step S3, the dc FLC is started after delaying 100ms, so that the signal ② after the dead zone is conducted to the input signal ⑥ of the proportional-integral link, and finally the signal of the dc power adjustment amount is obtained through the proportional-integral link (PI link)
As shown in fig. 5.
If the frequency difference of the converter station is not less than-0.14 Hz and not more than 0.14Hz, it indicates that the frequency difference of the converter station is recovered to the dead zone of the dc frequency limiter, and at this time, as shown in step S4, the negative feedback link is turned on by delaying 60S, that is, the signal r is selected by delaying 60S, so that the dc power is gradually recovered to the planned value, as shown in fig. 5.
In the steps S2 and S3, the following preset three-layer judgment logic may be adopted to realize this judgment step:
a: when the signal (II) exceeds the dead zone of 0.001Hz, the corresponding first judgment logic value EX1 is 1 (namely, the judgment is true), the timing module TIMER is started to start timing, and when the first judgment logic value EX1 is 0 (namely, the judgment is false), the timing module TIMER is reset.
B: and a second judgment logic, when the module TIMER counts for more than 100ms, the corresponding second judgment logic value EX2 is 1 (i.e. determined as true), otherwise, the value is 0 (i.e. determined as false).
C: and in the third judgment logic, the absolute value of the signal III is subjected to a differentiation link to obtain a differentiated signal III, when the signal III is less than 0, the frequency is judged to be in a recovery state, and the corresponding third judgment logic value EX3 is 1 (namely, the judgment is true).
D: when the logic value EX2 is 1, or the logic value EX1 is 0 and EX3 is 1, FLC is activated to transmit a signal ±, otherwise a signal with a constant value equal to 0 is input to the signal | (i.e., frequency difference input is locked), as shown in fig. 5.
The whole predetermined judgment logic is realized by: when the frequency exceeds 0.001Hz and lasts for 100ms or the frequency is in a recovery state, the signal is transmitted to a signal (c). The logic value EX3 has the function of judging whether the frequency is in a recovery state, if so, the frequency is in a positive direction, and the logic value EX3 is 1, so that when the signal (II) is recovered to a state that the dead zone is exceeded and the dead zone is not exceeded, the signal (II) cannot be stepped to 0, and the phenomenon of small power oscillation caused by the step change of direct current power after a proportional integral link is avoided.
As shown in FIG. 5, signal ⑥ goes through proportional element Kp to obtain signal ⑦, signal ⑥ goes through integrating element Ki to obtain signal ⑧, signal ⑩ is the difference between negative feedback signal ⑨ and signal ⑧, and signal ⑩ goes through delay integrating element to obtain signal ⑩
Signal
Obtaining signals after amplitude limiting
Signal
Is the signal ⑦ and the signal
And the sum is the FLC response action quantity which is finally obtained and is superposed on the original power reference value to change the direct current power.
In step S4, it is determined whether the frequency difference of the converter station is recovered to the dead zone, that is, it is determined whether the signal (ii) is equal to 0: if yes, delay 60s turns on negative feedback link, i.e. delay 60s selects signal (r) to gradually restore dc power to the planned value. The specific implementation process of the step S4 determination link includes:
1) when the signal (II) exceeds the dead zone of 0.001Hz, the logic value EX5 is 1 (namely, the judgment is true); when the logic value EX5 is 1, the module TIMER is used for clocking, and when the logic value EX5 is 0, the module TIMER is reset.
2) When module TIMER counts for more than 60s, the logic value EX6 is 1 (i.e., determined to be true). When in useLogic value EX6 is 1
Transmitted to signal ⑨, otherwise signal ⑨ takes the constant value signal 0.
The part of judgment logic is mainly to start a negative feedback link after delaying for 60s after meeting the frequency difference requirement.
Based on the above theoretical basis, the core code and corresponding explanation of the present embodiment are as follows:
the invention provides a method and a system for realizing a DSP (digital signal processor) of a control model of a delay resetting type direct current frequency limiter, aiming at the defect of a delay negative feedback type direct current frequency controller model of the existing DSP simulation tool of a power system. According to the method and the system, the modeling function of the user-defined direct-current power transmission control system of the DSP power system simulation software is utilized, the delay resetting type direct-current frequency limiter control model is established, the blank of the existing simulation tool for the delay resetting type direct-current frequency limiter model is filled, and the delay resetting type direct-current frequency limiter control model is optimized, so that the delay resetting type direct-current frequency limiter control model has better simulation performance. The method is beneficial to improving the simulation precision of the dynamic process of the power system under the large disturbance of the asynchronous networking.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A DSP implementation method of a direct current frequency limiter control model is characterized by comprising the following steps: the method comprises the following steps:
acquiring a frequency difference of a converter station;
judging whether the frequency difference of the converter station exceeds the dead zone of the direct current frequency limiter, if so, delaying the first preset time, starting the direct current frequency limiter, obtaining the direct current power regulating quantity through proportional-integral control for regulation, and delaying the second preset time when the frequency difference of the converter station is recovered to the dead zone of the direct current frequency limiter, and then restoring the direct current power to the planned value; otherwise, locking the frequency difference input;
judging whether the frequency difference of the converter station exceeds the dead zone of the direct current frequency limiter, if so, delaying the first preset time, starting the direct current frequency limiter, obtaining the direct current power regulating quantity through proportional-integral control for regulation, and delaying the second preset time when the frequency difference of the converter station is recovered to the dead zone of the direct current frequency limiter, and then restoring the direct current power to the planned value; otherwise, the step of locking the frequency difference input specifically includes:
judging whether the frequency difference of the converter station exceeds the dead zone of the direct-current frequency limiter, if so, executing the next step, otherwise, locking the frequency difference input;
starting a direct current frequency limiter after delaying the first preset time, conducting a proportional integral link, obtaining a direct current power regulating quantity through the proportional integral link, and further carrying out corresponding regulation according to the direct current power regulating quantity;
judging whether the frequency difference of the converter station is restored within the dead zone of the direct current frequency limiter, if so, delaying the second preset time and then switching on a negative feedback regulation link, and enabling the direct current power to be restored to a planned value through the negative feedback regulation link; otherwise, returning to the previous step.
2. The DSP implementing method of the dc frequency limiter control model according to claim 1, wherein: the step of acquiring the frequency difference of the converter station specifically comprises the following steps:
and extracting the frequency difference of the converter station and filtering the frequency difference through a filtering link to obtain a filtered frequency difference signal.
3. The DSP implementing method of the dc frequency limiter control model according to claim 1, wherein: the first preset time is 100ms, and the second preset time is 60 s.
4. The method according to claim 3, wherein the method comprises the following steps: the frequency difference value interval of the dead zone of the direct current frequency limiter is [ -0.14Hz,0.14Hz ].
5. The method for implementing the DSP of the DC frequency limiter control model according to claim 4, wherein the method comprises the following steps: the method comprises the following steps of judging whether the frequency difference of the converter station exceeds the dead zone of the direct-current frequency limiter, if so, executing the next step, otherwise, locking the frequency difference input, and specifically:
judging whether the frequency difference of the converter station exceeds the dead zone of the direct-current frequency limiter or not by adopting preset three-layer judgment logic, if so, enabling a frequency difference signal which exceeds the dead zone of the direct-current frequency limiter and meets a preset conduction condition to be conducted to a proportional integral link, otherwise, locking the frequency difference input, wherein the preset three-layer judgment logic comprises a first judgment logic, a second judgment logic and a third judgment logic, a first logic value corresponding to the first judgment logic is 1 when the frequency difference signal which exceeds the dead zone of the direct-current frequency limiter exceeds 0.001Hz, otherwise, the first judgment logic is 0, and the first judgment logic starts a timing module to time when the first logic value is 1 and resets the timing module when the first logic value is 0; a second logic value corresponding to the second judgment logic is 1 when the timing module times for more than 100ms, otherwise, the second logic value is 0; a third logic value corresponding to the third judgment logic is 1 when a differentiated signal is less than 0, otherwise, the differentiated signal is 0, and the differentiated signal is obtained by a frequency difference signal exceeding a dead zone of the direct current frequency limiter through a differentiation link;
the predetermined on condition is that the second logic value is 1, or the first logic value is 0 and the third logic value is 1.
6. The DSP implementing method of the dc frequency limiter control model according to claim 1, wherein: judging whether the frequency difference of the converter station is restored within the dead zone of the direct current frequency limiter, if so, delaying the second preset time and then switching on a negative feedback adjusting link, and enabling the direct current power to be restored to a planned value through the negative feedback adjusting link; otherwise, returning to the step of the previous step, specifically:
judging whether the frequency difference of the converter station is recovered to be within the dead zone of the direct current frequency limiter [ -0.14Hz,0.14Hz ], if so, delaying the second preset time and then switching on a negative feedback regulation link, and gradually resetting the direct current power to a planned value through the negative feedback regulation link; otherwise, returning to the previous step.
7. The utility model provides a DSP implementation system of direct current frequency limiter control model which characterized in that: the system comprises the following modules:
the frequency difference acquisition module is used for acquiring the frequency difference of the converter station;
the time delay resetting adjusting module is used for judging whether the frequency difference of the converter station exceeds the dead zone of the direct current frequency limiter, if so, the direct current frequency limiter is started after delaying for first preset time, the direct current power adjusting quantity is obtained through proportional-integral control to adjust, and when the frequency difference of the converter station is recovered to the dead zone of the direct current frequency limiter, the direct current power is reset to a planned value after delaying for second preset time; otherwise, locking the frequency difference input;
the delay resetting adjusting module comprises:
the first judging unit is used for judging whether the frequency difference of the converter station exceeds the dead zone of the direct-current frequency limiter, if so, the converter station is switched to the delay adjusting unit, otherwise, the frequency difference input is locked;
the delay adjusting unit is used for starting the direct current frequency limiter after delaying the first preset time, conducting a proportional-integral link, obtaining a direct current power adjusting quantity through the proportional-integral link, and further carrying out corresponding adjustment according to the direct current power adjusting quantity;
the second judgment unit is used for judging whether the frequency difference of the converter station is restored to be within the dead zone of the direct-current frequency limiter, if so, the negative feedback regulation link is conducted after delaying for a second preset time, and the direct-current power is restored to a planned value through the negative feedback regulation link; otherwise, returning to the delay adjusting unit.
8. The utility model provides a DSP implementation system of direct current frequency limiter control model which characterized in that: the method comprises the following steps:
a memory for storing a program;
processor for loading said program to perform a DSP-implemented method of controlling a dc frequency limiter according to any one of claims 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711068063.0A CN107918314B (en) | 2017-11-03 | 2017-11-03 | DSP implementation method and system of direct current frequency limiter control model |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711068063.0A CN107918314B (en) | 2017-11-03 | 2017-11-03 | DSP implementation method and system of direct current frequency limiter control model |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107918314A CN107918314A (en) | 2018-04-17 |
| CN107918314B true CN107918314B (en) | 2020-08-11 |
Family
ID=61895224
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711068063.0A Active CN107918314B (en) | 2017-11-03 | 2017-11-03 | DSP implementation method and system of direct current frequency limiter control model |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107918314B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437809A (en) * | 2011-12-14 | 2012-05-02 | 国网电力科学研究院 | Method for controlling speed regulating system of hydroelectric unit in island mode |
| CN202522866U (en) * | 2012-03-20 | 2012-11-07 | 南方电网科学研究院有限责任公司 | Real-time simulation test platform used for electrical network stabilization control test research and development |
| CN103633638A (en) * | 2013-11-06 | 2014-03-12 | 南方电网科学研究院有限责任公司 | Frequency control strategy for multiple DC (Direct Current) send-out island power grid |
| CN106849145A (en) * | 2016-12-27 | 2017-06-13 | 中国电力科学研究院 | For control method and system that direct current frequency limiter and algorithm for power modulation are coordinated |
| CN107086590A (en) * | 2017-06-30 | 2017-08-22 | 南方电网科学研究院有限责任公司 | Control method for coordinating, device and the transmission system of mixed DC station control |
-
2017
- 2017-11-03 CN CN201711068063.0A patent/CN107918314B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437809A (en) * | 2011-12-14 | 2012-05-02 | 国网电力科学研究院 | Method for controlling speed regulating system of hydroelectric unit in island mode |
| CN202522866U (en) * | 2012-03-20 | 2012-11-07 | 南方电网科学研究院有限责任公司 | Real-time simulation test platform used for electrical network stabilization control test research and development |
| CN103633638A (en) * | 2013-11-06 | 2014-03-12 | 南方电网科学研究院有限责任公司 | Frequency control strategy for multiple DC (Direct Current) send-out island power grid |
| CN106849145A (en) * | 2016-12-27 | 2017-06-13 | 中国电力科学研究院 | For control method and system that direct current frequency limiter and algorithm for power modulation are coordinated |
| CN107086590A (en) * | 2017-06-30 | 2017-08-22 | 南方电网科学研究院有限责任公司 | Control method for coordinating, device and the transmission system of mixed DC station control |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107918314A (en) | 2018-04-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Fridman et al. | Robust H/sub/spl infin//filtering of linear systems with time-varying delay | |
| CN103391015B (en) | A kind of variable parameter PI regulator parameter method of adjustment | |
| CN106909073B (en) | A kind of parameter regulation means of digital governer | |
| CN109066814A (en) | The control method and system of energy storage device auxiliary fired power generating unit frequency modulation frequency modulation | |
| CN107918314B (en) | DSP implementation method and system of direct current frequency limiter control model | |
| CN102749843B (en) | Self-adaptive feedback protection dynamic surface controller structure and design method | |
| KR20230067689A (en) | Power stabilization output control device, method and system | |
| CN106329904A (en) | Soft start control method and device for voltage conversion circuit | |
| CN105138036A (en) | Temperature control method and apparatus for integrated circuit | |
| CN113835372A (en) | Control system and method for primary frequency modulation of auxiliary thermal power generating unit of electrode type electric boiler | |
| CN103457291A (en) | Intelligent power generation control and optimization method adopting multi-algorithm one-direction per-unit estimation | |
| CN109884889A (en) | A kind of dynamic Feedforward control method improving Thermal generation unit coordinated control system regulation quality | |
| CN106786484B (en) | Method and device for suppressing second harmonic current | |
| CN111864744A (en) | Online switching method and system for control modes of speed regulator of high-proportion hydroelectric system | |
| CN110617152A (en) | Throttle control system based on fuzzy PID control | |
| CN112769347B (en) | Time delay compensation control method for converter | |
| CN115095652A (en) | EMS control method for optimizing DCT model low transmission oil temperature starting comfort | |
| CN113098343B (en) | Method, device and system for controlling output power of generator and electronic equipment | |
| CN110994586B (en) | DC bus voltage oscillation suppression method | |
| US7092770B2 (en) | Feedback control method and feedback control device | |
| CN114123236A (en) | Frequency response control method and device for power electronic equipment | |
| RU2468406C1 (en) | Adaptive system for controlling astatic object with delay | |
| KR102132580B1 (en) | DC voltage coordinated control method | |
| CN111293927A (en) | Multi-motor synchronous drive control method, device and system | |
| CN111555608A (en) | Unknown input observer-based non-singular terminal sliding mode control method for buck type direct current converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |