CN107911605A - Pipeline system zero propagation extracts the logic circuit and extracting method of image sharpness information - Google Patents
Pipeline system zero propagation extracts the logic circuit and extracting method of image sharpness information Download PDFInfo
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- CN107911605A CN107911605A CN201711200081.XA CN201711200081A CN107911605A CN 107911605 A CN107911605 A CN 107911605A CN 201711200081 A CN201711200081 A CN 201711200081A CN 107911605 A CN107911605 A CN 107911605A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/60—Control of cameras or camera modules
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/60—Control of cameras or camera modules
- H04N23/67—Focus control based on electronic image sensor signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
- H04N5/20—Circuitry for controlling amplitude response
- H04N5/205—Circuitry for controlling amplitude response for correcting amplitude versus frequency characteristic
- H04N5/208—Circuitry for controlling amplitude response for correcting amplitude versus frequency characteristic for compensating for attenuation of high frequency components, e.g. crispening, aperture distortion correction
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Abstract
The present invention relates to the logic circuit and extracting method of a kind of pipeline system zero propagation extraction image sharpness information, using hardware realization platform of the field programmable gate array (FPGA) as image procossing, logic circuit is divided into：5 parts such as pixel coordinate resolution logic circuit, pixel value row buffering logic circuit, image sharpness computing flip-flop logic circuit, Pixel-level acutance arithmetic logic circuit, image level acutance accumulation logic circuit.Utilize the clock signal being superimposed on HD video source, the coordinated indexing value of real-time reconstruction image pixel, for follow-up triggering control logic；By multichannel buffer queue mode, view data is grouped again, pipelines follow-up processing.The beneficial effects of the invention are as follows：Airborne Electro-optical Detecting System is realized the acquisition of image sharpness information, and possess the precondition of automatic focusing function.Improve the image quality, intelligent level, integrated degree of visual light imaging component.
Description
Technical field
The invention belongs to the image processing circuit of Airborne Electro-optical Detecting System, is related to a kind of pipeline system zero propagation extraction
The logic circuit and extracting method of image sharpness information.
Background technology
The Airborne Electro-optical Detecting System of integrated visual light imaging device, mesh is adjusted and is detected by Visible Light Camera field angle
The factors such as target distance change influence, often can not blur-free imaging.The reason for causing this phenomenon be, camera lens it is optimal
Imaging target surface and CCD photosurfaces are misaligned, i.e., do not focus accurately.Existing measure is that a hand is carried out in system initialization
Dynamic focusing；In the normal detection process of system, run into fuzzy pictures it is unclear when, then carry out focusing compensation manually.Existing measure
Inferior position includes, and lacks evaluation criterion whether the subjective judgement of heavy dependence operating personnel, response speed are slow, focusing is accurate.Grasping
Make personnel and handle the multi-task or during violent detected target distance change, often miss an opportunity because of a delay, result even in target with
Track fails.Therefore be badly in need of it is a kind of unattended, automation to focal compensation process, complete initialization auto-focusing, in real time from
Dynamic servo focusing and a key auto-focusing.A key technology therein, is to extract sharpness information from image zero propagation, with
This given input as auto-focusing control loop.
Airborne Electro-optical Detecting System is the important component of avionics system, it utilizes itself of object (target and background)
The physical features that radiation or reflection visible ray are embodied, by automatic or manual judgement target, realize detection, the identification to target
And tracking, during accurately being tracked to target, the characteristic information of target relative movement is obtained in real time, there is provided to weapon system
Resolved.It is the complication system of multinomial technological synthesis, mainly including optical component, ray machine frame parts, visual light imaging
Component, infrared imaging component, laser part, servo control components, information processing apparatus, the automatic tracking unit of image and system control
Component processed etc..Compared with radar, Airborne Electro-optical Detecting System has passive detection, acquisition target is more life-like, detection accuracy is high
The advantages of.
The content of the invention
Technical problems to be solved
In order to avoid the shortcomings of the prior art, the present invention proposes a kind of pipeline system zero propagation extraction image sharpness
The logic circuit and extracting method of information, suitable for Airborne Electro-optical Detecting System, pipeline system, zero propagation extract image
Sharpness information.
Technical solution
A kind of logic circuit of pipeline system zero propagation extraction image sharpness information, it is characterised in that：Can using scene
Gate array FPGA is programmed, logic circuit is divided into：Pixel coordinate resolution logic circuit, pixel value row buffering logic circuit, figure
As acutance computing flip-flop logic circuit, Pixel-level acutance arithmetic logic circuit and image level acutance accumulation logic circuit；
Pixel coordinate resolution logic circuit receives the field sync signal sum number of upper level visible light video Acquisition Circuit output
According to id signal, row coordinate and row coordinate data are exported to image sharpness computing trigger logic after parsing current pixel coordinate value
Circuit；The pixel coordinate resolution logic circuit uses audio video synchronization clock signal PCLK flip-flop numbers, believes in VSYNC and DE
Number effectively i.e. logical one when, be incremented by the row coordinate value (x=x+1) of pixel；
Image sharpness computing flip-flop logic circuit contrasts current pixel coordinate value and presetting acutance zoning
Trigger signal is exported to Pixel-level acutance arithmetic logic circuit and image level acutance accumulation logic circuit at the same time afterwards；
Pixel value row buffering logic circuit receives the video data stream of upper level visible light video Acquisition Circuit output, ought
Preceding pixel gray scale, LIN1 data and LIN2 data are exported to Pixel-level acutance arithmetic logic circuit jointly；The pixel value row delays
Rush logic circuit to build using 2 string formation line shift register queue LIN1, LIN2, the number of pixels that each column length and image are often gone
Identical, the data depth of register is identical with the data depth of pixel grey scale；The data input pin of LIN1 receives current pixel ash
Degree, the data input pin of LIN2 connect the output terminal of LIN1；The displacement of data is triggered by audio video synchronization clock signal PCLK；Current picture
Plain gray scale output terminal, LIN1 data output ends, LIN2 data output ends collectively constitute output port；
Pixel-level acutance arithmetic logic circuit was controlled by computing trigger signal, in each audio video synchronization clock signal PCLK weeks
In phase, a data displacement is completed to received signal and once-through operation is exported to image level acutance accumulation logic circuit；It is described
Pixel-level acutance arithmetic logic circuit uses 3x3 mask matrixes；
Image level acutance accumulation logic circuit is when computing trigger signal is effective, in each audio video synchronization clock signal PCLK
In cycle, one-accumulate computing is completed to received signal and is exported；When computing trigger signal is invalid, output is latched；The figure
As level acutance accumulation logic circuit uses accumulator.
A kind of logic circuit extraction image sharpness letter using pipeline system zero propagation extraction image sharpness information
The method of breath, it is characterised in that step is as follows：
Step 1：
The clock signal provided using image/video source parses current pixel coordinate value：Using field sync signal VSYNC's
It is x=1, y=1 that rising edge, which marks the origin coordinates of a new two field picture,；New using the rising edge mark of Data Identification signal DE
One-row pixels：Row coordinate y=y+1, row coordinate x=1；Using audio video synchronization clock signal PCLK flip-flop numbers, in VSYNC and
DE signals are effective, during logical one, are incremented by the row coordinate value x=x+1 of pixel；
To pixel value row buffering：The data input pin of LIN1 receives current pixel gray scale, and the data input pin of LIN2 connects
The output terminal of LIN1；The displacement of data is triggered by audio video synchronization clock signal PCLK；Current pixel gray scale output terminal, LIN1 data
Output terminal, LIN2 data output ends export jointly；
Step 2, contrast current pixel coordinate value and presetting acutance zoning ROI, if coordinate value falls into ROI models
In enclosing, trigger signal, i.e. logical one are exported；
Step 3, Pixel-level acutance computing：, will be current using 3x3 edge detection operators when computing trigger signal arrives
Pixel grey scale output terminal, LIN1 data output ends, LIN2 data, within each audio video synchronization clock signal PCLK cycles, are completed
Data displacement and once-through operation；
Step 4：To the data of step 3 displacement and once-through operation, when computing trigger signal is effective, in each audio video synchronization
In the clock signal PCLK cycles, carry out one-accumulate computing and export；When computing trigger signal is invalid, output is latched.
Beneficial effect
The logic circuit and extracting method of a kind of pipeline system zero propagation extraction image sharpness information proposed by the present invention,
Using hardware realization platform of the field programmable gate array (FPGA) as image procossing, logic circuit is divided into：Pixel is sat
Mark resolution logic circuit, pixel value row buffering logic circuit, image sharpness computing flip-flop logic circuit, Pixel-level acutance computing
5 parts such as logic circuit, image level acutance accumulation logic circuit, carry out test encapsulation, then carry out Two-level ensemble encapsulation respectively.Profit
With the clock signal being superimposed on HD video source, the coordinated indexing value of real-time reconstruction image pixel, controls for follow-up triggering
Logic；By multichannel buffer queue mode, view data is grouped again, pipelines follow-up processing.By ought
Preceding pixel coordinated indexing value value is contrasted with presetting acutance zoning (ROI), outwards exports computing trigger signal.Pass through figure
As the edge detection operator (including but are not limited to Laplace operators, sobel operators, canny operators) of space field operation, construction
3x3 sliding window matrixes, under clock and the control of computing trigger signal, the multichannel buffer queue to flowing water input performs linearly
Computing and the sharpness information for exporting single pixel.Using synchronised clock accumulator, pixel sharpness information is received, and by whole two field picture
Pixel acutance in area-of-interest (ROI) adds up and latches output.
The present invention can apply the image processing circuit of different type Airborne Electro-optical Detecting System visual light imaging component, complete
, to the abstraction function of the image sharpness information of HD video, meet airborne detection under the conditions of big data quantity, hard real-time constraints
Auto-focusing demand in the big focal range of equipment visibility light camera.By designing, emulating, verifying, modular standard is formed
Product, for different HD video forms, image ROI region, image space field operation parameter, can be used with minor modifications.This
Invention and its association invention realize the total solution of Visible Light Camera auto-focusing.By collecting in camera control platform
Into the logic circuit, real-time servo auto-focusing and the key focusing of Airborne Electro-optical Detecting System are realized.
The beneficial effects of the invention are as follows：
(1) Airborne Electro-optical Detecting System is made to realize the acquisition of image sharpness information, and before possessing automatic focusing function
Put forward condition.
(2) improve the image quality, intelligent level, integrated degree of visual light imaging component.
Brief description of the drawings
Fig. 1 is the general frame and signal interconnection schematic diagram of the present invention
Fig. 2 is the pixel row buffering and acutance calculation logic circuit schematic diagram of core in the present invention
Fig. 3 is final carrier --- the composition frame chart of Airborne Electro-optical Detecting System that the present invention is implemented
Fig. 4 is direct carrier --- the composition frame chart of visual light imaging component that the present invention is implemented
Embodiment
In conjunction with embodiment, attached drawing, the invention will be further described：
The visible light video source of certain type airborne photoelectric detection device uses high definition SDI forms, it is seen that before photoimaging component
End configuration visible light video Acquisition Circuit, the digital focusing control circuit of backend arrangement, interlude implement of the present invention patrol
Collect circuit.Automatic focusing function is needed from being completed with the associated relative program software of the present invention.
The embodiment of the present invention forms：Pixel coordinate resolution logic circuit, pixel value row buffering logic circuit, image sharpness
Computing flip-flop logic circuit, Pixel-level acutance arithmetic logic circuit, image level acutance accumulation logic circuit, it is characterised in that：
Realized based on FPGA hardware description language synthesis, cache pixel using modular design method, using multigroup serial shift queue
Half-tone information, pipeline system calculate the sharpness information of each pixel, the acutance using unified triggering timing synchronization Pixel-level
Calculate and the acutance of entire image calculates.
According to the general frame shown in Fig. 1 and signal interconnecting relation, each logic circuit is integrated together：
The output signal (row coordinate, row coordinate) of pixel coordinate resolution logic circuit connects image sharpness computing trigger logic
Circuit；
The output signal (computing trigger signal) of image sharpness computing flip-flop logic circuit is respectively connected to pixel value row and delays
Rush logic circuit and image level acutance accumulation logic circuit；
The output end signal (buffering queue 1, buffering queue 2, buffering queue 3) of pixel value row buffering logic circuit connects pixel
Level acutance arithmetic logic circuit；
The output signal (pixel acutance) of Pixel-level acutance arithmetic logic circuit connects image level acutance accumulation logic circuit；
The pixel coordinate resolution logic circuit：Sat based on the clock signal parsing current pixel that image/video source provides
Scale value, specially marks the origin coordinates (x=1, y=1) of a new two field picture using the rising edge of field sync signal (VSYNC)；
New one-row pixels (row coordinate y=y+1, row coordinate x=1) are marked using the rising edge of Data Identification signal (DE)；Using regarding
Frequency synchronizing clock signals (PCLK) flip-flop number, at VSYNC and DE signals effectively (logical one), is incremented by the row of pixel
Coordinate value (x=x+1).
The pixel value row buffering logic circuit：Built using 2 string formation line shift register queue LIN1, LIN2, often
The number of pixels that row length and image are often gone is identical, and the data depth of register is identical with the data depth of pixel grey scale；LIN1
Data input pin receive current pixel gray scale, the data input pin of LIN2 connects the output terminal of LIN1；The displacement of data is by video
Synchronizing clock signals (PCLK) trigger；Current pixel gray scale output terminal, LIN1 data output ends, common group of LIN2 data output ends
Into output port, Pixel-level acutance arithmetic logic circuit is terminated.
The image sharpness computing flip-flop logic circuit：Current pixel coordinate value and presetting acutance are calculated into area
Domain (ROI) contrasts, if coordinate value is fallen into the range of ROI, exports trigger signal (logical one).
The Pixel-level acutance arithmetic logic circuit：Using 3x3 edge detection operators, computing mask is formed；By computing
Trigger signal controls, and each audio video synchronization clock signal (PCLK) completes a data displacement and once-through operation in the cycle.
The picture image level acutance accumulation logic circuit：Realized using accumulator；When computing trigger signal is effective, each
Audio video synchronization clock signal (PCLK) is completed one-accumulate computing and is exported in the cycle；When computing trigger signal is invalid, latch defeated
Go out.
According to the interconnecting relation shown in Fig. 3, the logic circuit after integrating is embedded in camera automatic focusing module：
It will be seen that the output signal (field sync signal, Data Identification signal, video data stream) of light video capture circuit connects
The input terminal of integrated logic circuit；
The output end signal (image sharpness) of integrated logic circuit is connect into digital focusing control circuit.
The present invention is embodied in visual light imaging component, can be completed in the detection front end of system to image clearly journey
The real-time estimation (sharpness information) of degree, and coordinate digital control circuit and electromechanical actuator, it is automatically performed photodetection portion
The lifting of part image quality.
Claims (2)
- A kind of 1. logic circuit of pipeline system zero propagation extraction image sharpness information, it is characterised in that：It can be compiled using scene Journey gate array FPGA, logic circuit is divided into：Pixel coordinate resolution logic circuit, pixel value row buffering logic circuit, image Acutance computing flip-flop logic circuit, Pixel-level acutance arithmetic logic circuit and image level acutance accumulation logic circuit；Pixel coordinate resolution logic circuit receives the field sync signal and data mark of upper level visible light video Acquisition Circuit output Know signal, row coordinate and row coordinate data are exported to image sharpness computing trigger logic electricity after parsing current pixel coordinate value Road；The pixel coordinate resolution logic circuit uses audio video synchronization clock signal PCLK flip-flop numbers, in VSYNC and DE signals When being effectively logical one, it is incremented by the row coordinate value (x=x+1) of pixel；Image sharpness computing flip-flop logic circuit is same after current pixel coordinate value is contrasted with presetting acutance zoning When export trigger signal to Pixel-level acutance arithmetic logic circuit and image level acutance accumulation logic circuit；Pixel value row buffering logic circuit receives the video data stream of upper level visible light video Acquisition Circuit output, by current picture Plain gray scale, LIN1 data and LIN2 data are exported to Pixel-level acutance arithmetic logic circuit jointly；The pixel value row buffering is patrolled Volume circuit is built using 2 string formation line shift register queue LIN1, LIN2, the number of pixels phase that each column length and image are often gone Together, the data depth of register and the data depth of pixel grey scale are identical；The data input pin of LIN1 receives current pixel gray scale, The data input pin of LIN2 connects the output terminal of LIN1；The displacement of data is triggered by audio video synchronization clock signal PCLK；Current pixel Gray scale output terminal, LIN1 data output ends, LIN2 data output ends collectively constitute output port；Pixel-level acutance arithmetic logic circuit is controlled by computing trigger signal, in each audio video synchronization clock signal PCLK cycles It is interior, a data displacement is completed to received signal and once-through operation is exported to image level acutance accumulation logic circuit；The picture Plain level acutance arithmetic logic circuit uses 3x3 mask matrixes；Image level acutance accumulation logic circuit is when computing trigger signal is effective, in each audio video synchronization clock signal PCLK cycles It is interior, one-accumulate computing is completed to received signal and is exported；When computing trigger signal is invalid, output is latched；Described image level Acutance accumulation logic circuit uses accumulator.
- 2. a kind of logic circuit using pipeline system zero propagation extraction image sharpness information described in claim 1 extracts image The method of sharpness information, it is characterised in that step is as follows：Step 1：The clock signal provided using image/video source parses current pixel coordinate value：Using the rising of field sync signal VSYNC Origin coordinates along the new two field picture of mark is x=1, y=1；New a line is marked using the rising edge of Data Identification signal DE Pixel：Row coordinate y=y+1, row coordinate x=1；Using audio video synchronization clock signal PCLK flip-flop numbers, believe in VSYNC and DE Number effectively, during logical one, it is incremented by the row coordinate value x=x+1 of pixel；To pixel value row buffering：The data input pin of LIN1 receives current pixel gray scale, and the data input pin of LIN2 connects LIN1's Output terminal；The displacement of data is triggered by audio video synchronization clock signal PCLK；Current pixel gray scale output terminal, the output of LIN1 data End, LIN2 data output ends export jointly；Step 2, contrast current pixel coordinate value and presetting acutance zoning ROI, if coordinate value falls into ROI scopes It is interior, export trigger signal, i.e. logical one；Step 3, Pixel-level acutance computing：When computing trigger signal arrives, using 3x3 edge detection operators, by current pixel Gray scale output terminal, LIN1 data output ends, LIN2 data, within each audio video synchronization clock signal PCLK cycles, are completed once Data displacement and once-through operation；Step 4：To the data of step 3 displacement and once-through operation, when computing trigger signal is effective, in each audio video synchronization clock In the signal PCLK cycles, carry out one-accumulate computing and export；When computing trigger signal is invalid, output is latched.
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| CN201711200081.XA CN107911605B (en) | 2017-11-27 | 2017-11-27 | Logic circuit for zero-delay extraction of image sharpness information in pipeline mode and extraction method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110991609A (en) * | 2019-11-27 | 2020-04-10 | 天津大学 | Line buffer for improving data transmission efficiency |
| CN111984058A (en) * | 2020-07-17 | 2020-11-24 | 中国科学院计算技术研究所 | Microprocessor system based on superconducting SFQ circuit and arithmetic device thereof |
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| CN103426159A (en) * | 2012-05-23 | 2013-12-04 | 华为技术有限公司 | Multi-dimensional histogram statistic circuit and image processing system |
| CN105608662A (en) * | 2015-12-31 | 2016-05-25 | 哈尔滨工程大学 | FPGA-based dynamic target identification system and identification method thereof |
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| US6009531A (en) * | 1995-08-10 | 1999-12-28 | Ikos Systems, Inc. | Transition analysis and circuit resynthesis method and device for digital circuit modeling |
| CN103426159A (en) * | 2012-05-23 | 2013-12-04 | 华为技术有限公司 | Multi-dimensional histogram statistic circuit and image processing system |
| CN105608662A (en) * | 2015-12-31 | 2016-05-25 | 哈尔滨工程大学 | FPGA-based dynamic target identification system and identification method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110991609A (en) * | 2019-11-27 | 2020-04-10 | 天津大学 | Line buffer for improving data transmission efficiency |
| CN110991609B (en) * | 2019-11-27 | 2023-12-26 | 天津大学 | Line buffer for data transmission |
| CN111984058A (en) * | 2020-07-17 | 2020-11-24 | 中国科学院计算技术研究所 | Microprocessor system based on superconducting SFQ circuit and arithmetic device thereof |
| CN111984058B (en) * | 2020-07-17 | 2023-04-25 | 中国科学院计算技术研究所 | Microprocessor system based on superconducting SFQ circuit and operation device thereof |
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